diff options
| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2017-11-28 16:51:07 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2017-12-11 11:36:22 +0300 |
| commit | 64f47426315112e67af1214474659e0a55383dcc (patch) | |
| tree | 4d743182183d0f59a12178faae834ead03a99923 | |
| parent | e59c3797204b4cd565c0792620341e3d39f9240b (diff) | |
ARC: add defines of some cache and xCCM AUX registers
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| -rw-r--r-- | arch/arc/include/asm/arcregs.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 2a1bfc74ec..ba1f7bac77 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -27,6 +27,12 @@ #define ARC_AUX_IC_PTAG 0x1E #endif #define ARC_BCR_IC_BUILD 0x77 +#define AUX_AUX_CACHE_LIMIT 0x5D +#define ARC_AUX_NON_VOLATILE_LIMIT 0x5E + +/* ICCM and DCCM auxiliary registers */ +#define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */ +#define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */ /* Timer related auxiliary registers */ #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ |