diff options
| author | Andy Fleming <afleming@freescale.com> | 2008-05-07 16:54:31 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-05-07 16:54:31 -0500 |
| commit | 66f5fa9263629271edc86178b1f224e3c9aab2b3 (patch) | |
| tree | e7265ee835d7a1b2ccd11f85a362645d91453756 | |
| parent | 908261f3fdb418091d8c60bfbd7eb85e5869b579 (diff) | |
85xx: Limit CPU2 workaround to parts that have the errata
Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
| -rw-r--r-- | board/freescale/mpc8548cds/mpc8548cds.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index dc39fbe8dc..efe2a3a3de 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -59,6 +59,7 @@ int checkboard (void) uint pci_slot = get_pci_slot (); uint cpu_board_rev = get_cpu_board_revision (); + uint svr; printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", get_board_version (), pci_slot); @@ -71,12 +72,16 @@ int checkboard (void) */ local_bus_init (); + svr = get_svr(); + /* * Fix CPU2 errata: A core hang possible while executing a * msync instruction and a snoopable transaction from an I/O * master tagged to make quick forward progress is present. + * Fixed in Silicon Rev.2.1 */ - ecm->eebpcr |= (1 << 16); + if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1)) + ecm->eebpcr |= (1 << 16); /* * Hack TSEC 3 and 4 IO voltages. |