diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2015-09-08 17:07:01 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2015-11-19 14:03:05 +0100 |
| commit | 6777f3863044bf58082a3fdd67a890f2b5080e14 (patch) | |
| tree | 16507228d3b767be0d3ef7d02c0fcf9b1687dda8 | |
| parent | 2889659a5510558f55c50c51a29bd701792536fd (diff) | |
net: zynq: Fix MDC setting for zynq
Based on spec:
"MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and
write operations)"
Zynq is running on 111MHz. Current setting is 32 which is 111/32=3.47
which is above of 2.5MHz.
Using 48 divider will give us correct setting according spec
(111/48=2.31).
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| -rw-r--r-- | drivers/net/zynq_gem.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 4db3ed4339..858093f0d7 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -58,7 +58,7 @@ #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ -#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ +#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */ #ifdef CONFIG_ARM64 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ |