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authorEgli, Samuel <samuel.egli@siemens.com>2015-12-02 15:27:56 +0100
committerTom Rini <trini@konsulko.com>2015-12-12 15:56:09 -0500
commit69b918b65d11d030ff39dcc9b5f4d4605cd23c7f (patch)
treece64508f6a2a3ff19226366c52b41875f442455c
parentb3b522f247d3f19c4f2309ab0e6a02b3dd82de45 (diff)
am33xx,ddr3: fix ddr3 sdram configuration
This patch fixes the DDR3 initialization procedure in order to comply with DDR3 standard. A 500 us delay is specified between the DDR3 reset and clock enable signal. Until now, this delay was not respected. Some DDR3 chips don't bother but the bigger the RAM becomes the more likely it seems that this delay is needed. We observed that DRAM > 256 MB from the manufacturer Samsung have an issue when the specification is not respected. Changes: 1) Add a 1 ms wait for L3 timeout error trigger 2) Don't delay DDR3 initialization Bit 31 of emif_sdram_ref_ctrl shouldn't be set because his suppresses the initialization of DDR3 Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Reviewed-by: James Doublesin <doublesin@ti.com> Cc: Tom Rini <trini@konsulko.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Roger Meier <r.meier@siemens.com> Cc: Heiko Schocher <hs@denx.de>
-rw-r--r--arch/arm/cpu/armv7/am33xx/ddr.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index b3fb0c47ab..888cf1f732 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -164,6 +164,13 @@ void config_sdram(const struct emif_regs *regs, int nr)
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+
+ /* Trigger initialization */
+ writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
+ /* Wait 1ms because of L3 timeout error */
+ udelay(1000);
+
+ /* Write proper sdram_ref_cref_ctrl value */
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
}
@@ -292,7 +299,9 @@ void config_ddr_phy(const struct emif_regs *regs, int nr)
EMIF_REG_INITREF_DIS_MASK);
#endif
if (regs->zq_config)
- writel(0x80003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
+ /* Set time between rising edge of DDR_RESET to rising
+ * edge of DDR_CKE to > 500us per memory spec. */
+ writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->emif_ddr_phy_ctlr_1,
&emif_reg[nr]->emif_ddr_phy_ctrl_1);