diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2008-10-14 00:31:30 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-02-02 12:23:20 -0500 |
| commit | 6b310a05f0d10c751f22468040932139f71c71d3 (patch) | |
| tree | 84eb5b4baea7aa5e18982c51fb18301c86b2de9c | |
| parent | 6c6e042ab3bbfb5428e4cdeb38fa27728c63afdd (diff) | |
Blackfin: bfin_mac: set MDCDIV based on SCLK
Rather than hardcoding MDCDIV to 24 (which is correct for ~125mhz SCLK),
use the real algorithm so it gets set correctly regardless of SCLK.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
| -rw-r--r-- | drivers/net/bfin_mac.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index dddbb78b1c..a620fcc138 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -323,9 +323,12 @@ static void SoftResetPHY(void) } #endif +/* MDC = SCLK / MDC_freq / 2 - 1 */ +#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1) + static int SetupSystemRegs(int *opmode) { - u16 sysctl, phydat; + u16 phydat; int count = 0; /* Enable PHY output */ *pVR_CTL |= CLKBUFOE; @@ -368,12 +371,9 @@ static int SetupSystemRegs(int *opmode) # endif #endif - /* MDC = 2.5 MHz */ - sysctl = SET_MDCDIV(24); /* Odd word alignment for Receive Frame DMA word */ /* Configure checksum support and rcve frame word alignment */ - sysctl |= RXDWA | RXCKS; - *pEMAC_SYSCTL = sysctl; + *pEMAC_SYSCTL = RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(2500000)); /* auto negotiation on */ /* full duplex */ /* 100 Mbps */ |