diff options
| author | York Sun <yorksun@freescale.com> | 2014-02-10 13:59:43 -0800 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-02-21 11:06:13 -0500 |
| commit | 6b9e309a8a7f0f33252288f0ed8794a83a488301 (patch) | |
| tree | 24ace80dceeb3c6e184bc4eb39529de5379b57b2 | |
| parent | 4e5b1bd0dff216b00d7ce9a5201dfe173805a06c (diff) | |
Driver/ddr: Add support of different DDR base address
DDR base address has been the same from the view of core and DDR
controllers. This has changed for Freescale ARM-based SoCs. Controllers
setup DDR memory in a contiguous space and cores view it at separated
locations.
Signed-off-by: York Sun <yorksun@freescale.com>
| -rw-r--r-- | README | 5 | ||||
| -rw-r--r-- | drivers/ddr/fsl/main.c | 16 |
2 files changed, 19 insertions, 2 deletions
@@ -492,6 +492,11 @@ The following options need to be configured: CONFIG_SYS_FSL_DDR_LE Defines the DDR controller register space as Little Endian + CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY + Physical address from the view of DDR controllers. It is the + same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But + it could be different for ARM SoCs. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index d0cd58925c..dee50a0789 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -17,6 +17,18 @@ #include <fsl_ddr_sdram.h> #include <fsl_ddr.h> +/* + * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view + * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for + * all Power SoCs. But it could be different for ARM SoCs. For example, + * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of + * 0x00_8000_0000 ~ 0x00_ffff_ffff + * 0x80_8000_0000 ~ 0xff_ffff_ffff + */ +#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE +#endif + #ifdef CONFIG_PPC #include <asm/fsl_law.h> @@ -255,7 +267,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); } - current_mem_base = CONFIG_SYS_DDR_SDRAM_BASE; + current_mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; total_mem = 0; if (pinfo->memctl_opts[0].memctl_interleaving) { rank_density = pinfo->dimm_params[0][0].rank_density >> @@ -536,7 +548,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, } total_mem = 1 + (((unsigned long long)max_end << 24ULL) | - 0xFFFFFFULL) - CONFIG_SYS_DDR_SDRAM_BASE; + 0xFFFFFFULL) - CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; } return total_mem; |