diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2013-11-26 17:45:26 +0000 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2013-11-26 21:49:25 +0100 |
| commit | 72117dadcbbdffda447daa1e26b4cc4007f61160 (patch) | |
| tree | ede34c81c3da5aaab8fbc0fad22d8bb714e932cd | |
| parent | d18d49d7ad77f1a97b9697b3761802de5b82983d (diff) | |
malta: correct UART baudrate
CONFIG_SYS_NS16550_CLK specifies the rate of the clock 16x the baud
rate. The SMSC FDC37M81x datasheet states that a divider of 1 results in
a UART at 115200 baud, thus the x16 clock rate is 115200 * 16.
Previously the divider was left at 0 which led to a rate of 38400 baud
regardless of CONFIG_BAUDRATE or the baudrate environment variable.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| -rw-r--r-- | include/configs/malta.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/malta.h b/include/configs/malta.h index 458c33a586..666cca99a4 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -80,7 +80,7 @@ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 115200 +#define CONFIG_SYS_NS16550_CLK (115200 * 16) #define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_GT_UART0_BASE) #define CONFIG_SYS_NS16550_COM2 CKSEG1ADDR(MALTA_MSC01_UART0_BASE) #define CONFIG_CONS_INDEX 1 |