diff options
| author | Xu Ziyuan <xzy.xu@rock-chips.com> | 2017-04-16 17:44:44 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2017-05-10 13:37:21 -0600 |
| commit | 7a25a63c134f9fdc1e977ca7d6c8f1ddda6103e5 (patch) | |
| tree | d725342d9a59d1706de59a18ae00ef4e35075319 | |
| parent | 7f0cfe478bd817d2bb373522222cf06630fea3cd (diff) | |
rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO
The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3188.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index d36cf8f3f2..b32491d3db 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -269,14 +269,17 @@ static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate, switch (periph) { case HCLK_EMMC: + case SCLK_EMMC: con = readl(&cru->cru_clksel_con[12]); div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; break; case HCLK_SDMMC: + case SCLK_SDMMC: con = readl(&cru->cru_clksel_con[11]); div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; break; case HCLK_SDIO: + case SCLK_SDIO: con = readl(&cru->cru_clksel_con[12]); div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK; break; @@ -298,16 +301,19 @@ static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate, switch (periph) { case HCLK_EMMC: + case SCLK_EMMC: rk_clrsetreg(&cru->cru_clksel_con[12], EMMC_DIV_MASK << EMMC_DIV_SHIFT, src_clk_div << EMMC_DIV_SHIFT); break; case HCLK_SDMMC: + case SCLK_SDMMC: rk_clrsetreg(&cru->cru_clksel_con[11], MMC0_DIV_MASK << MMC0_DIV_SHIFT, src_clk_div << MMC0_DIV_SHIFT); break; case HCLK_SDIO: + case SCLK_SDIO: rk_clrsetreg(&cru->cru_clksel_con[12], SDIO_DIV_MASK << SDIO_DIV_SHIFT, src_clk_div << SDIO_DIV_SHIFT); @@ -466,6 +472,9 @@ static ulong rk3188_clk_get_rate(struct clk *clk) case HCLK_EMMC: case HCLK_SDMMC: case HCLK_SDIO: + case SCLK_EMMC: + case SCLK_SDMMC: + case SCLK_SDIO: new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ, clk->id); break; @@ -505,6 +514,9 @@ static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate) case HCLK_EMMC: case HCLK_SDMMC: case HCLK_SDIO: + case SCLK_EMMC: + case SCLK_SDMMC: + case SCLK_SDIO: new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, clk->id, rate); break; |