diff options
| author | Aneesh Bansal <aneesh.bansal@nxp.com> | 2016-04-18 22:58:33 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-05-24 10:31:21 -0700 |
| commit | 82eda68444fa4d026bcf1f59c7c0d044ddbcb193 (patch) | |
| tree | df6f6a6af8f690c3acc04ce23ad868ca700c3535 | |
| parent | 46caebc1dff8f456b4f076bbebbb2ba32236d06d (diff) | |
powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache
While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
error checking enable) must not be changed while the L2 cache is
enabled.
So, L2PE must be set before enabling L2 cache.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 82a151a0d0..4c51225868 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -720,16 +720,39 @@ enable_l2_cluster_l2: ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l sync stw r4, 0(r3) /* invalidate L2 */ + /* Poll till the bits are cleared */ 1: sync lwz r0, 0(r3) twi 0, r0, 0 isync and. r1, r0, r4 bne 1b + + /* L2PE must be set before L2 cache is enabled */ + lis r4, (L2CSR0_L2PE)@h + ori r4, r4, (L2CSR0_L2PE)@l + sync + stw r4, 0(r3) /* enable L2 parity/ECC error checking */ + /* Poll till the bit is set */ +1: sync + lwz r0, 0(r3) + twi 0, r0, 0 + isync + and. r1, r0, r4 + beq 1b + lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h ori r4, r4, (L2CSR0_L2REP_MODE)@l sync stw r4, 0(r3) /* enable L2 */ + /* Poll till the bit is set */ +1: sync + lwz r0, 0(r3) + twi 0, r0, 0 + isync + and. r1, r0, r4 + beq 1b + delete_ccsr_l2_tlb: delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3 #endif |