x86: coreboot: Add default TSC frequency in the device tree

It was observed sometimes U-Boot as the coreboot payload fails to
boot on QEMU. This is because TSC calibration fails with no valid
frequency. This adds default TSC frequency in the device tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
index a94f781833..e212f3dc7d 100644
--- a/arch/x86/dts/coreboot.dts
+++ b/arch/x86/dts/coreboot.dts
@@ -30,6 +30,10 @@
 		stdout-path = "/serial";
 	};
 
+	tsc-timer {
+		clock-frequency = <1000000000>;
+	};
+
 	pci {
 		compatible = "pci-x86";
 		u-boot,dm-pre-reloc;