diff options
| author | Simon Glass <sjg@chromium.org> | 2019-12-06 21:42:26 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2019-12-15 11:44:18 +0800 |
| commit | 86a8fb3b3b45523744d23626e419f72b7e201da8 (patch) | |
| tree | f573c4b298d994e7d64e8ee8ced49c1b181148b6 | |
| parent | f45e747d6d0b107992e8aed74c001034c8a6f1a1 (diff) | |
x86: Disable microcode section for FSP2
At present we don't support loading microcode with FSP2. The correct way
to do this is by adding it to the FIT. For now, disable including
microcode in the image.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| -rw-r--r-- | arch/x86/Kconfig | 4 | ||||
| -rw-r--r-- | arch/x86/dts/u-boot.dtsi | 7 |
2 files changed, 11 insertions, 0 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 44f7f0ab03..64f167306b 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -588,6 +588,10 @@ config HAVE_REFCODE broadwell) U-Boot will be missing some critical setup steps. Various peripherals may fail to work. +config HAVE_MICROCODE + bool + default y if !FSP_VERSION2 + config SMP bool "Enable Symmetric Multiprocessing" default n diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 33441c7c80..850fe3ac11 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -37,11 +37,13 @@ }; #endif #ifdef CONFIG_TPL +#ifdef CONFIG_HAVE_MICROCODE u-boot-tpl-with-ucode-ptr { offset = <CONFIG_TPL_TEXT_BASE>; }; u-boot-tpl-dtb { }; +#endif u-boot-spl { offset = <CONFIG_SPL_TEXT_BASE>; }; @@ -77,11 +79,16 @@ offset = <CONFIG_SYS_TEXT_BASE>; }; #endif +#ifdef CONFIG_HAVE_MICROCODE u-boot-dtb-with-ucode { }; u-boot-ucode { align = <16>; }; +#else + u-boot-dtb { + }; +#endif #ifdef CONFIG_HAVE_X86_FIT intel-fit { }; |