diff options
| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2014-04-08 19:13:34 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-04-22 17:58:51 -0700 |
| commit | 89ad7be8e713f33ec677cf4576e0c9b0ed83f7c6 (patch) | |
| tree | 4cc2d7b402e94354e4928d4da9dedc8dbceb53e0 | |
| parent | 1eaa742d85a59ed3602a78445adf903f26d9b594 (diff) | |
Makefile: Add support of CONFIG_SPL_FSL_PBL
Objective of this target to have concatenate binary having
- SPL binary in PBL command format
- U-boot binary
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
| -rw-r--r-- | Makefile | 19 | ||||
| -rw-r--r-- | README | 4 |
2 files changed, 23 insertions, 0 deletions
@@ -740,7 +740,11 @@ ALL-y += u-boot.srec u-boot.bin System.map ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin +ifeq ($(CONFIG_SPL_FSL_PBL),y) +ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin +else ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl +endif ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin @@ -925,6 +929,21 @@ endif u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE $(call if_changed,cat) +#Add a target to create boot binary having SPL binary in PBI format +#concatenated with u-boot binary. It is need by PowerPC SoC having +#internal SRAM <= 512KB. +MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ + -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage + +spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) + +OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ + --gap-fill=0xff + +u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl u-boot.bin FORCE + $(call if_changed,pad_cat) + # PPC4xx needs the SPL at the end of the image, since the reset vector # is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target # and need to introduce a new build target with the full blown U-Boot @@ -505,6 +505,10 @@ The following options need to be configured: PBI commands can be used to configure SoC before it starts the execution. Please refer doc/README.pblimage for more details + CONFIG_SPL_FSL_PBL + It adds a target to create boot binary having SPL binary in PBI format + concatenated with u-boot binary. + CONFIG_SYS_FSL_DDR_BE Defines the DDR controller register space as Big Endian |