diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2017-08-31 21:57:48 +0800 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2017-09-01 19:49:47 +0530 |
| commit | 8a647fc3ca2a93e2b6c965999ac2e0316191a755 (patch) | |
| tree | 1d88fa393639b8161eeddb1c3968798a436e3099 | |
| parent | ead3697d7ec491c055fe546b3a45bcfba45fa022 (diff) | |
mmc: sunxi: Only update timing mode bit when enabling new timing mode
When enabling the new mmc timing mode, we inadvertently clear all the
remaining bits in the new timing mode register. The bits cleared
include a default phase delay on the output clock. The BSP kernel
states that the default values are supposed to be used. Clearing them
results in decreased performance or transfer errors on some boards.
Fixes: de9b1771c3b6 ("mmc: sunxi: Support new mode")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
| -rw-r--r-- | drivers/mmc/sunxi_mmc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index a76e763bfd..4edb4be46c 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -167,7 +167,7 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) if (new_mode) { #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE val = CCM_MMC_CTRL_MODE_SEL_NEW; - writel(SUNXI_MMC_NTSR_MODE_SEL_NEW, &priv->reg->ntsr); + setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW); #endif } else { val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | |