Blackfin: pr1: new board port

This add support for the PR1 Appliance - Asterisk based ISDN PRI PBX.
This board is Blackfin BF537 based.  The schematics are not fully opened.

Signed-off-by: Dimitar Penev <dpn@switchfin.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

6 files changed, 272 insertions, 0 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index 8c4fe2df8d..4451ecd9a3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1162,6 +1162,10 @@ Chong Huang <chuang@ucrobotics.com>
 
 	bf525-ucr2	BF525
 
+Dimitar Penev <dpn@switchfin.org>
+
+	PR1 Appliance	BF537
+
 #########################################################################
 # NDS32 Systems:							#
 #									#
diff --git a/board/pr1/Makefile b/board/pr1/Makefile
new file mode 100644
index 0000000000..6ae998fcf8
--- /dev/null
+++ b/board/pr1/Makefile
@@ -0,0 +1,50 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) Switchfin Org. <dpn@switchfin.org>
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/pr1/config.mk b/board/pr1/config.mk
new file mode 100644
index 0000000000..fac20c538a
--- /dev/null
+++ b/board/pr1/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright (c) Switchfin Org. <dpn@switchfin.org>
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+CFLAGS_lib/zlib += -O2
diff --git a/board/pr1/pr1.c b/board/pr1/pr1.c
new file mode 100644
index 0000000000..bb907f3966
--- /dev/null
+++ b/board/pr1/pr1.c
@@ -0,0 +1,30 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) Switchfin Org. <dpn@switchfin.org>
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+
+int checkboard(void)
+{
+	printf("Board: Switchvoice PR1 Appliance\n");
+	printf("       Support: http://www.switchvoice.com/\n");
+	return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+int board_eth_init(bd_t *bis)
+{
+	return bfin_EMAC_initialize(bis);
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index 2f90dbf928..fd8db61486 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -289,6 +289,7 @@ cm-bf561                     blackfin    blackfin
 dnp5370                      blackfin    blackfin
 ibf-dsp561                   blackfin    blackfin
 ip04                         blackfin    blackfin
+pr1                          blackfin    blackfin
 tcm-bf518                    blackfin    blackfin
 tcm-bf537                    blackfin    blackfin
 M52277EVB                    m68k        mcf5227x    m52277evb           freescale      -           M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000
diff --git a/include/configs/pr1.h b/include/configs/pr1.h
new file mode 100644
index 0000000000..03d4269584
--- /dev/null
+++ b/include/configs/pr1.h
@@ -0,0 +1,157 @@
+/*
+ * U-boot - Configuration file for PR1 Appliance
+ *
+ * based on bf537-stamp.h
+ * Copyright (c) Switchfin Org. <dpn@switchfin.org>
+ */
+
+#ifndef __CONFIG_PR1_H__
+#define __CONFIG_PR1_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf537-0.3
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			24
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	11
+#define CONFIG_MEM_SIZE		128
+
+#define CONFIG_EBIU_SDRRC_VAL	0x306
+#define CONFIG_EBIU_SDGCTL_VAL	0x8091998d
+
+#define CONFIG_EBIU_AMGCTL_VAL	0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(384 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_BFIN_MAC
+#define CONFIG_NETCONSOLE
+#endif
+#define CONFIG_HOSTNAME		pr1
+#define CONFIG_TFTP_BLOCKSIZE	4404
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_NO_FLASH	/* We have no parallel FLASH */
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C
+#define CONFIG_HARD_I2C
+
+
+/*
+ * NAND Settings
+ */
+#define CONFIG_NAND_PLAT
+#define CONFIG_SYS_NAND_BASE		0x20000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
+#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
+#define BFIN_NAND_WRITE(addr, cmd) \
+	do { \
+		bfin_write8(addr, cmd); \
+		SSYNC(); \
+	} while (0)
+
+#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
+#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF9
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_SYS_PROMPT	"pr1>"
+#define CONFIG_BOOTCOMMAND	"run nandboot"
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_LOADADDR		0x2000000
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+/*
+ * Overwrite some settings defined in bfin_adi_common.h
+ */
+#undef NAND_ENV_SETTINGS
+#define NAND_ENV_SETTINGS \
+	"nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
+	"nandboot=" \
+		"nand read $(loadaddr) 0x0 0x900000;" \
+		"run nandargs;" \
+		"bootm" \
+		"\0"
+
+#endif