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authorPhil Sutter <phil@nwl.cc>2015-12-25 14:41:20 +0100
committerStefan Roese <sr@denx.de>2016-01-14 14:08:59 +0100
commit9a04527840dbb2c7b8bc5bd5145fa9bd26c597b4 (patch)
tree5ccc51a1f1823cd98d6ea6fb45256ede22d42f0c
parent7e1e59a7b7da45361761ab1439c2751f4cae4163 (diff)
drivers/pci/pci_mvebu: Fix for boards with X4 lanes
Armada XP has support for X4 lanes, boards specify this in their serdes_cfg. During PEX init in high_speed_env_lib.c, the configuration is stored in GEN_PURP_RES_2_REG. When enumerating PEX, subsequent interfaces of an X4 lane must be skipped. Otherwise the enumeration hangs up the board. The way this is implemented here is not exactly beautiful, but it mimics how Marvell's BSP does it. Alternatively we could get the information using board_serdes_cfg_get(), but that won't lead to clean code, either. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
-rw-r--r--arch/arm/mach-mvebu/include/mach/soc.h2
-rw-r--r--drivers/pci/pci_mvebu.c14
2 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index c696fc6cec..9f6a2a407e 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -96,6 +96,8 @@
#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
+#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8))
+
/* BootROM error register (also includes some status infos) */
#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
#define BOOTROM_ERR_MODE_OFFS 28
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index fd2744dbd4..4eedfe1cbb 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -155,6 +155,14 @@ static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx,
}
#endif
+static int mvebu_pex_unit_is_x4(int pex_idx)
+{
+ int pex_unit = pex_idx < 9 ? pex_idx >> 2 : 3;
+ u32 mask = (0x0f << (pex_unit * 8));
+
+ return (readl(COMPHY_REFCLK_ALIGNMENT) & mask) == mask;
+}
+
static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
{
u32 val;
@@ -419,5 +427,11 @@ void pci_init_board(void)
writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
bus = hose->last_busno + 1;
+
+ /* need to skip more for X4 links, otherwise scan will hang */
+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+ if (mvebu_pex_unit_is_x4(i))
+ i += 3;
+ }
}
}