diff options
| author | Stefano Babic <sbabic@denx.de> | 2015-03-05 16:05:10 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-03-05 16:05:10 +0100 |
| commit | 9b5b60a05cb8bba2d135439419b2030764e359bd (patch) | |
| tree | 15e249ac39e9c547668327218e63a0faf54a3283 | |
| parent | 32df39c741788e8637cffe6633d73594b26d70fb (diff) | |
| parent | 7ae8350f67eea861280a4cbd2d067777a0e87153 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot
244 files changed, 6461 insertions, 881 deletions
@@ -96,6 +96,24 @@ config SPL help If you want to build SPL as well as the normal image, say Y. +config SPL_STACK_R + depends on SPL + bool "Enable SDRAM location for SPL stack" + help + SPL starts off execution in SRAM and thus typically has only a small + stack available. Since SPL sets up DRAM while in its board_init_f() + function, it is possible for the stack to move there before + board_init_r() is reached. This option enables a special SDRAM + location for the SPL stack. U-Boot SPL switches to this after + board_init_f() completes, and before board_init_r() starts. + +config SPL_STACK_R_ADDR + depends on SPL_STACK_R + hex "SDRAM location for SPL stack" + help + Specify the address in SDRAM for the SPL stack. This will be set up + before board_init_r() is called. + config TPL bool depends on SPL && SUPPORT_TPL diff --git a/MAINTAINERS b/MAINTAINERS index eef70d0f68..68f35041f3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -148,7 +148,7 @@ F: arch/arm/mach-tegra/ F: arch/arm/include/asm/arch-tegra*/ ARM TI -M: Tom Rini <trini@ti.com> +M: Tom Rini <trini@konsulko.com> S: Maintained T: git git://git.denx.de/u-boot-ti.git F: arch/arm/cpu/arm926ejs/davinci/ @@ -162,8 +162,7 @@ ARM UNIPHIER M: Masahiro Yamada <yamada.m@jp.panasonic.com> S: Maintained T: git git://git.denx.de/u-boot-uniphier.git -F: arch/arm/cpu/armv7/uniphier/ -F: arch/arm/include/asm/arch-uniphier/ +F: arch/arm/mach-uniphier/ F: configs/ph1_*_defconfig N: uniphier @@ -173,6 +172,12 @@ S: Maintained F: arch/arm/cpu/armv7/zynq/ F: arch/arm/include/asm/arch-zynq/ +ARM ZYNQMP +M: Michal Simek <michal.simek@xilinx.com> +S: Maintained +F: arch/arm/cpu/armv8/zynqmp/ +F: arch/arm/include/asm/arch-zynqmp/ + AVR32 M: Andreas Bießmann <andreas.devel@googlemail.com> S: Maintained @@ -209,6 +214,7 @@ M: Lukasz Majewski <l.majewski@samsung.com> S: Maintained T: git git://git.denx.de/u-boot-dfu.git F: drivers/dfu/ +F: drivers/usb/gadget/ DRIVER MODEL M: Simon Glass <sjg@chromium.org> @@ -411,7 +417,7 @@ T: git git://git.denx.de/u-boot-x86.git F: arch/x86/ THE REST -M: Tom Rini <trini@ti.com> +M: Tom Rini <trini@konsulko.com> L: u-boot@lists.denx.de Q: http://patchwork.ozlabs.org/project/uboot/list/ S: Maintained @@ -1,7 +1,7 @@ VERSION = 2015 PATCHLEVEL = 04 SUBLEVEL = -EXTRAVERSION = -rc2 +EXTRAVERSION = -rc3 NAME = # *DOCUMENTATION* @@ -273,6 +273,75 @@ run some of U-Boot's tests. See board/sandbox/README.sandbox for more details. +Board Initialisation Flow: +-------------------------- + +This is the intended start-up flow for boards. This should apply for both +SPL and U-Boot proper (i.e. they both follow the same rules). At present SPL +mostly uses a separate code path, but the funtion names and roles of each +function are the same. Some boards or architectures may not conform to this. +At least most ARM boards which use CONFIG_SPL_FRAMEWORK conform to this. + +Execution starts with start.S with three functions called during init after +that. The purpose and limitations of each is described below. + +lowlevel_init(): + - purpose: essential init to permit execution to reach board_init_f() + - no global_data or BSS + - there is no stack (ARMv7 may have one but it will soon be removed) + - must not set up SDRAM or use console + - must only do the bare minimum to allow execution to continue to + board_init_f() + - this is almost never needed + - return normally from this function + +board_init_f(): + - purpose: set up the machine ready for running board_init_r(): + i.e. SDRAM and serial UART + - global_data is available + - stack is in SRAM + - BSS is not available, so you cannot use global/static variables, + only stack variables and global_data + + Non-SPL-specific notes: + - dram_init() is called to set up DRAM. If already done in SPL this + can do nothing + + SPL-specific notes: + - you can override the entire board_init_f() function with your own + version as needed. + - preloader_console_init() can be called here in extremis + - should set up SDRAM, and anything needed to make the UART work + - these is no need to clear BSS, it will be done by crt0.S + - must return normally from this function (don't call board_init_r() + directly) + +Here the BSS is cleared. For SPL, if CONFIG_SPL_STACK_R is defined, then at +this point the stack and global_data are relocated to below +CONFIG_SPL_STACK_R_ADDR. For non-SPL, U-Boot is relocated to run at the top of +memory. + +board_init_r(): + - purpose: main execution, common code + - global_data is available + - SDRAM is available + - BSS is available, all static/global variables can be used + - execution eventually continues to main_loop() + + Non-SPL-specific notes: + - U-Boot is relocated to the top of memory and is now running from + there. + + SPL-specific notes: + - stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and + CONFIG_SPL_STACK_R_ADDR points into SDRAM + - preloader_console_init() can be called here - typically this is + done by defining CONFIG_SPL_BOARD_INIT and then supplying a + spl_board_init() function containing this call + - loads U-Boot or (in falcon mode) Linux + + + Configuration Options: ---------------------- diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index eb92297cb3..8472d41565 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -596,6 +596,10 @@ config ZYNQ select CPU_V7 select SUPPORT_SPL +config TARGET_XILINX_ZYNQMP + bool "Support Xilinx ZynqMP Platform" + select ARM64 + config TEGRA bool "NVIDIA Tegra" select SUPPORT_SPL @@ -727,7 +731,7 @@ source "arch/arm/cpu/armv7/s5pc1xx/Kconfig" source "arch/arm/mach-tegra/Kconfig" -source "arch/arm/cpu/armv7/uniphier/Kconfig" +source "arch/arm/mach-uniphier/Kconfig" source "arch/arm/mach-versatile/Kconfig" @@ -845,6 +849,7 @@ source "board/wandboard/Kconfig" source "board/warp/Kconfig" source "board/woodburn/Kconfig" source "board/xaeniax/Kconfig" +source "board/xilinx/zynqmp/Kconfig" source "board/zipitz2/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 878ae26ce4..08946de244 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -15,6 +15,7 @@ machine-$(CONFIG_ARCH_NOMADIK) += nomadik # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X machine-$(CONFIG_ORION5X) += orion5x machine-$(CONFIG_TEGRA) += tegra +machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_VERSATILE) += versatile machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index b228ed6a2e..ad22489e1a 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -56,6 +56,5 @@ obj-$(CONFIG_SOCFPGA) += socfpga/ obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_U8500) += u8500/ -obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/ obj-$(CONFIG_VF610) += vf610/ obj-$(CONFIG_ZYNQ) += zynq/ diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 81477aa7b0..67bef23ea9 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -275,6 +275,14 @@ static void watchdog_disable(void) ; } +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + board_early_init_f(); + sdram_init(); +} +#endif + void s_init(void) { /* @@ -290,6 +298,7 @@ void s_init(void) setup_clocks_for_console(); uart_soft_reset(); #if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT) + /* TODO: This does not work, gd is not available yet */ gd->baudrate = CONFIG_BAUDRATE; serial_init(); gd->have_console = 1; @@ -298,9 +307,5 @@ void s_init(void) /* Enable RTC32K clock */ rtc32k_enable(); #endif -#ifdef CONFIG_SPL_BUILD - board_early_init_f(); - sdram_init(); -#endif } #endif diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile index e207bd6af0..8542f896cf 100644 --- a/arch/arm/cpu/armv7/exynos/Makefile +++ b/arch/arm/cpu/armv7/exynos/Makefile @@ -7,6 +7,8 @@ obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o +obj-$(CONFIG_EXYNOS5420) += sec_boot.o + ifdef CONFIG_SPL_BUILD obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o diff --git a/arch/arm/cpu/armv7/exynos/common_setup.h b/arch/arm/cpu/armv7/exynos/common_setup.h index e6318c0366..5235abb808 100644 --- a/arch/arm/cpu/armv7/exynos/common_setup.h +++ b/arch/arm/cpu/armv7/exynos/common_setup.h @@ -23,6 +23,8 @@ * MA 02111-1307 USA */ +#include <asm/arch/system.h> + #define DMC_OFFSET 0x10000 /* @@ -43,3 +45,63 @@ void system_clock_init(void); int do_lowlevel_init(void); void sdelay(unsigned long); + +enum l2_cache_params { + CACHE_DATA_RAM_LATENCY_2_CYCLES = (2 << 0), + CACHE_DATA_RAM_LATENCY_3_CYCLES = (3 << 0), + CACHE_DISABLE_CLEAN_EVICT = (1 << 3), + CACHE_DATA_RAM_SETUP = (1 << 5), + CACHE_TAG_RAM_LATENCY_2_CYCLES = (2 << 6), + CACHE_TAG_RAM_LATENCY_3_CYCLES = (3 << 6), + CACHE_ENABLE_HAZARD_DETECT = (1 << 7), + CACHE_TAG_RAM_SETUP = (1 << 9), + CACHE_ECC_AND_PARITY = (1 << 21), + CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27) +}; + + +#ifndef CONFIG_SYS_L2CACHE_OFF +/* + * Configure L2CTLR to get timings that keep us from hanging/crashing. + * + * Must be inline here since low_power_start() is called without a + * stack (!). + */ +static inline void configure_l2_ctlr(void) +{ + uint32_t val; + + mrc_l2_ctlr(val); + + val |= CACHE_TAG_RAM_SETUP | + CACHE_DATA_RAM_SETUP | + CACHE_TAG_RAM_LATENCY_2_CYCLES | + CACHE_DATA_RAM_LATENCY_2_CYCLES; + + if (proid_is_exynos5420() || proid_is_exynos5800()) { + val |= CACHE_ECC_AND_PARITY | + CACHE_TAG_RAM_LATENCY_3_CYCLES | + CACHE_DATA_RAM_LATENCY_3_CYCLES; + } + + mcr_l2_ctlr(val); +} + +/* + * Configure L2ACTLR. + * + * Must be inline here since low_power_start() is called without a + * stack (!). + */ +static inline void configure_l2_actlr(void) +{ + uint32_t val; + + if (proid_is_exynos5420() || proid_is_exynos5800()) { + mrc_l2_aux_ctlr(val); + val |= CACHE_ENABLE_FORCE_L2_LOGIC | + CACHE_DISABLE_CLEAN_EVICT; + mcr_l2_aux_ctlr(val); + } +} +#endif diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index 2eea48a0cc..9073f50f6b 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -700,6 +700,9 @@ #define CLK_DIV_CPERI1_VAL NOT_AVAILABLE #else + +#define CPU_CONFIG_STATUS_OFFSET 0x80 +#define CPU_RST_FLAG_VAL 0xFCBA0D10 #define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000 /* APLL_CON1 */ diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c index 83e1dcfc1e..120aaf8b96 100644 --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c @@ -31,7 +31,10 @@ #include <asm/arch/tzpc.h> #include <asm/arch/periph.h> #include <asm/arch/pinmux.h> +#include <asm/arch/system.h> +#include <asm/armv7.h> #include "common_setup.h" +#include "exynos5_setup.h" /* These are the things we can do during low-level init */ enum { @@ -42,6 +45,128 @@ enum { DO_POWER = 1 << 4, }; +#ifdef CONFIG_EXYNOS5420 +/* + * Power up secondary CPUs. + */ +static void secondary_cpu_start(void) +{ + v7_enable_smp(EXYNOS5420_INFORM_BASE); + svc32_mode_en(); + branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE); +} + +/* + * This is the entry point of hotplug-in and + * cluster switching. + */ +static void low_power_start(void) +{ + uint32_t val, reg_val; + + reg_val = readl(EXYNOS5420_SPARE_BASE); + if (reg_val != CPU_RST_FLAG_VAL) { + writel(0x0, CONFIG_LOWPOWER_FLAG); + branch_bx(0x0); + } + + reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4); + if (reg_val != (uint32_t)&low_power_start) { + /* Store jump address as low_power_start if not present */ + writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4); + dsb(); + sev(); + } + + /* Set the CPU to SVC32 mode */ + svc32_mode_en(); + +#ifndef CONFIG_SYS_L2CACHE_OFF + /* Read MIDR for Primary Part Number */ + mrc_midr(val); + val = (val >> 4); + val &= 0xf; + + if (val == 0xf) { + configure_l2_ctlr(); + configure_l2_actlr(); + v7_enable_l2_hazard_detect(); + } +#endif + + /* Invalidate L1 & TLB */ + val = 0x0; + mcr_tlb(val); + mcr_icache(val); + + /* Disable MMU stuff and caches */ + mrc_sctlr(val); + + val &= ~((0x2 << 12) | 0x7); + val |= ((0x1 << 12) | (0x8 << 8) | 0x2); + mcr_sctlr(val); + + /* CPU state is hotplug or reset */ + secondary_cpu_start(); + + /* Core should not enter into WFI here */ + wfi(); +} + +/* + * Pointer to this function is stored in iRam which is used + * for jump and power down of a specific core. + */ +static void power_down_core(void) +{ + uint32_t tmp, core_id, core_config; + + /* Get the unique core id */ + /* + * Multiprocessor Affinity Register + * [11:8] Cluster ID + * [1:0] CPU ID + */ + mrc_mpafr(core_id); + tmp = core_id & 0x3; + core_id = (core_id >> 6) & ~3; + core_id |= tmp; + core_id &= 0x3f; + + /* Set the status of the core to low */ + core_config = (core_id * CPU_CONFIG_STATUS_OFFSET); + core_config += EXYNOS5420_CPU_CONFIG_BASE; + writel(0x0, core_config); + + /* Core enter WFI */ + wfi(); +} + +/* + * Configurations for secondary cores are inapt at this stage. + * Reconfigure secondary cores. Shutdown and change the status + * of all cores except the primary core. + */ +static void secondary_cores_configure(void) +{ + /* Clear secondary boot iRAM base */ + writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C)); + + /* set lowpower flag and address */ + writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG); + writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR); + writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE); + /* Store jump address for power down */ + writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4); + + /* Need all core power down check */ + dsb(); + sev(); +} + +extern void relocate_wait_code(void); +#endif + int do_lowlevel_init(void) { uint32_t reset_status; @@ -49,6 +174,28 @@ int do_lowlevel_init(void) arch_cpu_init(); +#ifndef CONFIG_SYS_L2CACHE_OFF + /* + * Init L2 cache parameters here for use by boot and resume + * + * These are here instead of in v7_outer_cache_enable() so that the + * L2 cache settings get properly set even at resume time or if we're + * running U-Boot with the cache off. The kernel still needs us to + * set these for it. + */ + configure_l2_ctlr(); + configure_l2_actlr(); + dsb(); + isb(); +#endif + +#ifdef CONFIG_EXYNOS5420 + relocate_wait_code(); + + /* Reconfigure secondary cores */ + secondary_cores_configure(); +#endif + reset_status = get_reset_status(); switch (reset_status) { diff --git a/arch/arm/cpu/armv7/exynos/sec_boot.S b/arch/arm/cpu/armv7/exynos/sec_boot.S new file mode 100644 index 0000000000..dfc3455929 --- /dev/null +++ b/arch/arm/cpu/armv7/exynos/sec_boot.S @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Akshay Saraswat <akshay.s@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/arch/cpu.h> + + .globl relocate_wait_code +relocate_wait_code: + adr r0, code_base @ r0: source address (start) + adr r1, code_end @ r1: source address (end) + ldr r2, =0x02073000 @ r2: target address +1: + ldmia r0!, {r3-r6} + stmia r2!, {r3-r6} + cmp r0, r1 + blt 1b + b code_end + .ltorg +/* + * Secondary core waits here until Primary wake it up. + * Below code is copied to CONFIG_EXYNOS_RELOCATE_CODE_BASE. + * This is a workaround code which is supposed to act as a + * substitute/supplement to the iROM code. + * + * This workaround code is relocated to the address 0x02073000 + * because that comes out to be the last 4KB of the iRAM + * (Base Address - 0x02020000, Limit Address - 0x020740000). + * + * U-boot and kernel are aware of this code and flags by the simple + * fact that we are implementing a workaround in the last 4KB + * of the iRAM and we have already defined these flag and address + * values in both kernel and U-boot for our use. + */ +code_base: + b 1f +/* + * These addresses are being used as flags in u-boot and kernel. + * + * Jump address for resume and flag to check for resume/reset: + * Resume address - 0x2073008 + * Resume flag - 0x207300C + * + * Jump address for cluster switching: + * Switch address - 0x2073018 + * + * Jump address for core hotplug: + * Hotplug address - 0x207301C + * + * Jump address for C2 state (Reserved for future not being used right now): + * C2 address - 0x2073024 + * + * Managed per core status for the active cluster: + * CPU0 state - 0x2073028 + * CPU1 state - 0x207302C + * CPU2 state - 0x2073030 + * CPU3 state - 0x2073034 + * + * Managed per core GIC status for the active cluster: + * CPU0 gic state - 0x2073038 + * CPU1 gic state - 0x207303C + * CPU2 gic state - 0x2073040 + * CPU3 gic state - 0x2073044 + * + * Logic of the code: + * Step-1: Read current CPU status. + * Step-2: If it's a resume then continue, else jump to step 4. + * Step-3: Clear inform1 PMU register and jump to inform0 value. + * Step-4: If it's a switch, C2 or reset, get the hotplug address. + * Step-5: If address is not available, enter WFE. + * Step-6: If address is available, jump to that address. + */ + nop @ for backward compatibility + .word 0x0 @ REG0: RESUME_ADDR + .word 0x0 @ REG1: RESUME_FLAG + .word 0x0 @ REG2 + .word 0x0 @ REG3 +_switch_addr: + .word 0x0 @ REG4: SWITCH_ADDR +_hotplug_addr: + .word 0x0 @ REG5: CPU1_BOOT_REG + .word 0x0 @ REG6 +_c2_addr: + .word 0x0 @ REG7: REG_C2_ADDR +_cpu_state: + .word 0x1 @ CPU0_STATE : RESET + .word 0x2 @ CPU1_STATE : SECONDARY RESET + .word 0x2 @ CPU2_STATE : SECONDARY RESET + .word 0x2 @ CPU3_STATE : SECONDARY RESET +_gic_state: + .word 0x0 @ CPU0 - GICD_IGROUPR0 + .word 0x0 @ CPU1 - GICD_IGROUPR0 + .word 0x0 @ CPU2 - GICD_IGROUPR0 + .word 0x0 @ CPU3 - GICD_IGROUPR0 +1: + adr r0, _cpu_state + mrc p15, 0, r7, c0, c0, 5 @ read MPIDR + and r7, r7, #0xf @ r7 = cpu id +/* Read the current cpu state */ + ldr r10, [r0, r7, lsl #2] +svc_entry: + tst r10, #(1 << 4) + adrne r0, _switch_addr + bne wait_for_addr +/* Clear INFORM1 */ + ldr r0, =(0x10040000 + 0x804) + ldr r1, [r0] + cmp r1, #0x0 + movne r1, #0x0 + strne r1, [r0] +/* Get INFORM0 */ + ldrne r1, =(0x10040000 + 0x800) + ldrne pc, [r1] + tst r10, #(1 << 0) + ldrne pc, =0x23e00000 + adr r0, _hotplug_addr +wait_for_addr: + ldr r1, [r0] + cmp r1, #0x0 + bxne r1 + wfe + b wait_for_addr + .ltorg +code_end: + mov pc, lr diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c index 8c7d7d893f..0f116b141a 100644 --- a/arch/arm/cpu/armv7/exynos/soc.c +++ b/arch/arm/cpu/armv7/exynos/soc.c @@ -9,13 +9,6 @@ #include <asm/io.h> #include <asm/system.h> -enum l2_cache_params { - CACHE_TAG_RAM_SETUP = (1 << 9), - CACHE_DATA_RAM_SETUP = (1 << 5), - CACHE_TAG_RAM_LATENCY = (2 << 6), - CACHE_DATA_RAM_LATENCY = (2 << 0) -}; - void reset_cpu(ulong addr) { writel(0x1, samsung_get_base_swreset()); @@ -28,31 +21,3 @@ void enable_caches(void) dcache_enable(); } #endif - -#ifndef CONFIG_SYS_L2CACHE_OFF -/* - * Set L2 cache parameters - */ -static void exynos5_set_l2cache_params(void) -{ - unsigned int val = 0; - - asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val)); - - val |= CACHE_TAG_RAM_SETUP | - CACHE_DATA_RAM_SETUP | - CACHE_TAG_RAM_LATENCY | - CACHE_DATA_RAM_LATENCY; - - asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val)); -} - -/* - * Sets L2 cache related parameters before enabling data cache - */ -void v7_outer_cache_enable(void) -{ - if (cpu_is_exynos5()) - exynos5_set_l2cache_params(); -} -#endif diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index f1aea05c90..427b0b1321 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -17,10 +17,17 @@ ENTRY(lowlevel_init) /* - * Setup a temporary stack + * Setup a temporary stack. Global data is not available yet. */ ldr sp, =CONFIG_SYS_INIT_SP_ADDR bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ +#ifdef CONFIG_DM + mov r9, #0 +#else + /* + * Set up global data for boards that still need it. This will be + * removed soon. + */ #ifdef CONFIG_SPL_BUILD ldr r9, =gdata #else @@ -28,13 +35,24 @@ ENTRY(lowlevel_init) bic sp, sp, #7 mov r9, sp #endif +#endif /* * Save the old lr(passed in ip) and the current lr to stack */ push {ip, lr} /* - * go setup pll, mux, memory + * Call the very early init function. This should do only the + * absolute bare minimum to get started. It should not: + * + * - set up DRAM + * - use global_data + * - clear BSS + * - try to start a console + * + * For boards with SPL this should be empty since SPL can do all of + * this init in the SPL board_init_f() function which is called + * immediately after this. */ bl s_init pop {ip, pc} diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index cb35c198f1..6c8f3bcea4 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -128,14 +128,18 @@ void s_init(void) do_io_settings(); #endif prcm_init(); +} + #ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ #ifdef CONFIG_BOARD_EARLY_INIT_F board_early_init_f(); #endif /* For regular u-boot sdram_init() is called from dram_init() */ sdram_init(); -#endif } +#endif /* * Routine: wait_for_command_complete diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 90d6ae7bb5..347947c4b3 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -240,8 +240,6 @@ void try_unlock_memory(void) *****************************************************************************/ void s_init(void) { - int in_sdram = is_running_in_sdram(); - watchdog_init(); try_unlock_memory(); @@ -264,10 +262,14 @@ void s_init(void) #ifdef CONFIG_USB_EHCI_OMAP ehci_clocks_enable(); #endif +} - if (!in_sdram) - mem_init(); +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + mem_init(); } +#endif /* * Routine: misc_init_r diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig index 35866508a3..2b333a3d46 100644 --- a/arch/arm/cpu/armv7/rmobile/Kconfig +++ b/arch/arm/cpu/armv7/rmobile/Kconfig @@ -24,6 +24,9 @@ config TARGET_ALT config TARGET_SILK bool "Silk board" +config TARGET_PORTER + bool "Porter board" + endchoice config SYS_SOC @@ -31,7 +34,7 @@ config SYS_SOC config RMOBILE_EXTRAM_BOOT bool "Enable boot from RAM" - depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_SILK + depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK default n source "board/atmark-techno/armadillo-800eva/Kconfig" @@ -41,5 +44,6 @@ source "board/renesas/lager/Kconfig" source "board/kmc/kzm9g/Kconfig" source "board/renesas/alt/Kconfig" source "board/renesas/silk/Kconfig" +source "board/renesas/porter/Kconfig" endif diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c index 1259062a64..580aba39e1 100644 --- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c @@ -135,7 +135,91 @@ enum { FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, FN_MII_RXD2, - /* IPSR8 - IPSR16 */ + /* IPSR8 */ + FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, + FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, + FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, + FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, + FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, + FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, + FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, + FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV, + FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, + FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1, + FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC, + FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, + FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, + FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, + FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5, + FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, + FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD, + FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, + + /* IPSR9 */ + FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, + FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, + FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, + FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, + FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, + FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B, + FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, + FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, + FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B, + FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, + FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD, + FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, + FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, + FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK, + FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2, + FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B, + FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, + FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, + FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, + FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B, + FN_VI3_CLK_B, + + /* IPSR10 */ + FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, + FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D, + FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, + FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, + FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, + FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, + FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, + FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, + FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, + FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, + FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA, + FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, + FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, + FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK, + FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, + FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3, + FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, + FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, + FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4, + FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, + FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, + FN_GLO_I0_B, FN_VI3_DATA6_B, + + /* IPSR11 */ + FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, + FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, + FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, + FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD, + FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, + FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2, + FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3, + FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, + FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP, + FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, + FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, + FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, + FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, + FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN, + FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, + FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B, + FN_MOUT0, FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, FN_SEL_SCIF1_4, @@ -189,11 +273,110 @@ enum { FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, FN_SEL_I2C2_4, FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, - PINMUX_FUNCTION_END, PINMUX_MARK_BEGIN, + VI1_DATA7_VI1_B7_MARK, + + USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, + USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK, + DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK, + + D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK, + D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK, + VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK, + VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK, + VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK, + SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK, + VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK, + SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK, + VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK, + SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, + SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK, + VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK, + D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK, + VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, + + D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK, + VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK, + SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK, + VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK, + SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK, + VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK, + D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK, + VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK, + D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK, + VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK, + SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK, + VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK, + D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK, + VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK, + A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK, + + A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK, + PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK, + TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK, + A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK, + SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK, + A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK, + VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK, + A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK, + VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK, + A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK, + VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK, + + A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK, + VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK, + A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK, + VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK, + A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK, + MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK, + VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK, + ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK, + ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK, + A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK, + AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK, + ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK, + VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK, + + A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK, + A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK, + VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK, + VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK, + VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK, + VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK, + VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK, + VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK, + CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK, + VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK, + VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK, + MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK, + HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK, + VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK, + VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK, + + EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK, + VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK, + EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK, + VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK, + INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, + MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK, + VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK, + SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, + CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, + CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, + VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, + INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, + VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK, + WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK, + VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK, + IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK, + VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK, + MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK, + VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK, + SSI_WS78_B_MARK, + DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, @@ -235,12 +418,189 @@ enum { VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, MII_RXD2_MARK, + VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK, + MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, + AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK, + AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK, + AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK, + AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK, + MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, + MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK, + MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, + AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK, + SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK, + VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK, + MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, + AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK, + AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, + AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK, + SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK, + SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK, + + SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK, + SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK, + SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK, + SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK, + SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK, + GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK, + SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, + MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, + GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK, + SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, + AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK, + AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK, + SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK, + SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK, + MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, + AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK, + SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK, + SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, + TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, + SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK, + VI3_CLK_B_MARK, + + SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK, + GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK, + SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK, + VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK, + VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK, + VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK, + TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK, + SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK, + VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK, + TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK, + SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK, + VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK, + TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK, + SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK, + VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK, + GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK, + MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK, + HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK, + VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK, + TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK, + VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK, + GLO_I0_B_MARK, VI3_DATA6_B_MARK, + + SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK, + GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK, + TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK, + SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK, + MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK, + SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK, + MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK, + SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK, + VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK, + MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK, + RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK, + RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK, + MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK, + SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK, + SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, + RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK, + MOUT0_MARK, + + SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK, + SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK, + SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK, + SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK, + SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK, + MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK, + STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK, + CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK, + SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK, + SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK, + MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK, + SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK, + MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK, + SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK, + CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK, + IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK, + CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK, + IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK, + CAN_DEBUGOUT4_MARK, + + SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK, + LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK, + SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK, + DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK, + BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK, + SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK, + LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK, + FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK, + CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK, + SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK, + CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK, + SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK, + LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK, + STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK, + TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK, + BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK, + FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK, + STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK, + CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK, + STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK, + SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK, + SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK, + + AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK, + DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK, + REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK, + MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK, + SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, + DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK, + TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, + HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, + LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK, + SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK, + MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, + SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, + DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, + SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK, + LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK, + CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK, + SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK, + MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, + HRTS0_N_C_MARK, + + SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, + LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, + DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK, + SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK, + SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK, + DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, + DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, + LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK, + LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK, + LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK, + DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK, + SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK, + SCIFA2_RXD_B_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK, + DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK, + DU2_DG6_MARK, LCDOUT14_MARK, + + MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK, + DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK, + MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK, + ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, HRX0_C_MARK, + USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, + TCLK1_B_MARK, PINMUX_MARK_END, }; static pinmux_enum_t pinmux_data[] = { PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7), + PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), + PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS), + PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN), + PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC), + PINMUX_DATA(AVS1_MARK, FN_AVS1), + PINMUX_DATA(AVS2_MARK, FN_AVS2), + PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0), + PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2), + PINMUX_IPSR_DATA(IP6_2_0, DACK0), PINMUX_IPSR_DATA(IP6_2_0, IRQ0), PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N), @@ -364,12 +724,267 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2), + PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N), + PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3), + PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3), + PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N), + PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4), + PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N), + PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5), + PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N), + PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6), + PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1), + PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7), + PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER), + PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), + PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK), + PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0), + PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV), + PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV), + PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS), + PINMUX_IPSR_DATA(IP8_17_16, MII_CRS), + PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC), + PINMUX_IPSR_DATA(IP8_19_18, MII_MDC), + PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO), + PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), + PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC), + PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3), + PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), + PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK), + PINMUX_IPSR_DATA(IP8_28, SD0_CLK), + PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD), + PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1), + + PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0), + PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1), + PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2), + PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3), + PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1), + PINMUX_IPSR_DATA(IP9_11_8, SD0_CD), + PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1), + PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP9_15_12, SD0_WP), + PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1), + PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1), + PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), + PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK), + PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN), + PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN), + PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD), + PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER), + PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER), + PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0), + PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK), + PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1), + PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK), + PINMUX_IPSR_DATA(IP9_23_22, MII_LINK), + PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2), + PINMUX_IPSR_DATA(IP9_25_24, AVB_COL), + PINMUX_IPSR_DATA(IP9_25_24, MII_COL), + PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3), + PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0), + PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_DATA(IP9_31_28, SD1_CD), + PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0), + PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), + PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1), + + PINMUX_IPSR_DATA(IP10_3_0, SD1_WP), + PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0), + PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3), + PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1), + PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK), + PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD), + PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0), + PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1), + PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2), + PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3), + PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP10_29_26, SD2_CD), + PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1), + PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1), + + PINMUX_IPSR_DATA(IP11_3_0, SD2_WP), + PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1), + PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1), + PINMUX_IPSR_DATA(IP11_4, SD3_CLK), + PINMUX_IPSR_DATA(IP11_4, MMC1_CLK), + PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD), + PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD), + PINMUX_IPSR_DATA(IP11_6_5, MTS_N), + PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0), + PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0), + PINMUX_IPSR_DATA(IP11_8_7, STM_N), + PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1), + PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1), + PINMUX_IPSR_DATA(IP11_10_9, MDATA), + PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2), + PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2), + PINMUX_IPSR_DATA(IP11_12_11, SDATA), + PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3), + PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3), + PINMUX_IPSR_DATA(IP11_14_13, SCKZ), + PINMUX_IPSR_DATA(IP11_17_15, SD3_CD), + PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4), + PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0), + PINMUX_IPSR_DATA(IP11_17_15, VSP), + PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1), + PINMUX_IPSR_DATA(IP11_21_18, SD3_WP), + PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5), + PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4), + PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK), + PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1), + PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1), + PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT), + PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1), + PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129), + PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), + PINMUX_IPSR_DATA(IP11_31_30, MOUT0), + }; static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO_GP_ALL(), - /*IPSR0 - IPSR5*/ + GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC_VBUS), + GPIO_FN(USB2_PWEN), GPIO_FN(USB2_OVC), GPIO_FN(AVS1), GPIO_FN(AVS2), + GPIO_FN(DU_DOTCLKIN0), GPIO_FN(DU_DOTCLKIN2), + + /* IPSR0 - IPSR5 */ /*IPSR6*/ GPIO_FN(DACK0), GPIO_FN(IRQ0), GPIO_FN(INTC_IRQ0_N), GPIO_FN(SSI_SCK6_B), GPIO_FN(VI1_VSYNC_N), GPIO_FN(VI1_VSYNC_N_B), @@ -413,7 +1028,97 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(VI0_CLK), GPIO_FN(ATACS00_N), GPIO_FN(AVB_RXD1), GPIO_FN(MII_RXD1), GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(ATACS10_N), GPIO_FN(AVB_RXD2), GPIO_FN(MII_RXD2), - /*IPSR8 - IPSR16*/ + + /*IPSR8*/ + GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(ATARD0_N), GPIO_FN(AVB_RXD3), + GPIO_FN(MII_RXD3), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(ATAWR0_N), + GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ATADIR0_N), + GPIO_FN(AVB_RXD5), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ATAG0_N), + GPIO_FN(AVB_RXD6), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(EX_WAIT1), + GPIO_FN(AVB_RXD7), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RX_ER), + GPIO_FN(MII_RX_ER), GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RX_CLK), + GPIO_FN(MII_RX_CLK), GPIO_FN(VI1_CLK), GPIO_FN(AVB_RX_DV), + GPIO_FN(MII_RX_DV), GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SCIFA1_SCK_D), + GPIO_FN(AVB_CRS), GPIO_FN(MII_CRS), GPIO_FN(VI1_DATA1_VI1_B1), + GPIO_FN(SCIFA1_RXD_D), GPIO_FN(AVB_MDC), GPIO_FN(MII_MDC), + GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SCIFA1_TXD_D), GPIO_FN(AVB_MDIO), + GPIO_FN(MII_MDIO), GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SCIFA1_CTS_N_D), + GPIO_FN(AVB_GTX_CLK), GPIO_FN(VI1_DATA4_VI1_B4), + GPIO_FN(SCIFA1_RTS_N_D), GPIO_FN(AVB_MAGIC), GPIO_FN(MII_MAGIC), + GPIO_FN(VI1_DATA5_VI1_B5), GPIO_FN(AVB_PHY_INT), + GPIO_FN(VI1_DATA6_VI1_B6), GPIO_FN(AVB_GTXREFCLK), + GPIO_FN(SD0_CLK), GPIO_FN(VI1_DATA0_VI1_B0_B), GPIO_FN(SD0_CMD), + GPIO_FN(SCIFB1_SCK_B), GPIO_FN(VI1_DATA1_VI1_B1_B), + + /*IPSR9*/ + GPIO_FN(SD0_DAT0), GPIO_FN(SCIFB1_RXD_B), GPIO_FN(VI1_DATA2_VI1_B2_B), + GPIO_FN(SD0_DAT1), GPIO_FN(SCIFB1_TXD_B), GPIO_FN(VI1_DATA3_VI1_B3_B), + GPIO_FN(SD0_DAT2), GPIO_FN(SCIFB1_CTS_N_B), GPIO_FN(VI1_DATA4_VI1_B4_B), + GPIO_FN(SD0_DAT3), GPIO_FN(SCIFB1_RTS_N_B), GPIO_FN(VI1_DATA5_VI1_B5_B), + GPIO_FN(SD0_CD), GPIO_FN(MMC0_D6), GPIO_FN(TS_SDEN0_B), + GPIO_FN(USB0_EXTP), GPIO_FN(GLO_SCLK), GPIO_FN(VI1_DATA6_VI1_B6_B), + GPIO_FN(SCL1_B), GPIO_FN(SCL1_CIS_B), GPIO_FN(VI2_DATA6_VI2_B6_B), + GPIO_FN(SD0_WP), GPIO_FN(MMC0_D7), GPIO_FN(TS_SPSYNC0_B), + GPIO_FN(USB0_IDIN), GPIO_FN(GLO_SDATA), GPIO_FN(VI1_DATA7_VI1_B7_B), + GPIO_FN(SDA1_B), GPIO_FN(SDA1_CIS_B), GPIO_FN(VI2_DATA7_VI2_B7_B), + GPIO_FN(SD1_CLK), GPIO_FN(AVB_TX_EN), GPIO_FN(MII_TX_EN), + GPIO_FN(SD1_CMD), GPIO_FN(AVB_TX_ER), GPIO_FN(MII_TX_ER), + GPIO_FN(SCIFB0_SCK_B), GPIO_FN(SD1_DAT0), GPIO_FN(AVB_TX_CLK), + GPIO_FN(MII_TX_CLK), GPIO_FN(SCIFB0_RXD_B), GPIO_FN(SD1_DAT1), + GPIO_FN(AVB_LINK), GPIO_FN(MII_LINK), GPIO_FN(SCIFB0_TXD_B), + GPIO_FN(SD1_DAT2), GPIO_FN(AVB_COL), GPIO_FN(MII_COL), + GPIO_FN(SCIFB0_CTS_N_B), GPIO_FN(SD1_DAT3), GPIO_FN(AVB_RXD0), + GPIO_FN(MII_RXD0), GPIO_FN(SCIFB0_RTS_N_B), GPIO_FN(SD1_CD), + GPIO_FN(MMC1_D6), GPIO_FN(TS_SDEN1), GPIO_FN(USB1_EXTP), + GPIO_FN(GLO_SS), GPIO_FN(VI0_CLK_B), GPIO_FN(SCL2_D), + GPIO_FN(SCL2_CIS_D), GPIO_FN(SIM0_CLK_B), GPIO_FN(VI3_CLK_B), + + /*IPSR10*/ + GPIO_FN(SD1_WP), GPIO_FN(MMC1_D7), GPIO_FN(TS_SPSYNC1), + GPIO_FN(USB1_IDIN), GPIO_FN(GLO_RFON), GPIO_FN(VI1_CLK_B), + GPIO_FN(SDA2_D), GPIO_FN(SDA2_CIS_D), GPIO_FN(SIM0_D_B), + GPIO_FN(SD2_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(SIM0_CLK), + GPIO_FN(VI0_DATA0_VI0_B0_B), GPIO_FN(TS_SDEN0_C), GPIO_FN(GLO_SCLK_B), + GPIO_FN(VI3_DATA0_B), GPIO_FN(SD2_CMD), GPIO_FN(MMC0_CMD), + GPIO_FN(SIM0_D), GPIO_FN(VI0_DATA1_VI0_B1_B), GPIO_FN(SCIFB1_SCK_E), + GPIO_FN(SCK1_D), GPIO_FN(TS_SPSYNC0_C), GPIO_FN(GLO_SDATA_B), + GPIO_FN(VI3_DATA1_B), GPIO_FN(SD2_DAT0), GPIO_FN(MMC0_D0), + GPIO_FN(FMCLK_B), GPIO_FN(VI0_DATA2_VI0_B2_B), GPIO_FN(SCIFB1_RXD_E), + GPIO_FN(RX1_D), GPIO_FN(TS_SDAT0_C), GPIO_FN(GLO_SS_B), + GPIO_FN(VI3_DATA2_B), GPIO_FN(SD2_DAT1), GPIO_FN(MMC0_D1), + GPIO_FN(FMIN_B), GPIO_FN(RDS_DATA), GPIO_FN(VI0_DATA3_VI0_B3_B), + GPIO_FN(SCIFB1_TXD_E), GPIO_FN(TX1_D), GPIO_FN(TS_SCK0_C), + GPIO_FN(GLO_RFON_B), GPIO_FN(VI3_DATA3_B), GPIO_FN(SD2_DAT2), + GPIO_FN(MMC0_D2), GPIO_FN(BPFCLK_B), GPIO_FN(RDS_CLK), + GPIO_FN(VI0_DATA4_VI0_B4_B), GPIO_FN(HRX0_D), GPIO_FN(TS_SDEN1_B), + GPIO_FN(GLO_Q0_B), GPIO_FN(VI3_DATA4_B), GPIO_FN(SD2_DAT3), + GPIO_FN(MMC0_D3), GPIO_FN(SIM0_RST), GPIO_FN(VI0_DATA5_VI0_B5_B), + GPIO_FN(HTX0_D), GPIO_FN(TS_SPSYNC1_B), GPIO_FN(GLO_Q1_B), + GPIO_FN(VI3_DATA5_B), GPIO_FN(SD2_CD), GPIO_FN(MMC0_D4), + GPIO_FN(TS_SDAT0_B), GPIO_FN(USB2_EXTP), GPIO_FN(GLO_I0), + GPIO_FN(VI0_DATA6_VI0_B6_B), GPIO_FN(HCTS0_N_D), GPIO_FN(TS_SDAT1_B), + GPIO_FN(GLO_I0_B), GPIO_FN(VI3_DATA6_B), + + /*IPSR11*/ + GPIO_FN(SD2_WP), GPIO_FN(MMC0_D5), GPIO_FN(TS_SCK0_B), + GPIO_FN(USB2_IDIN), GPIO_FN(GLO_I1), GPIO_FN(VI0_DATA7_VI0_B7_B), + GPIO_FN(HRTS0_N_D), GPIO_FN(TS_SCK1_B), GPIO_FN(GLO_I1_B), + GPIO_FN(VI3_DATA7_B), GPIO_FN(SD3_CLK), GPIO_FN(MMC1_CLK), + GPIO_FN(SD3_CMD), GPIO_FN(MMC1_CMD), GPIO_FN(MTS_N), GPIO_FN(SD3_DAT0), + GPIO_FN(MMC1_D0), GPIO_FN(STM_N), GPIO_FN(SD3_DAT1), GPIO_FN(MMC1_D1), + GPIO_FN(MDATA), GPIO_FN(SD3_DAT2), GPIO_FN(MMC1_D2), GPIO_FN(SDATA), + GPIO_FN(SD3_DAT3), GPIO_FN(MMC1_D3), GPIO_FN(SCKZ), GPIO_FN(SD3_CD), + GPIO_FN(MMC1_D4), GPIO_FN(TS_SDAT1), GPIO_FN(VSP), GPIO_FN(GLO_Q0), + GPIO_FN(SIM0_RST_B), GPIO_FN(SD3_WP), GPIO_FN(MMC1_D5), + GPIO_FN(TS_SCK1), GPIO_FN(GLO_Q1), GPIO_FN(FMIN_C), GPIO_FN(RDS_DATA_B), + GPIO_FN(FMIN_E), GPIO_FN(RDS_DATA_D), GPIO_FN(FMIN_F), + GPIO_FN(RDS_DATA_E), GPIO_FN(MLB_CLK), GPIO_FN(SCL2_B), + GPIO_FN(SCL2_CIS_B), GPIO_FN(MLB_SIG), GPIO_FN(SCIFB1_RXD_D), + GPIO_FN(RX1_C), GPIO_FN(SDA2_B), GPIO_FN(SDA2_CIS_B), GPIO_FN(MLB_DAT), + GPIO_FN(SPV_EVEN), GPIO_FN(SCIFB1_TXD_D), GPIO_FN(TX1_C), + GPIO_FN(BPFCLK_C), GPIO_FN(RDS_CLK_B), GPIO_FN(SSI_SCK0129), + GPIO_FN(CAN_CLK_B), GPIO_FN(MOUT0), + }; static struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -621,8 +1326,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_1_FN, FN_IP14_24_22, GP_5_0_FN, FN_IP14_21_19 } }, - - /*IPSR0 - IPSR5*/ + /* IPSR0 - IPSR5 */ { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { /* IP6_31_29 [3] */ @@ -696,7 +1400,288 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } }, - /*IPSR8 - IPSR16*/ + { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, + 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2) { + /* IP8_31 [1] */ + 0, 0, + /* IP8_30_29 [2] */ + FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0, + /* IP8_28 [1] */ + FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, + /* IP8_27 [1] */ + FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, + /* IP8_26 [1] */ + FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT, + /* IP8_25_24 [2] */ + FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, + FN_AVB_MAGIC, FN_MII_MAGIC, + /* IP8_23_22 [2] */ + FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0, + /* IP8_21_20 [2] */ + FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, + FN_MII_MDIO, + /* IP8_19_18 [2] */ + FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC, + /* IP8_17_16 [2] */ + FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS, + /* IP8_15_14 [2] */ + FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0, + /* IP8_13_12 [2] */ + FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0, + /* IP8_11_10 [2] */ + FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0, + /* IP8_9_8 [2] */ + FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0, + /* IP8_7_6 [2] */ + FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0, + /* IP8_5_4 [2] */ + FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0, + /* IP8_3_2 [2] */ + FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, + /* IP8_1_0 [2] */ + FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, } + }, + { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, + 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { + /* IP9_31_28 [4] */ + FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, + FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D, + FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, + /* IP9_27_26 [2] */ + FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B, + /* IP9_25_24 [2] */ + FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B, + /* IP9_23_22 [2] */ + FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B, + /* IP9_21_20 [2] */ + FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B, + /* IP9_19_18 [2] */ + FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, + /* IP9_17_16 [2] */ + FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0, + /* IP9_15_12 [4] */ + FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, + FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B, + FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, + /* IP9_11_8 [4] */ + FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, + FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B, + FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, + /* IP9_7_6 [2] */ + FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0, + /* IP9_5_4 [2] */ + FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0, + /* IP9_3_2 [2] */ + FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0, + /* IP9_1_0 [2] */ + FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, + 2, 4, 3, 4, 4, 4, 4, 3, 4) { + /* IP10_31_30 [2] */ + 0, 0, 0, 0, + /* IP10_29_26 [4] */ + FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, + FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, + FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0, + /* IP10_25_23 [3] */ + FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, + FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B, + /* IP10_22_19 [4] */ + FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK, + FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, + FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0, + /* IP10_18_15 [4] */ + FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA, + FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, + FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, + 0, 0, 0, 0, 0, 0, + /* IP10_14_11 [4] */ + FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, + FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, + FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, + 0, 0, 0, 0, 0, 0, 0, + /* IP10_10_7 [4] */ + FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, + FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, + FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, + 0, 0, 0, 0, 0, 0, 0, + /* IP10_6_4 [3] */ + FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, + FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, + FN_VI3_DATA0_B, 0, + /* IP10_3_0 [4] */ + FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, + FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D, + FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, + 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) { + /* IP11_31_30 [2] */ + FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, + /* IP11_29_27 [3] */ + FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, + FN_RDS_CLK_B, 0, 0, + /* IP11_26_24 [3] */ + FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B, + 0, 0, 0, + /* IP11_23_22 [2] */ + FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0, + /* IP11_21_18 [4] */ + FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, + FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F, + FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0, + /* IP11_17_15 [3] */ + FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, + FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0, + /* IP11_14_13 [2] */ + FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0, + /* IP11_12_11 [2] */ + FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0, + /* IP11_10_9 [2] */ + FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0, + /* IP11_8_7 [2] */ + FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0, + /* IP11_6_5 [2] */ + FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0, + /* IP11_4 [1] */ + FN_SD3_CLK, FN_MMC1_CLK, + /* IP11_3_0 [4] */ + FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, + FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, + FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, + 3, 2, 2, 3, 2, 1, 1, 1, 2, 1, + 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) { + /* SEL_SCIF1 [3] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIF1_4, 0, 0, 0, + /* SEL_SCIFB [2] */ + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0, + /* SEL_SCIFB2 [2] */ + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0, + /* SEL_SCIFB1 [3] */ + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, + FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5, + FN_SEL_SCIFB1_6, 0, + /* SEL_SCIFA1 [2] */ + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, + FN_SEL_SCIFA1_3, + /* SEL_SCIF0 [1] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, + /* SEL_SCIFA [1] */ + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + /* SEL_SOF1 [1] */ + FN_SEL_SOF1_0, FN_SEL_SOF1_1, + /* SEL_SSI7 [2] */ + FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0, + /* SEL_SSI6 [1] */ + FN_SEL_SSI6_0, FN_SEL_SSI6_1, + /* SEL_SSI5 [2] */ + FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0, + /* SEL_VI3 [1] */ + FN_SEL_VI3_0, FN_SEL_VI3_1, + /* SEL_VI2 [1] */ + FN_SEL_VI2_0, FN_SEL_VI2_1, + /* SEL_VI1 [1] */ + FN_SEL_VI1_0, FN_SEL_VI1_1, + /* SEL_VI0 [1] */ + FN_SEL_VI0_0, FN_SEL_VI0_1, + /* SEL_TSIF1 [2] */ + FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0, + /* RESERVED [1] */ + 0, 0, + /* SEL_LBS [1] */ + FN_SEL_LBS_0, FN_SEL_LBS_1, + /* SEL_TSIF0 [2] */ + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + /* SEL_SOF3 [1] */ + FN_SEL_SOF3_0, FN_SEL_SOF3_1, + /* SEL_SOF0 [1] */ + FN_SEL_SOF0_0, FN_SEL_SOF0_1, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, + 2, 1, 1, 1, 1, 2, 1, 2, 1, + 2, 1, 1, 1, 3, 3, 2, 3, 2, 2) { + /* RESEVED [2] */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_TMU1 [1] */ + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + /* SEL_HSCIF1 [1] */ + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + /* SEL_SCIFCLK [1] */ + FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, + /* SEL_CAN0 [2] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + /* SEL_CANCLK [1] */ + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, + /* SEL_SCIFA2 [2] */ + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0, + /* SEL_CAN1 [1] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, + /* RESEVED [2] */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_ADI [1] */ + FN_SEL_ADI_0, FN_SEL_ADI_1, + /* SEL_SSP [1] */ + FN_SEL_SSP_0, FN_SEL_SSP_1, + /* SEL_FM [3] */ + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, + FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0, + /* SEL_HSCIF0 [3] */ + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, + FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0, + /* SEL_GPS [2] */ + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0, + /* SEL_RDS [3] */ + FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, + FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0, + /* SEL_SIM [2] */ + FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, + /* SEL_SSI8 [2] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, + 1, 1, 2, 4, 4, 2, 2, + 4, 2, 3, 2, 3, 2) { + /* SEL_IICDVFS [1] */ + FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, + /* SEL_IIC0 [1] */ + FN_SEL_IIC0_0, FN_SEL_IIC0_1, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESEVED [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_IEB [2] */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, + /* RESEVED [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_IIC2 [3] */ + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + FN_SEL_IIC2_4, 0, 0, 0, + /* SEL_IIC1 [2] */ + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0, + /* SEL_I2C2 [3] */ + FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, + FN_SEL_I2C2_4, 0, 0, 0, + /* SEL_I2C1 [2] */ + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, } + }, { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } }, { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { 0, 0, @@ -813,7 +1798,7 @@ static struct pinmux_info r8a7790_pinmux_info = { .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .first_gpio = GPIO_GP_0_0, - .last_gpio = GPIO_FN_MII_RXD2 /* GPIO_FN_TCLK1_B */, + .last_gpio = GPIO_FN_MOUT0, .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c index e123663333..7ea5edc2e5 100644 --- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c @@ -151,8 +151,18 @@ enum { FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20, + /* IPSR0 */ + FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK, + FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1, + FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3, + FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD, + FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, + FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B, + FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4, + FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, + /* - * From IPSR0 to IPSR5 have been removed because they does not use. + * From IPSR1 to IPSR5 have been removed because they does not use. */ /* IPSR6 */ @@ -285,8 +295,20 @@ enum { SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, + /* IPSR0 */ + SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK, + MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK, + SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK, + SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK, + MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK, + CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK, + CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK, + SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK, + SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK, + SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK, + /* - * From IPSR0 to IPSR5 have been removed because they does not use. + * From IPSR1 to IPSR5 have been removed because they does not use. */ /* IPSR6 */ @@ -399,8 +421,55 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2), PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3), + /* IPSR0 */ + PINMUX_IPSR_DATA(IP0_0, SD1_CD), + PINMUX_IPSR_MODSEL_DATA(IP0_0, CAN0_RX, SEL_CAN0_0), + PINMUX_IPSR_DATA(IP0_9_8, SD1_WP), + PINMUX_IPSR_DATA(IP0_9_8, IRQ7), + PINMUX_IPSR_MODSEL_DATA(IP0_9_8, CAN0_TX, SEL_CAN0_0), + PINMUX_IPSR_DATA(IP0_10, MMC_CLK), + PINMUX_IPSR_DATA(IP0_10, SD2_CLK), + PINMUX_IPSR_DATA(IP0_11, MMC_CMD), + PINMUX_IPSR_DATA(IP0_11, SD2_CMD), + PINMUX_IPSR_DATA(IP0_12, MMC_D0), + PINMUX_IPSR_DATA(IP0_12, SD2_DATA0), + PINMUX_IPSR_DATA(IP0_13, MMC_D1), + PINMUX_IPSR_DATA(IP0_13, SD2_DATA1), + PINMUX_IPSR_DATA(IP0_14, MMC_D2), + PINMUX_IPSR_DATA(IP0_14, SD2_DATA2), + PINMUX_IPSR_DATA(IP0_15, MMC_D3), + PINMUX_IPSR_DATA(IP0_15, SD2_DATA3), + PINMUX_IPSR_DATA(IP0_16, MMC_D4), + PINMUX_IPSR_DATA(IP0_16, SD2_CD), + PINMUX_IPSR_DATA(IP0_17, MMC_D5), + PINMUX_IPSR_DATA(IP0_17, SD2_WP), + PINMUX_IPSR_DATA(IP0_19_18, MMC_D6), + PINMUX_IPSR_MODSEL_DATA(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1), + PINMUX_IPSR_MODSEL_DATA(IP0_19_18, CAN1_RX, SEL_CAN1_0), + PINMUX_IPSR_DATA(IP0_21_20, MMC_D7), + PINMUX_IPSR_MODSEL_DATA(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1), + PINMUX_IPSR_MODSEL_DATA(IP0_21_20, CAN1_TX, SEL_CAN1_0), + PINMUX_IPSR_DATA(IP0_23_22, D0), + PINMUX_IPSR_MODSEL_DATA(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1), + PINMUX_IPSR_DATA(IP0_23_22, IRQ4), + PINMUX_IPSR_DATA(IP0_24, D1), + PINMUX_IPSR_MODSEL_DATA(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_DATA(IP0_25, D2), + PINMUX_IPSR_MODSEL_DATA(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_DATA(IP0_27_26, D3), + PINMUX_IPSR_MODSEL_DATA(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1), + PINMUX_IPSR_MODSEL_DATA(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1), + PINMUX_IPSR_DATA(IP0_29_28, D4), + PINMUX_IPSR_MODSEL_DATA(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1), + PINMUX_IPSR_MODSEL_DATA(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1), + PINMUX_IPSR_DATA(IP0_31_30, D5), + PINMUX_IPSR_MODSEL_DATA(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3), + /* - * From IPSR0 to IPSR5 have been removed because they does not use. + * From IPSR1 to IPSR5 have been removed because they does not use. */ /* IPSR6 */ @@ -674,8 +743,23 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(SD1_CLK), GPIO_FN(SD1_CMD), GPIO_FN(SD1_DATA0), GPIO_FN(SD1_DATA1), GPIO_FN(SD1_DATA2), GPIO_FN(SD1_DATA3), + /* IPSR0 */ + GPIO_FN(SD1_CD), GPIO_FN(CAN0_RX), GPIO_FN(SD1_WP), GPIO_FN(IRQ7), + GPIO_FN(CAN0_TX), GPIO_FN(MMC_CLK), GPIO_FN(SD2_CLK), GPIO_FN(MMC_CMD), + GPIO_FN(SD2_CMD), GPIO_FN(MMC_D0), GPIO_FN(SD2_DATA0), GPIO_FN(MMC_D1), + GPIO_FN(SD2_DATA1), GPIO_FN(MMC_D2), GPIO_FN(SD2_DATA2), + GPIO_FN(MMC_D3), GPIO_FN(SD2_DATA3), GPIO_FN(MMC_D4), + GPIO_FN(SD2_CD), GPIO_FN(MMC_D5), GPIO_FN(SD2_WP), GPIO_FN(MMC_D6), + GPIO_FN(SCIF0_RXD), GPIO_FN(I2C2_SCL_B), GPIO_FN(CAN1_RX), + GPIO_FN(MMC_D7), GPIO_FN(SCIF0_TXD), GPIO_FN(I2C2_SDA_B), + GPIO_FN(CAN1_TX), GPIO_FN(D0), GPIO_FN(SCIFA3_SCK_B), GPIO_FN(IRQ4), + GPIO_FN(D1), GPIO_FN(SCIFA3_RXD_B), GPIO_FN(D2), GPIO_FN(SCIFA3_TXD_B), + GPIO_FN(D3), GPIO_FN(I2C3_SCL_B), GPIO_FN(SCIF5_RXD_B), GPIO_FN(D4), + GPIO_FN(I2C3_SDA_B), GPIO_FN(SCIF5_TXD_B), GPIO_FN(D5), + GPIO_FN(SCIF4_RXD_B), GPIO_FN(I2C0_SCL_D), + /* - * From IPSR0 to IPSR5 have been removed because they does not use + * From IPSR1 to IPSR5 have been removed because they does not use. */ /* IPSR6 */ @@ -1017,9 +1101,63 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_1_FN, FN_SD0_CMD, GP_6_0_FN, FN_SD0_CLK } }, + { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, + 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, + 2, 1, 1, 1, 1, 1, 1, 1, 1) { + /* IP0_31_30 [2] */ + FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0, + /* IP0_29_28 [2] */ + FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0, + /* IP0_27_26 [2] */ + FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0, + /* IP0_25 [1] */ + FN_D2, FN_SCIFA3_TXD_B, + /* IP0_24 [1] */ + FN_D1, FN_SCIFA3_RXD_B, + /* IP0_23_22 [2] */ + FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0, + /* IP0_21_20 [2] */ + FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX, + /* IP0_19_18 [2] */ + FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX, + /* IP0_17 [1] */ + FN_MMC_D5, FN_SD2_WP, + /* IP0_16 [1] */ + FN_MMC_D4, FN_SD2_CD, + /* IP0_15 [1] */ + FN_MMC_D3, FN_SD2_DATA3, + /* IP0_14 [1] */ + FN_MMC_D2, FN_SD2_DATA2, + /* IP0_13 [1] */ + FN_MMC_D1, FN_SD2_DATA1, + /* IP0_12 [1] */ + FN_MMC_D0, FN_SD2_DATA0, + /* IP0_11 [1] */ + FN_MMC_CMD, FN_SD2_CMD, + /* IP0_10 [1] */ + FN_MMC_CLK, FN_SD2_CLK, + /* IP0_9_8 [2] */ + FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0, + /* IP0_7 [1] */ + 0, 0, + /* IP0_6 [1] */ + 0, 0, + /* IP0_5 [1] */ + 0, 0, + /* IP0_4 [1] */ + 0, 0, + /* IP0_3 [1] */ + 0, 0, + /* IP0_2 [1] */ + 0, 0, + /* IP0_1 [1] */ + 0, 0, + /* IP0_0 [1] */ + FN_SD1_CD, FN_CAN0_RX, } + }, /* - * From IPSR0 to IPSR5 have been removed because they does not use. + * From IPSR1 to IPSR5 have been removed because they does not use. */ { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c deleted file mode 100644 index 18965a94c5..0000000000 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 2011-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/sc-regs.h> - -void clkrst_init(void) -{ - u32 tmp; - - /* deassert reset */ - tmp = readl(SC_RSTCTRL); - tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1 - | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND; - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ - - /* privide clocks */ - tmp = readl(SC_CLKCTRL); - tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC - | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI; - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ -} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c deleted file mode 100644 index 2cc5df608f..0000000000 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) 2011-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/sg-regs.h> - -void sg_init(void) -{ - u32 tmp; - - /* Set DDR size */ - tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0); - tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1); -#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE - tmp |= SG_MEMCONF_SPARSEMEM; -#endif - writel(tmp, SG_MEMCONF); - - /* Input ports must be enabled before deasserting reset of cores */ - tmp = readl(SG_IECTRL); - tmp |= 0x1; - writel(tmp, SG_IECTRL); -} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c deleted file mode 100644 index 18965a94c5..0000000000 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 2011-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/sc-regs.h> - -void clkrst_init(void) -{ - u32 tmp; - - /* deassert reset */ - tmp = readl(SC_RSTCTRL); - tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1 - | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND; - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ - - /* privide clocks */ - tmp = readl(SC_CLKCTRL); - tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC - | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI; - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ -} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c deleted file mode 100644 index 3c82a1aca4..0000000000 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (C) 2011-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/sbc-regs.h> -#include <asm/arch/sg-regs.h> - -void sbc_init(void) -{ -#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) - /* - * Only CS1 is connected to support card. - * BKSZ[1:0] should be set to "01". - */ - writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); - writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); - writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); - writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); - - if (boot_is_swapped()) { - /* - * Boot Swap On: boot from external NOR/SRAM - * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. - * - * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank - * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals - */ - writel(0x0000bc01, SBBASE0); - } else { - /* - * Boot Swap Off: boot from mask ROM - * 0x00000000-0x01ffffff: mask ROM - * 0x02000000-0x3effffff: memory bank (31MB) - * 0x03f00000-0x3fffffff: peripherals (1MB) - */ - writel(0x0000be01, SBBASE0); /* dummy */ - writel(0x0200be01, SBBASE1); - } -#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD) -#if !defined(CONFIG_SPL_BUILD) - /* XECS0: boot/sub memory (boot swap = off/on) */ - writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); - writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); - writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); - writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); -#endif - /* XECS1: sub/boot memory (boot swap = off/on) */ - writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); - writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); - writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); - writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); - - /* XECS3: peripherals */ - writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); - writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); - writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); - writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); - - writel(0x0000bc01, SBBASE0); /* boot memory */ - writel(0x0400bc01, SBBASE1); /* sub memory */ - writel(0x0800bf01, SBBASE3); /* peripherals */ - -#if !defined(CONFIG_SPL_BUILD) - sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */ -#endif - sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */ - writel(0x00000001, SG_LOADPINCTRL); - -#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */ -} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c deleted file mode 100644 index b7c4b10969..0000000000 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) 2011-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/sg-regs.h> - -void sg_init(void) -{ - u32 tmp; - - /* Set DDR size */ - tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0); - tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1); -#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE - tmp |= SG_MEMCONF_SPARSEMEM; -#endif - writel(tmp, SG_MEMCONF); - - /* Input ports must be enabled before deasserting reset of cores */ - tmp = readl(SG_IECTRL); - tmp |= 1 << 6; - writel(tmp, SG_IECTRL); -} diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 0c102230ae..dee5e258b6 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -16,3 +16,4 @@ obj-y += tlb.o obj-y += transition.o obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/ +obj-$(CONFIG_TARGET_XILINX_ZYNQMP) += zynqmp/ diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile new file mode 100644 index 0000000000..a997e045bd --- /dev/null +++ b/arch/arm/cpu/armv8/zynqmp/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 - 2015 Xilinx, Inc. +# Michal Simek <michal.simek@xilinx.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += clk.o +obj-y += cpu.o diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c new file mode 100644 index 0000000000..0af619d92f --- /dev/null +++ b/arch/arm/cpu/armv8/zynqmp/clk.c @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +unsigned long get_uart_clk(int dev_id) +{ + u32 ver = zynqmp_get_silicon_version(); + + switch (ver) { + case ZYNQMP_CSU_VERSION_EP108: + return 25000000; + } + + return 133000000; +} + +#ifdef CONFIG_CLOCKS +/** + * set_cpu_clk_info() - Initialize clock framework + * Always returns zero. + * + * This function is called from common code after relocation and sets up the + * clock framework. The framework must not be used before this function had been + * called. + */ +int set_cpu_clk_info(void) +{ + gd->cpu_clk = get_tbclk(); + + /* Support Veloce to show at least 1MHz via bdi */ + if (gd->cpu_clk > 1000000) + gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; + else + gd->bd->bi_arm_freq = 1; + + gd->bd->bi_dsp_freq = 0; + + return 0; +} +#endif diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c new file mode 100644 index 0000000000..6fae03c1af --- /dev/null +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> + +#define ZYNQ_SILICON_VER_MASK 0xF000 +#define ZYNQ_SILICON_VER_SHIFT 12 + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int zynqmp_get_silicon_version(void) +{ + gd->cpu_clk = get_tbclk(); + + switch (gd->cpu_clk) { + case 50000000: + return ZYNQMP_CSU_VERSION_QEMU; + } + + return ZYNQMP_CSU_VERSION_EP108; +} diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi index 2a3dd73ead..8ed7bbf53c 100644 --- a/arch/arm/dts/uniphier-ph1-ld4.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for UniPhier PH1-LD4 SoC * - * Copyright (C) 2014 Panasonic Corporation + * Copyright (C) 2014-2015 Panasonic Corporation * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -94,19 +94,19 @@ }; usb0: usb@5a800100 { - compatible = "panasonic,uniphier-ehci", "usb-ehci"; + compatible = "panasonic,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a800100 0x100>; }; usb1: usb@5a810100 { - compatible = "panasonic,uniphier-ehci", "usb-ehci"; + compatible = "panasonic,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a810100 0x100>; }; usb2: usb@5a820100 { - compatible = "panasonic,uniphier-ehci", "usb-ehci"; + compatible = "panasonic,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a820100 0x100>; }; diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts index d9e7a8c52b..5bec92b8f3 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts @@ -36,6 +36,7 @@ i2c3 = &i2c3; i2c5 = &i2c5; i2c6 = &i2c6; + usb0 = &usb0; }; }; @@ -54,7 +55,3 @@ &usb0 { status = "okay"; }; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi index 49e375e8d2..1247779ab0 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for UniPhier PH1-Pro4 SoC * - * Copyright (C) 2014 Panasonic Corporation + * Copyright (C) 2014-2015 Panasonic Corporation * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -119,18 +119,30 @@ status = "ok"; }; - usb0: usb@5a800100 { - compatible = "panasonic,uniphier-ehci", "usb-ehci"; + usb2: usb@5a800100 { + compatible = "panasonic,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a800100 0x100>; }; - usb1: usb@5a810100 { - compatible = "panasonic,uniphier-ehci", "usb-ehci"; + usb3: usb@5a810100 { + compatible = "panasonic,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a810100 0x100>; }; + usb0: usb@65a00000 { + compatible = "panasonic,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65a00000 0x100>; + }; + + usb1: usb@65c00000 { + compatible = "panasonic,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65c00000 0x100>; + }; + nand: nand@68000000 { compatible = "denali,denali-nand-dt"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi index f5529d2e6e..88322c6a8c 100644 --- a/arch/arm/dts/uniphier-ph1-sld3.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for UniPhier PH1-sLD3 SoC * - * Copyright (C) 2014 Panasonic Corporation + * Copyright (C) 2014-2015 Panasonic Corporation * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -93,25 +93,25 @@ }; usb0: usb@5a800100 { - compatible = "panasonic,uniphier-ehci", "usb-ehci"; + compatible = "panasonic,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a800100 0x100>; }; usb1: usb@5a810100 { - compatible = "panasonic,uniphier-ehci", "usb-ehci"; + compatible = "panasonic,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a810100 0x100>; }; usb2: usb@5a820100 { - compatible = "panasonic,uniphier-ehci", "usb-ehci"; + compatible = "panasonic,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a820100 0x100>; }; usb3: usb@5a830100 { - compatible = "panasonic,uniphier-ehci", "usb-ehci"; + compatible = "panasonic,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a830100 0x100>; }; diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi index 0ea76e59fc..1b3eb228c8 100644 --- a/arch/arm/dts/uniphier-ph1-sld8.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for UniPhier PH1-sLD8 SoC * - * Copyright (C) 2014 Panasonic Corporation + * Copyright (C) 2014-2015 Panasonic Corporation * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -94,19 +94,19 @@ }; usb0: usb@5a800100 { - compatible = "panasonic,uniphier-ehci", "usb-ehci"; + compatible = "panasonic,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a800100 0x100>; }; usb1: usb@5a810100 { - compatible = "panasonic,uniphier-ehci", "usb-ehci"; + compatible = "panasonic,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a810100 0x100>; }; usb2: usb@5a820100 { - compatible = "panasonic,uniphier-ehci", "usb-ehci"; + compatible = "panasonic,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a820100 0x100>; }; diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 29674ad4da..e7395201ad 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -153,6 +153,10 @@ #define EXYNOS5420_CLOCK_BASE 0x10010000 #define EXYNOS5420_POWER_BASE 0x10040000 #define EXYNOS5420_SWRESET 0x10040400 +#define EXYNOS5420_INFORM_BASE 0x10040800 +#define EXYNOS5420_SPARE_BASE 0x10040900 +#define EXYNOS5420_CPU_CONFIG_BASE 0x10042000 +#define EXYNOS5420_CPU_STATUS_BASE 0x10042004 #define EXYNOS5420_SYSREG_BASE 0x10050000 #define EXYNOS5420_TZPC_BASE 0x100E0000 #define EXYNOS5420_WATCHDOG_BASE 0x101D0000 @@ -186,6 +190,7 @@ #define EXYNOS5420_USB3PHY_BASE DEVICE_NOT_AVAILABLE #define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE + #ifndef __ASSEMBLY__ #include <asm/io.h> /* CPU detection macros */ diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h index 4968d3dd2e..3ffb296a57 100644 --- a/arch/arm/include/asm/arch-exynos/system.h +++ b/arch/arm/include/asm/arch-exynos/system.h @@ -37,6 +37,94 @@ struct exynos5_sysreg { #define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) +/* + * Data Synchronization Barrier acts as a special kind of memory barrier. + * No instruction in program order after this instruction executes until + * this instruction completes. This instruction completes when: + * - All explicit memory accesses before this instruction complete. + * - All Cache, Branch predictor and TLB maintenance operations before + * this instruction complete. + */ +#define dsb() __asm__ __volatile__ ("dsb\n\t" : : ); + +/* + * This instruction causes an event to be signaled to all cores + * within a multiprocessor system. If SEV is implemented, + * WFE must also be implemented. + */ +#define sev() __asm__ __volatile__ ("sev\n\t" : : ); +/* + * If the Event Register is not set, WFE suspends execution until + * one of the following events occurs: + * - an IRQ interrupt, unless masked by the CPSR I-bit + * - an FIQ interrupt, unless masked by the CPSR F-bit + * - an Imprecise Data abort, unless masked by the CPSR A-bit + * - a Debug Entry request, if Debug is enabled + * - an Event signaled by another processor using the SEV instruction. + * If the Event Register is set, WFE clears it and returns immediately. + * If WFE is implemented, SEV must also be implemented. + */ +#define wfe() __asm__ __volatile__ ("wfe\n\t" : : ); + +/* Move 0xd3 value to CPSR register to enable SVC mode */ +#define svc32_mode_en() __asm__ __volatile__ \ + ("@ I&F disable, Mode: 0x13 - SVC\n\t" \ + "msr cpsr_c, #0x13|0xC0\n\t" : : ) + +/* Set program counter with the given value */ +#define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x)) + +/* Branch to the given location */ +#define branch_bx(x) __asm__ __volatile__ ("bx %0\n\t" : : "r"(x)) + +/* Read Main Id register */ +#define mrc_midr(x) __asm__ __volatile__ \ + ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(x) : ) + +/* Read Multiprocessor Affinity Register */ +#define mrc_mpafr(x) __asm__ __volatile__ \ + ("mrc p15, 0, %0, c0, c0, 5\n\t" : "=r"(x) : ) + +/* Read System Control Register */ +#define mrc_sctlr(x) __asm__ __volatile__ \ + ("mrc p15, 0, %0, c1, c0, 0\n\t" : "=r"(x) : ) + +/* Read Auxiliary Control Register */ +#define mrc_auxr(x) __asm__ __volatile__ \ + ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(x) : ) + +/* Read L2 Control register */ +#define mrc_l2_ctlr(x) __asm__ __volatile__ \ + ("mrc p15, 1, %0, c9, c0, 2\n\t" : "=r"(x) : ) + +/* Read L2 Auxilliary Control register */ +#define mrc_l2_aux_ctlr(x) __asm__ __volatile__ \ + ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(x) : ) + +/* Write System Control Register */ +#define mcr_sctlr(x) __asm__ __volatile__ \ + ("mcr p15, 0, %0, c1, c0, 0\n\t" : : "r"(x)) + +/* Write Auxiliary Control Register */ +#define mcr_auxr(x) __asm__ __volatile__ \ + ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(x)) + +/* Invalidate all instruction caches to PoU */ +#define mcr_icache(x) __asm__ __volatile__ \ + ("mcr p15, 0, %0, c7, c5, 0\n\t" : : "r"(x)) + +/* Invalidate unified TLB */ +#define mcr_tlb(x) __asm__ __volatile__ \ + ("mcr p15, 0, %0, c8, c7, 0\n\t" : : "r"(x)) + +/* Write L2 Control register */ +#define mcr_l2_ctlr(x) __asm__ __volatile__ \ + ("mcr p15, 1, %0, c9, c0, 2\n\t" : : "r"(x)) + +/* Write L2 Auxilliary Control register */ +#define mcr_l2_aux_ctlr(x) __asm__ __volatile__ \ + ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(x)) + void set_usbhost_mode(unsigned int mode); void set_system_display_ctrl(void); int exynos_lcd_early_init(const void *blob); diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h index a45a67c4d6..8a002a8918 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h @@ -74,8 +74,23 @@ enum { GPIO_FN_SD1_CLK, GPIO_FN_SD1_CMD, GPIO_FN_SD1_DATA0, GPIO_FN_SD1_DATA1, GPIO_FN_SD1_DATA2, GPIO_FN_SD1_DATA3, + /* IPSR0 */ + GPIO_FN_SD1_CD, GPIO_FN_CAN0_RX, GPIO_FN_SD1_WP, GPIO_FN_IRQ7, + GPIO_FN_CAN0_TX, GPIO_FN_MMC_CLK, GPIO_FN_SD2_CLK, GPIO_FN_MMC_CMD, + GPIO_FN_SD2_CMD, GPIO_FN_MMC_D0, GPIO_FN_SD2_DATA0, GPIO_FN_MMC_D1, + GPIO_FN_SD2_DATA1, GPIO_FN_MMC_D2, GPIO_FN_SD2_DATA2, + GPIO_FN_MMC_D3, GPIO_FN_SD2_DATA3, GPIO_FN_MMC_D4, + GPIO_FN_SD2_CD, GPIO_FN_MMC_D5, GPIO_FN_SD2_WP, GPIO_FN_MMC_D6, + GPIO_FN_SCIF0_RXD, GPIO_FN_I2C2_SCL_B, GPIO_FN_CAN1_RX, GPIO_FN_MMC_D7, + GPIO_FN_SCIF0_TXD, GPIO_FN_I2C2_SDA_B, GPIO_FN_CAN1_TX, GPIO_FN_D0, + GPIO_FN_SCIFA3_SCK_B, GPIO_FN_IRQ4, GPIO_FN_D1, GPIO_FN_SCIFA3_RXD_B, + GPIO_FN_D2, GPIO_FN_SCIFA3_TXD_B, GPIO_FN_D3, GPIO_FN_I2C3_SCL_B, + GPIO_FN_SCIF5_RXD_B, GPIO_FN_D4, GPIO_FN_I2C3_SDA_B, + GPIO_FN_SCIF5_TXD_B, GPIO_FN_D5, GPIO_FN_SCIF4_RXD_B, + GPIO_FN_I2C0_SCL_D, + /* - * From IPSR0 to IPSR5 have been removed because they does not use. + * From IPSR1 to IPSR5 have been removed because they does not use. */ /* IPSR6 */ @@ -144,9 +159,54 @@ enum { GPIO_FN_SCIF5_RXD, GPIO_FN_I2C2_SCL_C, GPIO_FN_DU1_DR2, GPIO_FN_RIF1_D0_B, GPIO_FN_TS_SDEN_D, GPIO_FN_FMCLK_C, GPIO_FN_RDS_CLK, - /* - * From IPSR9 to IPSR10 have been removed because they does not use. - */ + /* IPSR9 */ + GPIO_FN_MSIOF0_TXD, GPIO_FN_SCIF5_TXD, GPIO_FN_I2C2_SDA_C, + GPIO_FN_DU1_DR3, GPIO_FN_RIF1_D1_B, GPIO_FN_TS_SPSYNC_D, GPIO_FN_FMIN_C, + GPIO_FN_RDS_DATA, GPIO_FN_MSIOF0_SCK, GPIO_FN_IRQ0, GPIO_FN_TS_SDATA, + GPIO_FN_DU1_DR4, GPIO_FN_RIF1_SYNC, GPIO_FN_TPUTO1_C, + GPIO_FN_MSIOF0_SYNC, GPIO_FN_PWM1, GPIO_FN_TS_SCK, GPIO_FN_DU1_DR5, + GPIO_FN_RIF1_CLK, GPIO_FN_BPFCLK_B, GPIO_FN_MSIOF0_SS1, + GPIO_FN_SCIFA0_RXD, GPIO_FN_TS_SDEN, GPIO_FN_DU1_DR6, GPIO_FN_RIF1_D0, + GPIO_FN_FMCLK_B, GPIO_FN_RDS_CLK_B, GPIO_FN_MSIOF0_SS2, + GPIO_FN_SCIFA0_TXD, GPIO_FN_TS_SPSYNC, GPIO_FN_DU1_DR7, GPIO_FN_RIF1_D1, + GPIO_FN_FMIN_B, GPIO_FN_RDS_DATA_B, GPIO_FN_HSCIF1_HRX, + GPIO_FN_I2C4_SCL, GPIO_FN_PWM6, GPIO_FN_DU1_DG0, GPIO_FN_HSCIF1_HTX, + GPIO_FN_I2C4_SDA, GPIO_FN_TPUTO1, GPIO_FN_DU1_DG1, GPIO_FN_HSCIF1_HSCK, + GPIO_FN_PWM2, GPIO_FN_IETX, GPIO_FN_DU1_DG2, GPIO_FN_REMOCON_B, + GPIO_FN_SPEEDIN_B, GPIO_FN_VSP_B, GPIO_FN_HSCIF1_HCTS_N, + GPIO_FN_SCIFA4_RXD, GPIO_FN_IECLK, GPIO_FN_DU1_DG3, GPIO_FN_SSI_SCK1_B, + GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_CC50_STATE32, + GPIO_FN_HSCIF1_HRTS_N, GPIO_FN_SCIFA4_TXD, GPIO_FN_IERX, + GPIO_FN_DU1_DG4, GPIO_FN_SSI_WS1_B, GPIO_FN_CAN_STEP0, + GPIO_FN_CC50_STATE33, GPIO_FN_SCIF1_SCK, GPIO_FN_PWM3, GPIO_FN_TCLK2, + GPIO_FN_DU1_DG5, GPIO_FN_SSI_SDATA1_B, GPIO_FN_CAN_TXCLK, + GPIO_FN_CC50_STATE34, + + /* IPSR10 */ + GPIO_FN_SCIF1_RXD, GPIO_FN_IIC0_SCL, GPIO_FN_DU1_DG6, + GPIO_FN_SSI_SCK2_B, GPIO_FN_CAN_DEBUGOUT0, GPIO_FN_CC50_STATE35, + GPIO_FN_SCIF1_TXD, GPIO_FN_IIC0_SDA, GPIO_FN_DU1_DG7, GPIO_FN_SSI_WS2_B, + GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_CC50_STATE36, GPIO_FN_SCIF2_RXD, + GPIO_FN_IIC1_SCL, GPIO_FN_DU1_DB0, GPIO_FN_SSI_SDATA2_B, + GPIO_FN_USB0_EXTLP, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_CC50_STATE37, + GPIO_FN_SCIF2_TXD, GPIO_FN_IIC1_SDA, GPIO_FN_DU1_DB1, + GPIO_FN_SSI_SCK9_B, GPIO_FN_USB0_OVC1, GPIO_FN_CAN_DEBUGOUT3, + GPIO_FN_CC50_STATE38, GPIO_FN_SCIF2_SCK, GPIO_FN_IRQ1, GPIO_FN_DU1_DB2, + GPIO_FN_SSI_WS9_B, GPIO_FN_USB0_IDIN, GPIO_FN_CAN_DEBUGOUT4, + GPIO_FN_CC50_STATE39, GPIO_FN_SCIF3_SCK, GPIO_FN_IRQ2, GPIO_FN_BPFCLK_D, + GPIO_FN_DU1_DB3, GPIO_FN_SSI_SDATA9_B, GPIO_FN_TANS2, + GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_CC50_OSCOUT, GPIO_FN_SCIF3_RXD, + GPIO_FN_I2C1_SCL_E, GPIO_FN_FMCLK_D, GPIO_FN_DU1_DB4, + GPIO_FN_AUDIO_CLKA_C, GPIO_FN_SSI_SCK4_B, GPIO_FN_CAN_DEBUGOUT6, + GPIO_FN_RDS_CLK_C, GPIO_FN_SCIF3_TXD, GPIO_FN_I2C1_SDA_E, + GPIO_FN_FMIN_D, GPIO_FN_DU1_DB5, GPIO_FN_AUDIO_CLKB_C, + GPIO_FN_SSI_WS4_B, GPIO_FN_CAN_DEBUGOUT7, GPIO_FN_RDS_DATA_C, + GPIO_FN_I2C2_SCL, GPIO_FN_SCIFA5_RXD, GPIO_FN_DU1_DB6, + GPIO_FN_AUDIO_CLKC_C, GPIO_FN_SSI_SDATA4_B, GPIO_FN_CAN_DEBUGOUT8, + GPIO_FN_I2C2_SDA, GPIO_FN_SCIFA5_TXD, GPIO_FN_DU1_DB7, + GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SCK5, + GPIO_FN_SCIFA3_SCK, GPIO_FN_CAN_DEBUGOUT10, + GPIO_FN_DU1_DOTCLKIN, /* IPSR11 */ GPIO_FN_SSI_WS5, GPIO_FN_SCIFA3_RXD, GPIO_FN_I2C3_SCL_C, @@ -168,9 +228,49 @@ enum { GPIO_FN_AD_DO_B, GPIO_FN_SSI_SDATA0, GPIO_FN_MSIOF1_SCK_B, GPIO_FN_PWM0_B, GPIO_FN_ADICLK_B, GPIO_FN_AD_CLK_B, - /* - * From IPSR12 to IPSR13 have been removed because they does not use. - */ + /* IPSR12 */ + GPIO_FN_SSI_SCK34, GPIO_FN_MSIOF1_SYNC_B, GPIO_FN_SCIFA1_SCK_C, + GPIO_FN_ADICHS0_B, GPIO_FN_AD_NCS_N_B, GPIO_FN_DREQ1_N_B, + GPIO_FN_SSI_WS34, GPIO_FN_MSIOF1_SS1_B, GPIO_FN_SCIFA1_RXD_C, + GPIO_FN_ADICHS1_B, GPIO_FN_CAN1_RX_C, GPIO_FN_DACK1_B, + GPIO_FN_SSI_SDATA3, GPIO_FN_MSIOF1_SS2_B, GPIO_FN_SCIFA1_TXD_C, + GPIO_FN_ADICHS2_B, GPIO_FN_CAN1_TX_C, GPIO_FN_DREQ2_N, GPIO_FN_SSI_SCK4, + GPIO_FN_MLB_CK, GPIO_FN_IETX_B, GPIO_FN_IRD_TX, GPIO_FN_SSI_WS4, + GPIO_FN_MLB_SIG, GPIO_FN_IECLK_B, GPIO_FN_IRD_RX, GPIO_FN_SSI_SDATA4, + GPIO_FN_MLB_DAT, GPIO_FN_IERX_B, GPIO_FN_IRD_SCK, GPIO_FN_SSI_SDATA8, + GPIO_FN_SCIF1_SCK_B, GPIO_FN_PWM1_B, GPIO_FN_IRQ9, GPIO_FN_REMOCON, + GPIO_FN_DACK2, GPIO_FN_ETH_MDIO_B, GPIO_FN_SSI_SCK1, + GPIO_FN_SCIF1_RXD_B, GPIO_FN_IIC1_SCL_C, GPIO_FN_VI1_CLK, + GPIO_FN_CAN0_RX_D, GPIO_FN_AVB_AVTP_CAPTURE, GPIO_FN_ETH_CRS_DV_B, + GPIO_FN_SSI_WS1, GPIO_FN_SCIF1_TXD_B, GPIO_FN_IIC1_SDA_C, + GPIO_FN_VI1_DATA0, GPIO_FN_CAN0_TX_D, GPIO_FN_AVB_AVTP_MATCH, + GPIO_FN_ETH_RX_ER_B, GPIO_FN_SSI_SDATA1, GPIO_FN_HSCIF1_HRX_B, + GPIO_FN_VI1_DATA1, GPIO_FN_SDATA, GPIO_FN_ATAG0_N, GPIO_FN_ETH_RXD0_B, + GPIO_FN_SSI_SCK2, GPIO_FN_HSCIF1_HTX_B, GPIO_FN_VI1_DATA2, + GPIO_FN_MDATA, GPIO_FN_ATAWR0_N, GPIO_FN_ETH_RXD1_B, + + /* IPSR13 */ + GPIO_FN_SSI_WS2, GPIO_FN_HSCIF1_HCTS_N_B, GPIO_FN_SCIFA0_RXD_D, + GPIO_FN_VI1_DATA3, GPIO_FN_SCKZ, GPIO_FN_ATACS00_N, GPIO_FN_ETH_LINK_B, + GPIO_FN_SSI_SDATA2, GPIO_FN_HSCIF1_HRTS_N_B, GPIO_FN_SCIFA0_TXD_D, + GPIO_FN_VI1_DATA4, GPIO_FN_STM_N, GPIO_FN_ATACS10_N, + GPIO_FN_ETH_REFCLK_B, GPIO_FN_SSI_SCK9, GPIO_FN_SCIF2_SCK_B, + GPIO_FN_PWM2_B, GPIO_FN_VI1_DATA5, GPIO_FN_MTS_N, GPIO_FN_EX_WAIT1, + GPIO_FN_ETH_TXD1_B, GPIO_FN_SSI_WS9, GPIO_FN_SCIF2_RXD_B, + GPIO_FN_I2C3_SCL_E, GPIO_FN_VI1_DATA6, GPIO_FN_ATARD0_N, + GPIO_FN_ETH_TX_EN_B, GPIO_FN_SSI_SDATA9, GPIO_FN_SCIF2_TXD_B, + GPIO_FN_I2C3_SDA_E, GPIO_FN_VI1_DATA7, GPIO_FN_ATADIR0_N, + GPIO_FN_ETH_MAGIC_B, GPIO_FN_AUDIO_CLKA, GPIO_FN_I2C0_SCL_B, + GPIO_FN_SCIFA4_RXD_D, GPIO_FN_VI1_CLKENB, GPIO_FN_TS_SDATA_C, + GPIO_FN_RIF0_SYNC_B, GPIO_FN_ETH_TXD0_B, GPIO_FN_AUDIO_CLKB, + GPIO_FN_I2C0_SDA_B, GPIO_FN_SCIFA4_TXD_D, GPIO_FN_VI1_FIELD, + GPIO_FN_TS_SCK_C, GPIO_FN_RIF0_CLK_B, GPIO_FN_BPFCLK_E, + GPIO_FN_ETH_MDC_B, GPIO_FN_AUDIO_CLKC, GPIO_FN_I2C4_SCL_B, + GPIO_FN_SCIFA5_RXD_D, GPIO_FN_VI1_HSYNC_N, GPIO_FN_TS_SDEN_C, + GPIO_FN_RIF0_D0_B, GPIO_FN_FMCLK_E, GPIO_FN_RDS_CLK_D, + GPIO_FN_AUDIO_CLKOUT, GPIO_FN_I2C4_SDA_B, GPIO_FN_SCIFA5_TXD_D, + GPIO_FN_VI1_VSYNC_N, GPIO_FN_TS_SPSYNC_C, GPIO_FN_RIF0_D1_B, + GPIO_FN_FMIN_E, GPIO_FN_RDS_DATA_D, }; #endif /* __ASM_R8A7794_H__ */ diff --git a/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h b/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h deleted file mode 100644 index e9c5fb4af8..0000000000 --- a/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (C) 2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __PLAT_UNIPHIER_EHCI_H -#define __PLAT_UNIPHIER_EHCI_H - -#include <linux/types.h> -#include <asm/io.h> -#include "mio-regs.h" - -struct uniphier_ehci_platform_data { - unsigned long base; -}; - -extern struct uniphier_ehci_platform_data uniphier_ehci_platdata[]; - -static inline void uniphier_ehci_reset(int index, int on) -{ - u32 tmp; - - tmp = readl(MIO_USB_RSTCTRL(index)); - if (on) - tmp &= ~MIO_USB_RSTCTRL_XRST; - else - tmp |= MIO_USB_RSTCTRL_XRST; - writel(tmp, MIO_USB_RSTCTRL(index)); -} - -#endif /* __PLAT_UNIPHIER_EHCI_H */ diff --git a/arch/arm/include/asm/arch-zynqmp/clk.h b/arch/arm/include/asm/arch-zynqmp/clk.h new file mode 100644 index 0000000000..d55bc31c43 --- /dev/null +++ b/arch/arm/include/asm/arch-zynqmp/clk.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_CLK_H_ +#define _ASM_ARCH_CLK_H_ + +unsigned long get_uart_clk(int dev_id); + +#endif /* _ASM_ARCH_CLK_H_ */ diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h new file mode 100644 index 0000000000..97fb49a2a7 --- /dev/null +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +#define ZYNQ_SERIAL_BASEADDR0 0xFF000000 +#define ZYNQ_SERIAL_BASEADDR1 0xFF001000 + +#define ZYNQ_SDHCI_BASEADDR0 0xFF160000 +#define ZYNQ_SDHCI_BASEADDR1 0xFF170000 + +#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 +#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 + +struct crlapb_regs { + u32 reserved0[74]; + u32 timestamp_ref_ctrl; /* 0x128 */ + u32 reserved0_1[53]; + u32 boot_mode; /* 0x200 */ + u32 reserved1[26]; +}; + +#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) + +#define ZYNQMP_IOU_SCNTR 0xFF250000 +#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 +#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 + +struct iou_scntr { + u32 counter_control_register; + u32 reserved0[7]; + u32 base_frequency_id_register; +}; + +#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR) + +/* Bootmode setting values */ +#define BOOT_MODES_MASK 0x0000000F +#define SD_MODE 0x00000005 +#define JTAG_MODE 0x00000000 + +/* Board version value */ +#define ZYNQMP_CSU_VERSION_SILICON 0x0 +#define ZYNQMP_CSU_VERSION_EP108 0x1 +#define ZYNQMP_CSU_VERSION_QEMU 0x3 + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h new file mode 100644 index 0000000000..d8e0ba1588 --- /dev/null +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_SYS_PROTO_H +#define _ASM_ARCH_SYS_PROTO_H + +int zynq_sdhci_init(unsigned long regbase); + +unsigned int zynqmp_get_silicon_version(void); + +#endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a13da23cf1..edb3b80015 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -58,6 +58,7 @@ #ifndef __ASSEMBLY__ #include <linux/types.h> +#include <asm/io.h> /* * CP15 Barrier instructions @@ -69,6 +70,50 @@ #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) +/* + * Workaround for ARM errata # 798870 + * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been + * stalled for 1024 cycles to verify that its hazard condition still exists. + */ +static inline void v7_enable_l2_hazard_detect(void) +{ + uint32_t val; + + /* L2ACTLR[7]: Enable hazard detect timeout */ + asm volatile ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(val)); + val |= (1 << 7); + asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(val)); +} + +/* + * Workaround for ARM errata # 799270 + * Ensure that the L2 logic has been used within the previous 256 cycles + * before modifying the ACTLR.SMP bit. This is required during boot before + * MMU has been enabled, or during a specified reset or power down sequence. + */ +static inline void v7_enable_smp(uint32_t address) +{ + uint32_t temp, val; + + /* Read auxiliary control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val)); + + /* Enable SMP */ + val |= (1 << 6); + + /* Dummy read to assure L2 access */ + temp = readl(address); + temp &= 0; + val |= temp; + + /* Write auxiliary control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val)); + + CP15DSB; + CP15ISB; +} + +void v7_en_l2_hazard_detect(void); void v7_outer_cache_enable(void); void v7_outer_cache_disable(void); void v7_outer_cache_flush_all(void); diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 17b6f544da..6db405d7d9 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -37,6 +37,8 @@ void spl_board_load_image(void); /* Linker symbols. */ extern char __bss_start[], __bss_end[]; +#ifndef CONFIG_DM extern gd_t gdata; +#endif #endif diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 22df3e5b83..7939cedede 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -113,7 +113,14 @@ here: /* Set up final (full) environment */ bl c_runtime_cpu_setup /* we still call old routine here */ - +#endif +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FRAMEWORK) +# ifdef CONFIG_SPL_BUILD + /* Use a DRAM stack for the rest of SPL, if requested */ + bl spl_relocate_stack_gd + cmp r0, #0 + movne sp, r0 +# endif ldr r0, =__bss_start /* this is auto-relocated! */ ldr r1, =__bss_end /* this is auto-relocated! */ @@ -124,9 +131,10 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */ addlo r0, r0, #4 /* move to next */ blo clbss_l +#if ! defined(CONFIG_SPL_BUILD) bl coloured_LED_init bl red_led_on - +#endif /* call board_init_r(gd_t *id, ulong dest_addr) */ mov r0, r9 /* gd_t */ ldr r1, [r9, #GD_RELOCADDR] /* dest_addr */ @@ -134,7 +142,6 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */ ldr pc, =board_init_r /* this is auto-relocated! */ /* we should not return here. */ - #endif ENDPROC(_main) diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index c41850aaee..bd8c7d2ede 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -13,6 +13,7 @@ #include <image.h> #include <linux/compiler.h> +#ifndef CONFIG_DM /* Pointer to as well as the global data structure for SPL */ DECLARE_GLOBAL_DATA_PTR; @@ -21,6 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; * pafches that rely on it. The global_data area is set up in crt0.S. */ gd_t gdata __attribute__ ((section(".data"))); +#endif /* * In the context of SPL, board_init_f must ensure that any clocks/etc for @@ -33,8 +35,10 @@ void __weak board_init_f(ulong dummy) /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); +#ifndef CONFIG_DM /* TODO: Remove settings of the global data pointer here */ gd = &gdata; +#endif board_init_r(NULL, 0); } diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 8615248377..fccfd79648 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -29,6 +29,9 @@ config USE_PRIVATE_LIBGCC config DM default y +config SPL_DM + default y + config DM_SERIAL default y diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 8335685e32..8335685e32 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index df418dd3c4..e7a801b2ac 100644 --- a/arch/arm/cpu/armv7/uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -7,6 +7,7 @@ ifdef CONFIG_SPL_BUILD obj-y += lowlevel_init.o obj-y += init_page_table.o obj-y += spl.o +obj-y += memconf.o obj-y += ddrphy_training.o else diff --git a/arch/arm/cpu/armv7/uniphier/board_common.c b/arch/arm/mach-uniphier/board_common.c index 3fb26c6d84..5f2d5f6f5b 100644 --- a/arch/arm/cpu/armv7/uniphier/board_common.c +++ b/arch/arm/mach-uniphier/board_common.c @@ -6,7 +6,7 @@ */ #include <common.h> -#include <asm/arch/led.h> +#include <mach/led.h> /* * Routine: board_init diff --git a/arch/arm/cpu/armv7/uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c index d25bbaec08..7108740408 100644 --- a/arch/arm/cpu/armv7/uniphier/board_early_init_f.c +++ b/arch/arm/mach-uniphier/board_early_init_f.c @@ -5,10 +5,11 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <asm/arch/led.h> -#include <asm/arch/board.h> +#include <mach/led.h> +#include <mach/board.h> void pin_init(void); +void clkrst_init(void); int board_early_init_f(void) { @@ -18,5 +19,9 @@ int board_early_init_f(void) led_write(U, 1, , ); + clkrst_init(); + + led_write(U, 2, , ); + return 0; } diff --git a/arch/arm/cpu/armv7/uniphier/board_early_init_r.c b/arch/arm/mach-uniphier/board_early_init_r.c index cb7e04fc36..579fe70463 100644 --- a/arch/arm/cpu/armv7/uniphier/board_early_init_r.c +++ b/arch/arm/mach-uniphier/board_early_init_r.c @@ -6,7 +6,7 @@ */ #include <common.h> -#include <asm/arch/board.h> +#include <mach/board.h> int board_early_init_r(void) { diff --git a/arch/arm/cpu/armv7/uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 0622a1e16e..0622a1e16e 100644 --- a/arch/arm/cpu/armv7/uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c diff --git a/arch/arm/cpu/armv7/uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/cache_uniphier.c index e47f977fe5..52f3c7c7a6 100644 --- a/arch/arm/cpu/armv7/uniphier/cache_uniphier.c +++ b/arch/arm/mach-uniphier/cache_uniphier.c @@ -8,7 +8,7 @@ #include <common.h> #include <asm/io.h> #include <asm/armv7.h> -#include <asm/arch/ssc-regs.h> +#include <mach/ssc-regs.h> #ifdef CONFIG_UNIPHIER_L2CACHE_ON static void uniphier_cache_maint_all(u32 operation) diff --git a/arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c b/arch/arm/mach-uniphier/cmd_ddrphy.c index 431d9010f1..5f44927b17 100644 --- a/arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c +++ b/arch/arm/mach-uniphier/cmd_ddrphy.c @@ -7,7 +7,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/ddrphy-regs.h> +#include <mach/ddrphy-regs.h> /* Select either decimal or hexadecimal */ #if 1 diff --git a/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c b/arch/arm/mach-uniphier/cmd_pinmon.c index 3c1b325976..8be2ed4fe6 100644 --- a/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c +++ b/arch/arm/mach-uniphier/cmd_pinmon.c @@ -6,8 +6,8 @@ */ #include <common.h> -#include <asm/arch/boot-device.h> -#include <asm/arch/sbc-regs.h> +#include <mach/boot-device.h> +#include <mach/sbc-regs.h> static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/arch/arm/cpu/armv7/uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c index 86d079ad56..13a0b1e48f 100644 --- a/arch/arm/cpu/armv7/uniphier/cpu_info.c +++ b/arch/arm/mach-uniphier/cpu_info.c @@ -7,7 +7,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/sg-regs.h> +#include <mach/sg-regs.h> int print_cpuinfo(void) { diff --git a/arch/arm/cpu/armv7/uniphier/ddrphy_training.c b/arch/arm/mach-uniphier/ddrphy_training.c index cc8b8ad648..b1d46cf627 100644 --- a/arch/arm/cpu/armv7/uniphier/ddrphy_training.c +++ b/arch/arm/mach-uniphier/ddrphy_training.c @@ -7,7 +7,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/ddrphy-regs.h> +#include <mach/ddrphy-regs.h> void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank) { diff --git a/arch/arm/cpu/armv7/uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 4b8c938b5e..4b8c938b5e 100644 --- a/arch/arm/cpu/armv7/uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c diff --git a/arch/arm/include/asm/arch-uniphier/arm-mpcore.h b/arch/arm/mach-uniphier/include/mach/arm-mpcore.h index cf7cd46c10..cf7cd46c10 100644 --- a/arch/arm/include/asm/arch-uniphier/arm-mpcore.h +++ b/arch/arm/mach-uniphier/include/mach/arm-mpcore.h diff --git a/arch/arm/include/asm/arch-uniphier/bcu-regs.h b/arch/arm/mach-uniphier/include/mach/bcu-regs.h index 0dfd94e5d7..0dfd94e5d7 100644 --- a/arch/arm/include/asm/arch-uniphier/bcu-regs.h +++ b/arch/arm/mach-uniphier/include/mach/bcu-regs.h diff --git a/arch/arm/include/asm/arch-uniphier/board.h b/arch/arm/mach-uniphier/include/mach/board.h index e3cba5befe..e3cba5befe 100644 --- a/arch/arm/include/asm/arch-uniphier/board.h +++ b/arch/arm/mach-uniphier/include/mach/board.h diff --git a/arch/arm/include/asm/arch-uniphier/boot-device.h b/arch/arm/mach-uniphier/include/mach/boot-device.h index 7a10f1c5b2..7a10f1c5b2 100644 --- a/arch/arm/include/asm/arch-uniphier/boot-device.h +++ b/arch/arm/mach-uniphier/include/mach/boot-device.h diff --git a/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h index 6b7d600a9c..6b7d600a9c 100644 --- a/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h diff --git a/arch/arm/include/asm/arch-uniphier/debug-uart.S b/arch/arm/mach-uniphier/include/mach/debug-uart.S index af55feed04..af55feed04 100644 --- a/arch/arm/include/asm/arch-uniphier/debug-uart.S +++ b/arch/arm/mach-uniphier/include/mach/debug-uart.S diff --git a/arch/arm/include/asm/arch-uniphier/led.h b/arch/arm/mach-uniphier/include/mach/led.h index 21277dac76..21277dac76 100644 --- a/arch/arm/include/asm/arch-uniphier/led.h +++ b/arch/arm/mach-uniphier/include/mach/led.h diff --git a/arch/arm/include/asm/arch-uniphier/mio-regs.h b/arch/arm/mach-uniphier/include/mach/mio-regs.h index 3306934ff7..3306934ff7 100644 --- a/arch/arm/include/asm/arch-uniphier/mio-regs.h +++ b/arch/arm/mach-uniphier/include/mach/mio-regs.h diff --git a/arch/arm/include/asm/arch-uniphier/platdevice.h b/arch/arm/mach-uniphier/include/mach/platdevice.h index 62a512659c..cdf7d132d4 100644 --- a/arch/arm/include/asm/arch-uniphier/platdevice.h +++ b/arch/arm/mach-uniphier/include/mach/platdevice.h @@ -21,6 +21,4 @@ U_BOOT_DEVICE(serial##n) = { \ .platdata = &serial_device##n \ }; -#include <asm/arch/ehci-uniphier.h> - #endif /* ARCH_PLATDEVICE_H */ diff --git a/arch/arm/include/asm/arch-uniphier/sbc-regs.h b/arch/arm/mach-uniphier/include/mach/sbc-regs.h index efb68e8564..efb68e8564 100644 --- a/arch/arm/include/asm/arch-uniphier/sbc-regs.h +++ b/arch/arm/mach-uniphier/include/mach/sbc-regs.h diff --git a/arch/arm/include/asm/arch-uniphier/sc-regs.h b/arch/arm/mach-uniphier/include/mach/sc-regs.h index 1197bb52d4..20878e2d1c 100644 --- a/arch/arm/include/asm/arch-uniphier/sc-regs.h +++ b/arch/arm/mach-uniphier/include/mach/sc-regs.h @@ -1,7 +1,7 @@ /* * UniPhier SC (System Control) block registers * - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -11,10 +11,6 @@ #define SC_BASE_ADDR 0x61840000 -#define SC_MPLLOSCCTL (SC_BASE_ADDR | 0x1184) -#define SC_MPLLOSCCTL_MPLLEN (0x1 << 0) -#define SC_MPLLOSCCTL_MPLLST (0x1 << 1) - #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200) #define SC_DPLLCTRL_SSC_EN (0x1 << 31) #define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16) @@ -38,21 +34,32 @@ #define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298) #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) +#define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */ +#define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */ #define SC_RSTCTRL_NRST_ETHER (0x1 << 12) +#define SC_RSTCTRL_NRST_STDMAC (0x1 << 10) +#define SC_RSTCTRL_NRST_GIO (0x1 << 6) #define SC_RSTCTRL_NRST_UMC1 (0x1 << 5) #define SC_RSTCTRL_NRST_UMC0 (0x1 << 4) #define SC_RSTCTRL_NRST_NAND (0x1 << 2) #define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004) +#define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */ +#define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */ + #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) #define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) -#define SC_CLKCTRL_CLK_ETHER (0x1 << 12) -#define SC_CLKCTRL_CLK_MIO (0x1 << 11) -#define SC_CLKCTRL_CLK_UMC (0x1 << 4) -#define SC_CLKCTRL_CLK_NAND (0x1 << 2) -#define SC_CLKCTRL_CLK_SBC (0x1 << 1) -#define SC_CLKCTRL_CLK_PERI (0x1 << 0) +#define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */ +#define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */ +#define SC_CLKCTRL_CEN_ETHER (0x1 << 12) +#define SC_CLKCTRL_CEN_MIO (0x1 << 11) +#define SC_CLKCTRL_CEN_STDMAC (0x1 << 10) +#define SC_CLKCTRL_CEN_GIO (0x1 << 6) +#define SC_CLKCTRL_CEN_UMC (0x1 << 4) +#define SC_CLKCTRL_CEN_NAND (0x1 << 2) +#define SC_CLKCTRL_CEN_SBC (0x1 << 1) +#define SC_CLKCTRL_CEN_PERI (0x1 << 0) /* System reset control register */ #define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000) diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/mach-uniphier/include/mach/sg-regs.h index 4ae67c8adb..63408d5ba7 100644 --- a/arch/arm/include/asm/arch-uniphier/sg-regs.h +++ b/arch/arm/mach-uniphier/include/mach/sg-regs.h @@ -1,7 +1,7 @@ /* * UniPhier SG (SoC Glue) block registers * - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -108,7 +108,6 @@ #else #include <linux/types.h> -#include <linux/sizes.h> #include <asm/io.h> static inline void sg_set_pinsel(int n, int value) @@ -117,122 +116,6 @@ static inline void sg_set_pinsel(int n, int value) | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n)); } -static inline u32 sg_memconf_val_ch0(unsigned long size, int num) -{ - int size_mb = size / num; - u32 ret; - - switch (size_mb) { - case SZ_64M: - ret = SG_MEMCONF_CH0_SZ_64M; - break; - case SZ_128M: - ret = SG_MEMCONF_CH0_SZ_128M; - break; - case SZ_256M: - ret = SG_MEMCONF_CH0_SZ_256M; - break; - case SZ_512M: - ret = SG_MEMCONF_CH0_SZ_512M; - break; - case SZ_1G: - ret = SG_MEMCONF_CH0_SZ_1G; - break; - default: - BUG(); - break; - } - - switch (num) { - case 1: - ret |= SG_MEMCONF_CH0_NUM_1; - break; - case 2: - ret |= SG_MEMCONF_CH0_NUM_2; - break; - default: - BUG(); - break; - } - return ret; -} - -static inline u32 sg_memconf_val_ch1(unsigned long size, int num) -{ - int size_mb = size / num; - u32 ret; - - switch (size_mb) { - case SZ_64M: - ret = SG_MEMCONF_CH1_SZ_64M; - break; - case SZ_128M: - ret = SG_MEMCONF_CH1_SZ_128M; - break; - case SZ_256M: - ret = SG_MEMCONF_CH1_SZ_256M; - break; - case SZ_512M: - ret = SG_MEMCONF_CH1_SZ_512M; - break; - case SZ_1G: - ret = SG_MEMCONF_CH1_SZ_1G; - break; - default: - BUG(); - break; - } - - switch (num) { - case 1: - ret |= SG_MEMCONF_CH1_NUM_1; - break; - case 2: - ret |= SG_MEMCONF_CH1_NUM_2; - break; - default: - BUG(); - break; - } - return ret; -} - -static inline u32 sg_memconf_val_ch2(unsigned long size, int num) -{ - int size_mb = size / num; - u32 ret; - - switch (size_mb) { - case SZ_64M: - ret = SG_MEMCONF_CH2_SZ_64M; - break; - case SZ_128M: - ret = SG_MEMCONF_CH2_SZ_128M; - break; - case SZ_256M: - ret = SG_MEMCONF_CH2_SZ_256M; - break; - case SZ_512M: - ret = SG_MEMCONF_CH2_SZ_512M; - break; - default: - BUG(); - break; - } - - switch (num) { - case 1: - ret |= SG_MEMCONF_CH2_NUM_1; - break; - case 2: - ret |= SG_MEMCONF_CH2_NUM_2; - break; - default: - BUG(); - break; - } - return ret; -} #endif /* __ASSEMBLY__ */ #endif /* ARCH_SG_REGS_H */ diff --git a/arch/arm/include/asm/arch-uniphier/ssc-regs.h b/arch/arm/mach-uniphier/include/mach/ssc-regs.h index 77b3470c6d..02fca3b6f6 100644 --- a/arch/arm/include/asm/arch-uniphier/ssc-regs.h +++ b/arch/arm/mach-uniphier/include/mach/ssc-regs.h @@ -60,8 +60,6 @@ #define SSCOQCE0 0x506c0270 #define SSC_LINE_SIZE 128 -#define SSC_NUM_ENTRIES 256 -#define SSC_WAY_SIZE ((SSC_LINE_SIZE) * (SSC_NUM_ENTRIES)) #define SSC_RANGE_OP_MAX_SIZE (0x00400000 - (SSC_LINE_SIZE)) #endif /* ARCH_SSC_REGS_H */ diff --git a/arch/arm/include/asm/arch-uniphier/umc-regs.h b/arch/arm/mach-uniphier/include/mach/umc-regs.h index 6159281fd3..6159281fd3 100644 --- a/arch/arm/include/asm/arch-uniphier/umc-regs.h +++ b/arch/arm/mach-uniphier/include/mach/umc-regs.h diff --git a/arch/arm/cpu/armv7/uniphier/init_page_table.S b/arch/arm/mach-uniphier/init_page_table.S index 2638bcd779..2638bcd779 100644 --- a/arch/arm/cpu/armv7/uniphier/init_page_table.S +++ b/arch/arm/mach-uniphier/init_page_table.S diff --git a/arch/arm/cpu/armv7/uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S index c208ab67a1..92299fe64d 100644 --- a/arch/arm/cpu/armv7/uniphier/lowlevel_init.S +++ b/arch/arm/mach-uniphier/lowlevel_init.S @@ -7,10 +7,12 @@ #include <config.h> #include <linux/linkage.h> +#include <linux/sizes.h> #include <asm/system.h> -#include <asm/arch/led.h> -#include <asm/arch/arm-mpcore.h> -#include <asm/arch/sbc-regs.h> +#include <mach/led.h> +#include <mach/arm-mpcore.h> +#include <mach/sbc-regs.h> +#include <mach/ssc-regs.h> ENTRY(lowlevel_init) mov r8, lr @ persevere link reg across call @@ -122,9 +124,11 @@ ENTRY(enable_mmu) mov pc, lr ENDPROC(enable_mmu) -#include <asm/arch/ssc-regs.h> - -#define BOOT_RAM_SIZE (SSC_WAY_SIZE) +/* + * For PH1-Pro4 or older SoCs, the size of WAY is 32KB. + * It is large enough for tmp RAM. + */ +#define BOOT_RAM_SIZE (SZ_32K) #define BOOT_WAY_BITS (0x00000100) /* way 8 */ ENTRY(setup_init_ram) diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c new file mode 100644 index 0000000000..bf3c177ed9 --- /dev/null +++ b/arch/arm/mach-uniphier/memconf.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/sizes.h> +#include <asm/io.h> +#include <mach/sg-regs.h> + +static inline u32 sg_memconf_val_ch0(unsigned long size, int num) +{ + int size_mb = size / num; + u32 ret; + + switch (size_mb) { + case SZ_64M: + ret = SG_MEMCONF_CH0_SZ_64M; + break; + case SZ_128M: + ret = SG_MEMCONF_CH0_SZ_128M; + break; + case SZ_256M: + ret = SG_MEMCONF_CH0_SZ_256M; + break; + case SZ_512M: + ret = SG_MEMCONF_CH0_SZ_512M; + break; + case SZ_1G: + ret = SG_MEMCONF_CH0_SZ_1G; + break; + default: + BUG(); + break; + } + + switch (num) { + case 1: + ret |= SG_MEMCONF_CH0_NUM_1; + break; + case 2: + ret |= SG_MEMCONF_CH0_NUM_2; + break; + default: + BUG(); + break; + } + return ret; +} + +static inline u32 sg_memconf_val_ch1(unsigned long size, int num) +{ + int size_mb = size / num; + u32 ret; + + switch (size_mb) { + case SZ_64M: + ret = SG_MEMCONF_CH1_SZ_64M; + break; + case SZ_128M: + ret = SG_MEMCONF_CH1_SZ_128M; + break; + case SZ_256M: + ret = SG_MEMCONF_CH1_SZ_256M; + break; + case SZ_512M: + ret = SG_MEMCONF_CH1_SZ_512M; + break; + case SZ_1G: + ret = SG_MEMCONF_CH1_SZ_1G; + break; + default: + BUG(); + break; + } + + switch (num) { + case 1: + ret |= SG_MEMCONF_CH1_NUM_1; + break; + case 2: + ret |= SG_MEMCONF_CH1_NUM_2; + break; + default: + BUG(); + break; + } + return ret; +} + +void memconf_init(void) +{ + u32 tmp; + + /* Set DDR size */ + tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0); + tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1); +#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE + tmp |= SG_MEMCONF_SPARSEMEM; +#endif + writel(tmp, SG_MEMCONF); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/mach-uniphier/ph1-ld4/Makefile index 72f46636fd..5ce3d8a520 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile +++ b/arch/arm/mach-uniphier/ph1-ld4/Makefile @@ -4,10 +4,12 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o -obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \ +obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \ pll_spectrum.o umc_init.o ddrphy_init.o +obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o +obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o else -obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o +obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o endif diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c b/arch/arm/mach-uniphier/ph1-ld4/bcu_init.c index 85f37f299b..837e0d1fcc 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c +++ b/arch/arm/mach-uniphier/ph1-ld4/bcu_init.c @@ -7,7 +7,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/bcu-regs.h> +#include <mach/bcu-regs.h> #define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c b/arch/arm/mach-uniphier/ph1-ld4/boot-mode.c index d359b56291..d359b56291 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c +++ b/arch/arm/mach-uniphier/ph1-ld4/boot-mode.c diff --git a/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c b/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c new file mode 100644 index 0000000000..4ac5411562 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <mach/sc-regs.h> + +void clkrst_init(void) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_RSTCTRL_NRST_ETHER; +#endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_RSTCTRL_NRST_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_RSTCTRL_NRST_NAND; +#endif + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_CLKCTRL_CEN_ETHER; +#endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_CLKCTRL_CEN_NAND; +#endif + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c b/arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c index 60fc5ad6ea..a47e87a714 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c +++ b/arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c @@ -6,7 +6,7 @@ #include <linux/types.h> #include <asm/io.h> -#include <asm/arch/ddrphy-regs.h> +#include <mach/ddrphy-regs.h> void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) { diff --git a/arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c new file mode 100644 index 0000000000..d7ef16b10a --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c @@ -0,0 +1 @@ +#include "../ph1-pro4/early_clkrst_init.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S index c0778a0abb..7928c5c87c 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S +++ b/arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S @@ -8,10 +8,10 @@ */ #include <linux/linkage.h> -#include <asm/arch/sg-regs.h> +#include <mach/sg-regs.h> #define UART_CLK 36864000 -#include <asm/arch/debug-uart.S> +#include <mach/debug-uart.S> ENTRY(setup_lowlevel_debug) init_debug_uart r0, r1, r2 diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c index a7429402f3..15d81ebb3d 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c +++ b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c @@ -6,7 +6,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/sg-regs.h> +#include <mach/sg-regs.h> void pin_init(void) { diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c b/arch/arm/mach-uniphier/ph1-ld4/platdevice.c index 9d51299308..c0e62943be 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c +++ b/arch/arm/mach-uniphier/ph1-ld4/platdevice.c @@ -1,11 +1,11 @@ /* - * Copyright (C) 2014 Panasonic Corporation + * Copyright (C) 2014-2015 Panasonic Corporation * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> * * SPDX-License-Identifier: GPL-2.0+ */ -#include <asm/arch/platdevice.h> +#include <mach/platdevice.h> #define UART_MASTER_CLK 36864000 @@ -13,15 +13,3 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) - -struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { - { - .base = 0x5a800100, - }, - { - .base = 0x5a810100, - }, - { - .base = 0x5a820100, - }, -}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c b/arch/arm/mach-uniphier/ph1-ld4/pll_init.c index b83582fee7..985e14f4a9 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c +++ b/arch/arm/mach-uniphier/ph1-ld4/pll_init.c @@ -6,8 +6,8 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/sc-regs.h> -#include <asm/arch/sg-regs.h> +#include <mach/sc-regs.h> +#include <mach/sg-regs.h> #undef DPLL_SSC_RATE_1PER diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c index 837b2a891b..837b2a891b 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c +++ b/arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c diff --git a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c new file mode 100644 index 0000000000..00f84614f6 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sbc-regs.h> +#include <mach/sg-regs.h> + +void sbc_init(void) +{ + u32 tmp; + + /* system bus output enable */ + tmp = readl(PC0CTRL); + tmp &= 0xfffffcff; + writel(tmp, PC0CTRL); + + /* + * Only CS1 is connected to support card. + * BKSZ[1:0] should be set to "01". + */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); + + if (boot_is_swapped()) { + /* + * Boot Swap On: boot from external NOR/SRAM + * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. + * + * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank + * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals + */ + writel(0x0000bc01, SBBASE0); + } else { + /* + * Boot Swap Off: boot from mask ROM + * 0x00000000-0x01ffffff: mask ROM + * 0x02000000-0x03efffff: memory bank (31MB) + * 0x03f00000-0x03ffffff: peripherals (1MB) + */ + writel(0x0000be01, SBBASE0); /* dummy */ + writel(0x0200be01, SBBASE1); + } +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c b/arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c index 4839c943c7..374a8c0680 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c +++ b/arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -7,8 +7,8 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/sbc-regs.h> -#include <asm/arch/sg-regs.h> +#include <mach/sbc-regs.h> +#include <mach/sg-regs.h> void sbc_init(void) { @@ -25,13 +25,12 @@ void sbc_init(void) writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); -#if !defined(CONFIG_SPL_BUILD) /* XECS0: boot/sub memory (boot swap = off/on) */ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); -#endif + /* XECS3: peripherals */ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); @@ -43,9 +42,9 @@ void sbc_init(void) writel(0x0400bc01, SBBASE1); writel(0x0800bf01, SBBASE3); -#if !defined(CONFIG_SPL_BUILD) /* enable access to sub memory when boot swap is on */ - sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */ -#endif + if (boot_is_swapped()) + sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */ + sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */ } diff --git a/arch/arm/mach-uniphier/ph1-ld4/sg_init.c b/arch/arm/mach-uniphier/ph1-ld4/sg_init.c new file mode 100644 index 0000000000..93e44afd19 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/sg_init.c @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <mach/sg-regs.h> + +void sg_init(void) +{ + u32 tmp; + + /* Input ports must be enabled before deasserting reset of cores */ + tmp = readl(SG_IECTRL); + tmp |= 0x1; + writel(tmp, SG_IECTRL); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c b/arch/arm/mach-uniphier/ph1-ld4/umc_init.c index bbc3dcb3da..081b028c0c 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c +++ b/arch/arm/mach-uniphier/ph1-ld4/umc_init.c @@ -6,8 +6,8 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/umc-regs.h> -#include <asm/arch/ddrphy-regs.h> +#include <mach/umc-regs.h> +#include <mach/ddrphy-regs.h> static void umc_start_ssif(void __iomem *ssif_base) { diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/mach-uniphier/ph1-pro4/Makefile index 72f46636fd..b88525c82d 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile +++ b/arch/arm/mach-uniphier/ph1-pro4/Makefile @@ -4,10 +4,12 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o -obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \ +obj-y += sg_init.o pll_init.o early_clkrst_init.o \ pll_spectrum.o umc_init.o ddrphy_init.o +obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o +obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o else -obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o +obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o endif diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c b/arch/arm/mach-uniphier/ph1-pro4/boot-mode.c index c31b74badd..9894c1a9c0 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c +++ b/arch/arm/mach-uniphier/ph1-pro4/boot-mode.c @@ -8,9 +8,9 @@ #include <common.h> #include <spl.h> #include <asm/io.h> -#include <asm/arch/boot-device.h> -#include <asm/arch/sg-regs.h> -#include <asm/arch/sbc-regs.h> +#include <mach/boot-device.h> +#include <mach/sg-regs.h> +#include <mach/sbc-regs.h> struct boot_device_info boot_device_table[] = { {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"}, diff --git a/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c b/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c new file mode 100644 index 0000000000..054efa6537 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <mach/sc-regs.h> + +void clkrst_init(void) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 | + SC_RSTCTRL_NRST_GIO; +#endif +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_RSTCTRL_NRST_ETHER; +#endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_RSTCTRL_NRST_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_RSTCTRL_NRST_NAND; +#endif + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp = readl(SC_RSTCTRL2); + tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1; + writel(tmp, SC_RSTCTRL2); + readl(SC_RSTCTRL2); /* dummy read */ +#endif + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | + SC_CLKCTRL_CEN_GIO; +#endif +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_CLKCTRL_CEN_ETHER; +#endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_CLKCTRL_CEN_NAND; +#endif + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c b/arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c index c5d1f606cf..7df5aea0f3 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c +++ b/arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c @@ -6,7 +6,7 @@ #include <linux/types.h> #include <asm/io.h> -#include <asm/arch/ddrphy-regs.h> +#include <mach/ddrphy-regs.h> void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) { diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c b/arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c index 18965a94c5..37bb79e25a 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c +++ b/arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c @@ -1,29 +1,31 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <spl.h> #include <asm/io.h> -#include <asm/arch/sc-regs.h> +#include <mach/sc-regs.h> -void clkrst_init(void) +void early_clkrst_init(void) { u32 tmp; /* deassert reset */ tmp = readl(SC_RSTCTRL); - tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1 - | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND; + + tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0; + if (spl_boot_device() != BOOT_DEVICE_NAND) + tmp &= ~SC_RSTCTRL_NRST_NAND; writel(tmp, SC_RSTCTRL); readl(SC_RSTCTRL); /* dummy read */ /* privide clocks */ tmp = readl(SC_CLKCTRL); - tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC - | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI; + tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI; writel(tmp, SC_CLKCTRL); readl(SC_CLKCTRL); /* dummy read */ } diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S index a793b7c118..fcaf6d12d8 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S +++ b/arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S @@ -8,16 +8,16 @@ */ #include <linux/linkage.h> -#include <asm/arch/sc-regs.h> -#include <asm/arch/sg-regs.h> +#include <mach/sc-regs.h> +#include <mach/sg-regs.h> #define UART_CLK 73728000 -#include <asm/arch/debug-uart.S> +#include <mach/debug-uart.S> ENTRY(setup_lowlevel_debug) ldr r0, =SC_CLKCTRL ldr r1, [r0] - orr r1, r1, #SC_CLKCTRL_CLK_PERI + orr r1, r1, #SC_CLKCTRL_CEN_PERI str r1, [r0] init_debug_uart r0, r1, r2 diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c b/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c index 4e3d47615b..f382ef4842 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c +++ b/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c @@ -6,7 +6,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/sg-regs.h> +#include <mach/sg-regs.h> void pin_init(void) { @@ -41,6 +41,13 @@ void pin_init(void) sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */ #endif +#ifdef CONFIG_USB_XHCI_UNIPHIER + sg_set_pinsel(180, 0); /* USB0VBUS -> USB0VBUS */ + sg_set_pinsel(181, 0); /* USB0OD -> USB0OD */ + sg_set_pinsel(182, 0); /* USB1VBUS -> USB1VBUS */ + sg_set_pinsel(183, 0); /* USB1OD -> USB1OD */ +#endif + #ifdef CONFIG_USB_EHCI_UNIPHIER sg_set_pinsel(184, 0); /* USB2VBUS -> USB2VBUS */ sg_set_pinsel(185, 0); /* USB2OD -> USB2OD */ diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c b/arch/arm/mach-uniphier/ph1-pro4/platdevice.c index 31ee2a2100..7440ceddff 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c +++ b/arch/arm/mach-uniphier/ph1-pro4/platdevice.c @@ -1,11 +1,11 @@ /* - * Copyright (C) 2014 Panasonic Corporation + * Copyright (C) 2014-2015 Panasonic Corporation * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> * * SPDX-License-Identifier: GPL-2.0+ */ -#include <asm/arch/platdevice.h> +#include <mach/platdevice.h> #define UART_MASTER_CLK 73728000 @@ -13,12 +13,3 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) - -struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { - { - .base = 0x5a800100, - }, - { - .base = 0x5a810100, - }, -}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c b/arch/arm/mach-uniphier/ph1-pro4/pll_init.c index 1db90f88a0..2a965a5e67 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c +++ b/arch/arm/mach-uniphier/ph1-pro4/pll_init.c @@ -6,8 +6,8 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/sc-regs.h> -#include <asm/arch/sg-regs.h> +#include <mach/sc-regs.h> +#include <mach/sg-regs.h> #undef DPLL_SSC_RATE_1PER @@ -46,22 +46,6 @@ static void dpll_init(void) writel(tmp, SC_DPLLCTRL2); } -static void stop_mpll(void) -{ - u32 tmp; - - tmp = readl(SC_MPLLOSCCTL); - - if (!(tmp & SC_MPLLOSCCTL_MPLLST)) - return; /* already stopped */ - - tmp &= ~SC_MPLLOSCCTL_MPLLEN; - writel(tmp, SC_MPLLOSCCTL); - - while (readl(SC_MPLLOSCCTL) & SC_MPLLOSCCTL_MPLLST) - ; -} - static void vpll_init(void) { u32 tmp, clk_mode_axosel; @@ -157,7 +141,6 @@ static void vpll_init(void) void pll_init(void) { dpll_init(); - stop_mpll(); vpll_init(); /* diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c index 4538d1af44..ff9c73ff21 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c +++ b/arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c @@ -6,7 +6,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/sc-regs.h> +#include <mach/sc-regs.h> void enable_dpll_ssc(void) { diff --git a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c b/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c new file mode 100644 index 0000000000..5e75454dcb --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sbc-regs.h> +#include <mach/sg-regs.h> + +void sbc_init(void) +{ + /* + * Only CS1 is connected to support card. + * BKSZ[1:0] should be set to "01". + */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); + + if (boot_is_swapped()) { + /* + * Boot Swap On: boot from external NOR/SRAM + * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. + * + * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank + * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals + */ + writel(0x0000bc01, SBBASE0); + } else { + /* + * Boot Swap Off: boot from mask ROM + * 0x00000000-0x01ffffff: mask ROM + * 0x02000000-0x03efffff: memory bank (31MB) + * 0x03f00000-0x03ffffff: peripherals (1MB) + */ + writel(0x0000be01, SBBASE0); /* dummy */ + writel(0x0200be01, SBBASE1); + } +} diff --git a/arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c b/arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c new file mode 100644 index 0000000000..67e6d8245b --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sbc-regs.h> +#include <mach/sg-regs.h> + +void sbc_init(void) +{ + /* XECS0: boot/sub memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); + + /* XECS1: sub/boot memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); + + /* XECS3: peripherals */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); + + writel(0x0000bc01, SBBASE0); /* boot memory */ + writel(0x0400bc01, SBBASE1); /* sub memory */ + writel(0x0800bf01, SBBASE3); /* peripherals */ + + /* enable access to sub memory when boot swap is on */ + if (boot_is_swapped()) + sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */ + + sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */ + writel(0x00000001, SG_LOADPINCTRL); +} diff --git a/arch/arm/mach-uniphier/ph1-pro4/sg_init.c b/arch/arm/mach-uniphier/ph1-pro4/sg_init.c new file mode 100644 index 0000000000..8677666323 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/sg_init.c @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <mach/sg-regs.h> + +void sg_init(void) +{ + u32 tmp; + + /* Input ports must be enabled before deasserting reset of cores */ + tmp = readl(SG_IECTRL); + tmp |= 1 << 6; + writel(tmp, SG_IECTRL); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c b/arch/arm/mach-uniphier/ph1-pro4/umc_init.c index 2d1bde6f13..6cbb6b2473 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c +++ b/arch/arm/mach-uniphier/ph1-pro4/umc_init.c @@ -6,8 +6,8 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/umc-regs.h> -#include <asm/arch/ddrphy-regs.h> +#include <mach/umc-regs.h> +#include <mach/ddrphy-regs.h> static void umc_start_ssif(void __iomem *ssif_base) { diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/mach-uniphier/ph1-sld8/Makefile index e330fda1ed..5ce3d8a520 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile +++ b/arch/arm/mach-uniphier/ph1-sld8/Makefile @@ -4,10 +4,12 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o -obj-y += sbc_init.o sg_init.o pll_init.o clkrst_init.o \ +obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \ pll_spectrum.o umc_init.o ddrphy_init.o +obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o +obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o else -obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o +obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o endif diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c b/arch/arm/mach-uniphier/ph1-sld8/bcu_init.c index 69b172e4e7..69b172e4e7 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c +++ b/arch/arm/mach-uniphier/ph1-sld8/bcu_init.c diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c b/arch/arm/mach-uniphier/ph1-sld8/boot-mode.c index d359b56291..d359b56291 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c +++ b/arch/arm/mach-uniphier/ph1-sld8/boot-mode.c diff --git a/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c new file mode 100644 index 0000000000..8d3435d632 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c @@ -0,0 +1 @@ +#include "../ph1-ld4/clkrst_init.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c b/arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c index a5eafef9a8..304edfb482 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c +++ b/arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c @@ -7,7 +7,7 @@ #include <config.h> #include <linux/types.h> #include <asm/io.h> -#include <asm/arch/ddrphy-regs.h> +#include <mach/ddrphy-regs.h> void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) { diff --git a/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c new file mode 100644 index 0000000000..dd236b7e50 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c @@ -0,0 +1 @@ +#include "../ph1-ld4/early_clkrst_init.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S index a413e5fd8a..73f0f63eba 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S +++ b/arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S @@ -8,10 +8,10 @@ */ #include <linux/linkage.h> -#include <asm/arch/sg-regs.h> +#include <mach/sg-regs.h> #define UART_CLK 80000000 -#include <asm/arch/debug-uart.S> +#include <mach/debug-uart.S> ENTRY(setup_lowlevel_debug) init_debug_uart r0, r1, r2 diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c index 5e80335b58..4c494ffa40 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c +++ b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c @@ -6,7 +6,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/sg-regs.h> +#include <mach/sg-regs.h> void pin_init(void) { diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c b/arch/arm/mach-uniphier/ph1-sld8/platdevice.c index ea0691dd67..aa334a1ca4 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c +++ b/arch/arm/mach-uniphier/ph1-sld8/platdevice.c @@ -1,11 +1,11 @@ /* - * Copyright (C) 2014 Panasonic Corporation + * Copyright (C) 2014-2015 Panasonic Corporation * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> * * SPDX-License-Identifier: GPL-2.0+ */ -#include <asm/arch/platdevice.h> +#include <mach/platdevice.h> #define UART_MASTER_CLK 80000000 @@ -13,15 +13,3 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) - -struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { - { - .base = 0x5a800100, - }, - { - .base = 0x5a810100, - }, - { - .base = 0x5a820100, - }, -}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c b/arch/arm/mach-uniphier/ph1-sld8/pll_init.c index 4b82700f44..885100747d 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c +++ b/arch/arm/mach-uniphier/ph1-sld8/pll_init.c @@ -6,8 +6,8 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/sc-regs.h> -#include <asm/arch/sg-regs.h> +#include <mach/sc-regs.h> +#include <mach/sg-regs.h> static void dpll_init(void) { diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c index 9b8c4855e5..9b8c4855e5 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c +++ b/arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c diff --git a/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c b/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c new file mode 100644 index 0000000000..225c0d24de --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c @@ -0,0 +1 @@ +#include "../ph1-ld4/sbc_init.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c b/arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c index 5efee9c505..fdef88e126 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c +++ b/arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -7,8 +7,8 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/sbc-regs.h> -#include <asm/arch/sg-regs.h> +#include <mach/sbc-regs.h> +#include <mach/sg-regs.h> void sbc_init(void) { @@ -19,18 +19,18 @@ void sbc_init(void) tmp &= 0xfffffcff; writel(tmp, PC0CTRL); -#if !defined(CONFIG_SPL_BUILD) - /* XECS0 : dummy */ - writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); - writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); - writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); - writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); -#endif - /* XECS1 : boot memory (always boot swap = on) */ - writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); - writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); - writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); - writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); + /* + * SBCTRL0* does not need settings because PH1-sLD8 has no support for + * XECS0. The boot swap must be enabled to boot from the support card. + */ + + if (boot_is_swapped()) { + /* XECS1 : boot memory if boot swap is on */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); + } /* XECS4 : sub memory */ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40); @@ -54,5 +54,5 @@ void sbc_init(void) sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */ /* dummy read to assure write process */ - readl(SG_PINCTRL(33)); + readl(SG_PINCTRL(0)); } diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c b/arch/arm/mach-uniphier/ph1-sld8/sg_init.c index a808289a56..a808289a56 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c +++ b/arch/arm/mach-uniphier/ph1-sld8/sg_init.c diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c b/arch/arm/mach-uniphier/ph1-sld8/umc_init.c index 2fbc73ab03..302611e5d2 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c +++ b/arch/arm/mach-uniphier/ph1-sld8/umc_init.c @@ -6,8 +6,8 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/umc-regs.h> -#include <asm/arch/ddrphy-regs.h> +#include <mach/umc-regs.h> +#include <mach/ddrphy-regs.h> static void umc_start_ssif(void __iomem *ssif_base) { diff --git a/arch/arm/cpu/armv7/uniphier/print_misc_info.c b/arch/arm/mach-uniphier/print_misc_info.c index 69cfab519f..22ea512285 100644 --- a/arch/arm/cpu/armv7/uniphier/print_misc_info.c +++ b/arch/arm/mach-uniphier/print_misc_info.c @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <asm/arch/board.h> +#include <mach/board.h> int misc_init_f(void) { diff --git a/arch/arm/cpu/armv7/uniphier/reset.c b/arch/arm/mach-uniphier/reset.c index 50d1fed647..005fbcf0b8 100644 --- a/arch/arm/cpu/armv7/uniphier/reset.c +++ b/arch/arm/mach-uniphier/reset.c @@ -7,7 +7,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/sc-regs.h> +#include <mach/sc-regs.h> void reset_cpu(unsigned long ignored) { diff --git a/arch/arm/cpu/armv7/uniphier/smp.S b/arch/arm/mach-uniphier/smp.S index 25ba981cea..18e3a9d21e 100644 --- a/arch/arm/cpu/armv7/uniphier/smp.S +++ b/arch/arm/mach-uniphier/smp.S @@ -8,8 +8,8 @@ #include <config.h> #include <linux/linkage.h> #include <asm/system.h> -#include <asm/arch/led.h> -#include <asm/arch/sbc-regs.h> +#include <mach/led.h> +#include <mach/sbc-regs.h> /* Entry point of U-Boot main program for the secondary CPU */ LENTRY(secondary_entry) diff --git a/arch/arm/cpu/armv7/uniphier/spl.c b/arch/arm/mach-uniphier/spl.c index 8a4eafc266..c3d90d03d0 100644 --- a/arch/arm/cpu/armv7/uniphier/spl.c +++ b/arch/arm/mach-uniphier/spl.c @@ -8,8 +8,8 @@ #include <common.h> #include <spl.h> #include <linux/compiler.h> -#include <asm/arch/led.h> -#include <asm/arch/board.h> +#include <mach/led.h> +#include <mach/board.h> void __weak bcu_init(void) { @@ -18,7 +18,8 @@ void sbc_init(void); void sg_init(void); void pll_init(void); void pin_init(void); -void clkrst_init(void); +void memconf_init(void); +void early_clkrst_init(void); int umc_init(void); void enable_dpll_ssc(void); @@ -38,10 +39,14 @@ void spl_board_init(void) led_write(L, 0, , ); - clkrst_init(); + memconf_init(); led_write(L, 1, , ); + early_clkrst_init(); + + led_write(L, 2, , ); + { int res; @@ -51,9 +56,9 @@ void spl_board_init(void) ; } } - led_write(L, 2, , ); + led_write(L, 3, , ); enable_dpll_ssc(); - led_write(L, 3, , ); + led_write(L, 4, , ); } diff --git a/arch/arm/cpu/armv7/uniphier/support_card.c b/arch/arm/mach-uniphier/support_card.c index 443224c451..e7b4158636 100644 --- a/arch/arm/cpu/armv7/uniphier/support_card.c +++ b/arch/arm/mach-uniphier/support_card.c @@ -7,7 +7,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/board.h> +#include <mach/board.h> #if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) @@ -112,7 +112,7 @@ int board_eth_init(bd_t *bis) #if !defined(CONFIG_SYS_NO_FLASH) #include <mtd/cfi_flash.h> -#include <asm/arch/sbc-regs.h> +#include <mach/sbc-regs.h> struct memory_bank { phys_addr_t base; diff --git a/arch/arm/cpu/armv7/uniphier/timer.c b/arch/arm/mach-uniphier/timer.c index 6edc0842a9..adef08d2de 100644 --- a/arch/arm/cpu/armv7/uniphier/timer.c +++ b/arch/arm/mach-uniphier/timer.c @@ -7,7 +7,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/arm-mpcore.h> +#include <mach/arm-mpcore.h> #define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */ #define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1) diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index ff8f5b5ce8..2128f23264 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -124,6 +124,9 @@ config SYS_CPU default "sh3" if CPU_SH3 default "sh4" if CPU_SH4 +config USE_PRIVATE_LIBGCC + default y + source "board/alphaproject/ap_sh4a_4a/Kconfig" source "board/espt/Kconfig" source "board/mpr2/Kconfig" diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile index 1304f4ee93..f7ae4f86ef 100644 --- a/arch/sh/lib/Makefile +++ b/arch/sh/lib/Makefile @@ -15,5 +15,14 @@ obj-y += time.o endif obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o -lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashiftrt.o ashiftlt.o lshiftrt.o \ - ashldi3.o ashrsi3.o lshrdi3.o movmem.o +udivsi3-y := udivsi3_i4i-Os.o + +ifneq ($(CONFIG_CC_OPTIMIZE_FOR_SIZE),y) +udivsi3-$(CONFIG_CPU_SH3) := udivsi3_i4i.o +udivsi3-$(CONFIG_CPU_SH4) := udivsi3_i4i.o +endif +udivsi3-y += udivsi3.o + +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += movmem.o ashldi3.o ashrdi3.o lshrdi3.o \ + ashlsi3.o ashrsi3.o ashiftrt.o lshrsi3.o \ + udiv_qrnnd.o $(udivsi3-y) diff --git a/arch/sh/lib/ashiftlt.S b/arch/sh/lib/ashlsi3.S index f971568e35..f971568e35 100644 --- a/arch/sh/lib/ashiftlt.S +++ b/arch/sh/lib/ashlsi3.S diff --git a/arch/sh/lib/ashrdi3.c b/arch/sh/lib/ashrdi3.c new file mode 100644 index 0000000000..f30359b73f --- /dev/null +++ b/arch/sh/lib/ashrdi3.c @@ -0,0 +1,27 @@ +#include "libgcc.h" + +long long __ashrdi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + /* w.s.high = 1..1 or 0..0 */ + w.s.high = + uu.s.high >> 31; + w.s.low = uu.s.high >> -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.high << bm; + + w.s.high = uu.s.high >> b; + w.s.low = ((unsigned int) uu.s.low >> b) | carries; + } + + return w.ll; +} diff --git a/arch/sh/lib/lshiftrt.S b/arch/sh/lib/lshrsi3.S index 787044d2e6..787044d2e6 100644 --- a/arch/sh/lib/lshiftrt.S +++ b/arch/sh/lib/lshrsi3.S diff --git a/arch/sh/lib/udiv_qrnnd.S b/arch/sh/lib/udiv_qrnnd.S new file mode 100644 index 0000000000..4557a15665 --- /dev/null +++ b/arch/sh/lib/udiv_qrnnd.S @@ -0,0 +1,60 @@ +/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003, + 2004, 2005, 2006 + Free Software Foundation, Inc. + + * SPDX-License-Identifier: GPL-2.0+ + */ + +!! libgcc routines for the Renesas / SuperH SH CPUs. +!! Contributed by Steve Chamberlain. +!! sac@cygnus.com + +!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines +!! recoded in assembly by Toshiyasu Morita +!! tm@netcom.com + +/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and + ELF local label prefixes by J"orn Rennecke + amylaar@cygnus.com */ + + /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ + /* n1 < d, but n1 might be larger than d1. */ + .global __udiv_qrnnd_16 + .balign 8 +__udiv_qrnnd_16: + div0u + cmp/hi r6,r0 + bt .Lots + .rept 16 + div1 r6,r0 + .endr + extu.w r0,r1 + bt 0f + add r6,r0 +0: rotcl r1 + mulu.w r1,r5 + xtrct r4,r0 + swap.w r0,r0 + sts macl,r2 + cmp/hs r2,r0 + sub r2,r0 + bt 0f + addc r5,r0 + add #-1,r1 + bt 0f +1: add #-1,r1 + rts + add r5,r0 + .balign 8 +.Lots: + sub r5,r0 + swap.w r4,r1 + xtrct r0,r1 + clrt + mov r1,r0 + addc r5,r0 + mov #-1,r1 + bf/s 1b + shlr16 r1 +0: rts + nop diff --git a/arch/sh/lib/udivsi3.S b/arch/sh/lib/udivsi3.S new file mode 100644 index 0000000000..53409f1dc0 --- /dev/null +++ b/arch/sh/lib/udivsi3.S @@ -0,0 +1,66 @@ +/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003, + 2004, 2005 + Free Software Foundation, Inc. + + * SPDX-License-Identifier: GPL-2.0+ + */ + +!! libgcc routines for the Renesas / SuperH SH CPUs. +!! Contributed by Steve Chamberlain. +!! sac@cygnus.com + + .balign 4 + .global __udivsi3 + .type __udivsi3, @function +div8: + div1 r5,r4 +div7: + div1 r5,r4; div1 r5,r4; div1 r5,r4 + div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4 + +divx4: + div1 r5,r4; rotcl r0 + div1 r5,r4; rotcl r0 + div1 r5,r4; rotcl r0 + rts; div1 r5,r4 + +__udivsi3: + sts.l pr,@-r15 + extu.w r5,r0 + cmp/eq r5,r0 + bf/s large_divisor + div0u + swap.w r4,r0 + shlr16 r4 + bsr div8 + shll16 r5 + bsr div7 + div1 r5,r4 + xtrct r4,r0 + xtrct r0,r4 + bsr div8 + swap.w r4,r4 + bsr div7 + div1 r5,r4 + lds.l @r15+,pr + xtrct r4,r0 + swap.w r0,r0 + rotcl r0 + rts + shlr16 r5 + +large_divisor: + mov #0,r0 + xtrct r4,r0 + xtrct r0,r4 + bsr divx4 + rotcl r0 + bsr divx4 + rotcl r0 + bsr divx4 + rotcl r0 + bsr divx4 + rotcl r0 + lds.l @r15+,pr + rts + rotcl r0 diff --git a/arch/sh/lib/udivsi3_i4i-Os.S b/arch/sh/lib/udivsi3_i4i-Os.S new file mode 100644 index 0000000000..54988ee8d0 --- /dev/null +++ b/arch/sh/lib/udivsi3_i4i-Os.S @@ -0,0 +1,128 @@ +/* Copyright (C) 2006 Free Software Foundation, Inc. + + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Moderately Space-optimized libgcc routines for the Renesas SH / + STMicroelectronics ST40 CPUs. + Contributed by J"orn Rennecke joern.rennecke@st.com. */ + +/* Size: 186 bytes jointly for udivsi3_i4i and sdivsi3_i4i + sh4-200 run times: + udiv small divisor: 55 cycles + udiv large divisor: 52 cycles + sdiv small divisor, positive result: 59 cycles + sdiv large divisor, positive result: 56 cycles + sdiv small divisor, negative result: 65 cycles (*) + sdiv large divisor, negative result: 62 cycles (*) + (*): r2 is restored in the rts delay slot and has a lingering latency + of two more cycles. */ + .balign 4 + .global __udivsi3_i4i + .global __udivsi3_i4 + .set __udivsi3_i4, __udivsi3_i4i + .type __udivsi3_i4i, @function + .type __sdivsi3_i4i, @function +__udivsi3_i4i: + sts pr,r1 + mov.l r4,@-r15 + extu.w r5,r0 + cmp/eq r5,r0 + swap.w r4,r0 + shlr16 r4 + bf/s large_divisor + div0u + mov.l r5,@-r15 + shll16 r5 +sdiv_small_divisor: + div1 r5,r4 + bsr div6 + div1 r5,r4 + div1 r5,r4 + bsr div6 + div1 r5,r4 + xtrct r4,r0 + xtrct r0,r4 + bsr div7 + swap.w r4,r4 + div1 r5,r4 + bsr div7 + div1 r5,r4 + xtrct r4,r0 + mov.l @r15+,r5 + swap.w r0,r0 + mov.l @r15+,r4 + jmp @r1 + rotcl r0 +div7: + div1 r5,r4 +div6: + div1 r5,r4; div1 r5,r4; div1 r5,r4 + div1 r5,r4; div1 r5,r4; rts; div1 r5,r4 + +divx3: + rotcl r0 + div1 r5,r4 + rotcl r0 + div1 r5,r4 + rotcl r0 + rts + div1 r5,r4 + +large_divisor: + mov.l r5,@-r15 +sdiv_large_divisor: + xor r4,r0 + .rept 4 + rotcl r0 + bsr divx3 + div1 r5,r4 + .endr + mov.l @r15+,r5 + mov.l @r15+,r4 + jmp @r1 + rotcl r0 + + .global __sdivsi3_i4i + .global __sdivsi3_i4 + .global __sdivsi3 + .set __sdivsi3_i4, __sdivsi3_i4i + .set __sdivsi3, __sdivsi3_i4i +__sdivsi3_i4i: + mov.l r4,@-r15 + cmp/pz r5 + mov.l r5,@-r15 + bt/s pos_divisor + cmp/pz r4 + neg r5,r5 + extu.w r5,r0 + bt/s neg_result + cmp/eq r5,r0 + neg r4,r4 +pos_result: + swap.w r4,r0 + bra sdiv_check_divisor + sts pr,r1 +pos_divisor: + extu.w r5,r0 + bt/s pos_result + cmp/eq r5,r0 + neg r4,r4 +neg_result: + mova negate_result,r0 + ; + mov r0,r1 + swap.w r4,r0 + lds r2,macl + sts pr,r2 +sdiv_check_divisor: + shlr16 r4 + bf/s sdiv_large_divisor + div0u + bra sdiv_small_divisor + shll16 r5 + .balign 4 +negate_result: + neg r0,r0 + jmp @r2 + sts macl,r2 diff --git a/arch/sh/lib/udivsi3_i4i.S b/arch/sh/lib/udivsi3_i4i.S new file mode 100644 index 0000000000..a9a283c8d9 --- /dev/null +++ b/arch/sh/lib/udivsi3_i4i.S @@ -0,0 +1,644 @@ +/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003, + 2004, 2005, 2006 + Free Software Foundation, Inc. + + * SPDX-License-Identifier: GPL-2.0+ + */ + +!! libgcc routines for the Renesas / SuperH SH CPUs. +!! Contributed by Steve Chamberlain. +!! sac@cygnus.com + +!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines +!! recoded in assembly by Toshiyasu Morita +!! tm@netcom.com + +/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and + ELF local label prefixes by J"orn Rennecke + amylaar@cygnus.com */ + +/* This code used shld, thus is not suitable for SH1 / SH2. */ + +/* Signed / unsigned division without use of FPU, optimized for SH4. + Uses a lookup table for divisors in the range -128 .. +128, and + div1 with case distinction for larger divisors in three more ranges. + The code is lumped together with the table to allow the use of mova. */ +#ifdef CONFIG_CPU_LITTLE_ENDIAN +#define L_LSB 0 +#define L_LSWMSB 1 +#define L_MSWLSB 2 +#else +#define L_LSB 3 +#define L_LSWMSB 2 +#define L_MSWLSB 1 +#endif + + .balign 4 + .global __udivsi3_i4i + .global __udivsi3_i4 + .set __udivsi3_i4, __udivsi3_i4i + .type __udivsi3_i4i, @function +__udivsi3_i4i: + mov.w c128_w, r1 + div0u + mov r4,r0 + shlr8 r0 + cmp/hi r1,r5 + extu.w r5,r1 + bf udiv_le128 + cmp/eq r5,r1 + bf udiv_ge64k + shlr r0 + mov r5,r1 + shll16 r5 + mov.l r4,@-r15 + div1 r5,r0 + mov.l r1,@-r15 + div1 r5,r0 + div1 r5,r0 + bra udiv_25 + div1 r5,r0 + +div_le128: + mova div_table_ix,r0 + bra div_le128_2 + mov.b @(r0,r5),r1 +udiv_le128: + mov.l r4,@-r15 + mova div_table_ix,r0 + mov.b @(r0,r5),r1 + mov.l r5,@-r15 +div_le128_2: + mova div_table_inv,r0 + mov.l @(r0,r1),r1 + mov r5,r0 + tst #0xfe,r0 + mova div_table_clz,r0 + dmulu.l r1,r4 + mov.b @(r0,r5),r1 + bt/s div_by_1 + mov r4,r0 + mov.l @r15+,r5 + sts mach,r0 + /* clrt */ + addc r4,r0 + mov.l @r15+,r4 + rotcr r0 + rts + shld r1,r0 + +div_by_1_neg: + neg r4,r0 +div_by_1: + mov.l @r15+,r5 + rts + mov.l @r15+,r4 + +div_ge64k: + bt/s div_r8 + div0u + shll8 r5 + bra div_ge64k_2 + div1 r5,r0 +udiv_ge64k: + cmp/hi r0,r5 + mov r5,r1 + bt udiv_r8 + shll8 r5 + mov.l r4,@-r15 + div1 r5,r0 + mov.l r1,@-r15 +div_ge64k_2: + div1 r5,r0 + mov.l zero_l,r1 + .rept 4 + div1 r5,r0 + .endr + mov.l r1,@-r15 + div1 r5,r0 + mov.w m256_w,r1 + div1 r5,r0 + mov.b r0,@(L_LSWMSB,r15) + xor r4,r0 + and r1,r0 + bra div_ge64k_end + xor r4,r0 +div_r8: + shll16 r4 + bra div_r8_2 + shll8 r4 +udiv_r8: + mov.l r4,@-r15 + shll16 r4 + clrt + shll8 r4 + mov.l r5,@-r15 +div_r8_2: + rotcl r4 + mov r0,r1 + div1 r5,r1 + mov r4,r0 + rotcl r0 + mov r5,r4 + div1 r5,r1 + .rept 5 + rotcl r0; div1 r5,r1 + .endr + rotcl r0 + mov.l @r15+,r5 + div1 r4,r1 + mov.l @r15+,r4 + rts + rotcl r0 + + .global __sdivsi3_i4i + .global __sdivsi3_i4 + .global __sdivsi3 + .set __sdivsi3_i4, __sdivsi3_i4i + .set __sdivsi3, __sdivsi3_i4i + .type __sdivsi3_i4i, @function + /* This is link-compatible with a __sdivsi3 call, + but we effectively clobber only r1. */ +__sdivsi3_i4i: + mov.l r4,@-r15 + cmp/pz r5 + mov.w c128_w, r1 + bt/s pos_divisor + cmp/pz r4 + mov.l r5,@-r15 + neg r5,r5 + bt/s neg_result + cmp/hi r1,r5 + neg r4,r4 +pos_result: + extu.w r5,r0 + bf div_le128 + cmp/eq r5,r0 + mov r4,r0 + shlr8 r0 + bf/s div_ge64k + cmp/hi r0,r5 + div0u + shll16 r5 + div1 r5,r0 + div1 r5,r0 + div1 r5,r0 +udiv_25: + mov.l zero_l,r1 + div1 r5,r0 + div1 r5,r0 + mov.l r1,@-r15 + .rept 3 + div1 r5,r0 + .endr + mov.b r0,@(L_MSWLSB,r15) + xtrct r4,r0 + swap.w r0,r0 + .rept 8 + div1 r5,r0 + .endr + mov.b r0,@(L_LSWMSB,r15) +div_ge64k_end: + .rept 8 + div1 r5,r0 + .endr + mov.l @r15+,r4 ! zero-extension and swap using LS unit. + extu.b r0,r0 + mov.l @r15+,r5 + or r4,r0 + mov.l @r15+,r4 + rts + rotcl r0 + +div_le128_neg: + tst #0xfe,r0 + mova div_table_ix,r0 + mov.b @(r0,r5),r1 + mova div_table_inv,r0 + bt/s div_by_1_neg + mov.l @(r0,r1),r1 + mova div_table_clz,r0 + dmulu.l r1,r4 + mov.b @(r0,r5),r1 + mov.l @r15+,r5 + sts mach,r0 + /* clrt */ + addc r4,r0 + mov.l @r15+,r4 + rotcr r0 + shld r1,r0 + rts + neg r0,r0 + +pos_divisor: + mov.l r5,@-r15 + bt/s pos_result + cmp/hi r1,r5 + neg r4,r4 +neg_result: + extu.w r5,r0 + bf div_le128_neg + cmp/eq r5,r0 + mov r4,r0 + shlr8 r0 + bf/s div_ge64k_neg + cmp/hi r0,r5 + div0u + mov.l zero_l,r1 + shll16 r5 + div1 r5,r0 + mov.l r1,@-r15 + .rept 7 + div1 r5,r0 + .endr + mov.b r0,@(L_MSWLSB,r15) + xtrct r4,r0 + swap.w r0,r0 + .rept 8 + div1 r5,r0 + .endr + mov.b r0,@(L_LSWMSB,r15) +div_ge64k_neg_end: + .rept 8 + div1 r5,r0 + .endr + mov.l @r15+,r4 ! zero-extension and swap using LS unit. + extu.b r0,r1 + mov.l @r15+,r5 + or r4,r1 +div_r8_neg_end: + mov.l @r15+,r4 + rotcl r1 + rts + neg r1,r0 + +div_ge64k_neg: + bt/s div_r8_neg + div0u + shll8 r5 + mov.l zero_l,r1 + .rept 6 + div1 r5,r0 + .endr + mov.l r1,@-r15 + div1 r5,r0 + mov.w m256_w,r1 + div1 r5,r0 + mov.b r0,@(L_LSWMSB,r15) + xor r4,r0 + and r1,r0 + bra div_ge64k_neg_end + xor r4,r0 + +c128_w: + .word 128 + +div_r8_neg: + clrt + shll16 r4 + mov r4,r1 + shll8 r1 + mov r5,r4 + .rept 7 + rotcl r1; div1 r5,r0 + .endr + mov.l @r15+,r5 + rotcl r1 + bra div_r8_neg_end + div1 r4,r0 + +m256_w: + .word 0xff00 +/* This table has been generated by divtab-sh4.c. */ + .balign 4 +div_table_clz: + .byte 0 + .byte 1 + .byte 0 + .byte -1 + .byte -1 + .byte -2 + .byte -2 + .byte -2 + .byte -2 + .byte -3 + .byte -3 + .byte -3 + .byte -3 + .byte -3 + .byte -3 + .byte -3 + .byte -3 + .byte -4 + .byte -4 + .byte -4 + .byte -4 + .byte -4 + .byte -4 + .byte -4 + .byte -4 + .byte -4 + .byte -4 + .byte -4 + .byte -4 + .byte -4 + .byte -4 + .byte -4 + .byte -4 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -5 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 + .byte -6 +/* Lookup table translating positive divisor to index into table of + normalized inverse. N.B. the '0' entry is also the last entry of the + previous table, and causes an unaligned access for division by zero. */ +div_table_ix: + .byte -6 + .byte -128 + .byte -128 + .byte 0 + .byte -128 + .byte -64 + .byte 0 + .byte 64 + .byte -128 + .byte -96 + .byte -64 + .byte -32 + .byte 0 + .byte 32 + .byte 64 + .byte 96 + .byte -128 + .byte -112 + .byte -96 + .byte -80 + .byte -64 + .byte -48 + .byte -32 + .byte -16 + .byte 0 + .byte 16 + .byte 32 + .byte 48 + .byte 64 + .byte 80 + .byte 96 + .byte 112 + .byte -128 + .byte -120 + .byte -112 + .byte -104 + .byte -96 + .byte -88 + .byte -80 + .byte -72 + .byte -64 + .byte -56 + .byte -48 + .byte -40 + .byte -32 + .byte -24 + .byte -16 + .byte -8 + .byte 0 + .byte 8 + .byte 16 + .byte 24 + .byte 32 + .byte 40 + .byte 48 + .byte 56 + .byte 64 + .byte 72 + .byte 80 + .byte 88 + .byte 96 + .byte 104 + .byte 112 + .byte 120 + .byte -128 + .byte -124 + .byte -120 + .byte -116 + .byte -112 + .byte -108 + .byte -104 + .byte -100 + .byte -96 + .byte -92 + .byte -88 + .byte -84 + .byte -80 + .byte -76 + .byte -72 + .byte -68 + .byte -64 + .byte -60 + .byte -56 + .byte -52 + .byte -48 + .byte -44 + .byte -40 + .byte -36 + .byte -32 + .byte -28 + .byte -24 + .byte -20 + .byte -16 + .byte -12 + .byte -8 + .byte -4 + .byte 0 + .byte 4 + .byte 8 + .byte 12 + .byte 16 + .byte 20 + .byte 24 + .byte 28 + .byte 32 + .byte 36 + .byte 40 + .byte 44 + .byte 48 + .byte 52 + .byte 56 + .byte 60 + .byte 64 + .byte 68 + .byte 72 + .byte 76 + .byte 80 + .byte 84 + .byte 88 + .byte 92 + .byte 96 + .byte 100 + .byte 104 + .byte 108 + .byte 112 + .byte 116 + .byte 120 + .byte 124 + .byte -128 +/* 1/64 .. 1/127, normalized. There is an implicit leading 1 in bit 32. */ + .balign 4 +zero_l: + .long 0x0 + .long 0xF81F81F9 + .long 0xF07C1F08 + .long 0xE9131AC0 + .long 0xE1E1E1E2 + .long 0xDAE6076C + .long 0xD41D41D5 + .long 0xCD856891 + .long 0xC71C71C8 + .long 0xC0E07039 + .long 0xBACF914D + .long 0xB4E81B4F + .long 0xAF286BCB + .long 0xA98EF607 + .long 0xA41A41A5 + .long 0x9EC8E952 + .long 0x9999999A + .long 0x948B0FCE + .long 0x8F9C18FA + .long 0x8ACB90F7 + .long 0x86186187 + .long 0x81818182 + .long 0x7D05F418 + .long 0x78A4C818 + .long 0x745D1746 + .long 0x702E05C1 + .long 0x6C16C16D + .long 0x68168169 + .long 0x642C8591 + .long 0x60581606 + .long 0x5C9882BA + .long 0x58ED2309 +div_table_inv: + .long 0x55555556 + .long 0x51D07EAF + .long 0x4E5E0A73 + .long 0x4AFD6A06 + .long 0x47AE147B + .long 0x446F8657 + .long 0x41414142 + .long 0x3E22CBCF + .long 0x3B13B13C + .long 0x38138139 + .long 0x3521CFB3 + .long 0x323E34A3 + .long 0x2F684BDB + .long 0x2C9FB4D9 + .long 0x29E4129F + .long 0x27350B89 + .long 0x24924925 + .long 0x21FB7813 + .long 0x1F7047DD + .long 0x1CF06ADB + .long 0x1A7B9612 + .long 0x18118119 + .long 0x15B1E5F8 + .long 0x135C8114 + .long 0x11111112 + .long 0xECF56BF + .long 0xC9714FC + .long 0xA6810A7 + .long 0x8421085 + .long 0x624DD30 + .long 0x4104105 + .long 0x2040811 + /* maximum error: 0.987342 scaled: 0.921875*/ diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c index aa108ca153..458d90c871 100644 --- a/board/balloon3/balloon3.c +++ b/board/balloon3/balloon3.c @@ -29,7 +29,7 @@ int board_init(void) dcache_disable(); icache_disable(); - /* arch number of vpac270 */ + /* arch number of balloon3 */ gd->bd->bi_arch_number = MACH_TYPE_BALLOON3; /* adress of boot parameters */ diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index e0a1031380..565f815781 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -166,8 +166,13 @@ int board_early_init_f(void) int board_mmc_init(bd_t *bd) { struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; + char buffer[HWCONFIG_BUFFER_SIZE] = {0}; + int esdhc_hwconfig_enabled = 0; - if (!hwconfig("esdhc")) + if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) + esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer); + + if (esdhc_hwconfig_enabled == 0) return 0; clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 11472ebaf2..25480e481d 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -20,10 +20,8 @@ void gpio_early_init_uart(void) { /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ -#ifndef CONFIG_SPL_BUILD gpio_request(GPIO_PI3, NULL); -#endif - tegra_spl_gpio_direction_output(GPIO_PI3, 0); + gpio_direction_output(GPIO_PI3, 0); } #endif diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index 8cc17e9581..f0010db814 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -8,6 +8,8 @@ #include <common.h> #include <malloc.h> +#include <dm.h> +#include <dm/platform_data/serial_sh.h> #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> @@ -17,6 +19,7 @@ #include <asm/arch/rmobile.h> #include <asm/arch/rcar-mstp.h> #include <asm/arch/mmc.h> +#include <asm/arch/sh_sdhi.h> #include <netdev.h> #include <miiphy.h> #include <i2c.h> @@ -44,6 +47,11 @@ void s_init(void) #define ETHER_MSTP813 (1 << 13) #define IIC1_MSTP323 (1 << 23) #define MMC0_MSTP315 (1 << 15) +#define SDHI0_MSTP314 (1 << 14) +#define SDHI1_MSTP312 (1 << 12) + +#define SD1CKCR 0xE6150078 +#define SD1_97500KHZ 0x7 int board_early_init_f(void) { @@ -63,6 +71,17 @@ int board_early_init_f(void) /* MMC */ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); #endif + +#ifdef CONFIG_SH_SDHI + /* SDHI0, 1 */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI1_MSTP312); + + /* + * SD0 clock is set to 97.5MHz by default. + * Set SD1 to the 97.5MHz as well. + */ + writel(SD1_97500KHZ, SD1CKCR); +#endif return 0; } @@ -128,7 +147,7 @@ int board_eth_init(bd_t *bis) int board_mmc_init(bd_t *bis) { - int ret = 0; + int ret = -ENODEV; #ifdef CONFIG_SH_MMCIF gpio_request(GPIO_GP_4_31, NULL); @@ -136,6 +155,42 @@ int board_mmc_init(bd_t *bis) ret = mmcif_mmc_init(); #endif + +#ifdef CONFIG_SH_SDHI + gpio_request(GPIO_FN_SD0_DATA0, NULL); + gpio_request(GPIO_FN_SD0_DATA1, NULL); + gpio_request(GPIO_FN_SD0_DATA2, NULL); + gpio_request(GPIO_FN_SD0_DATA3, NULL); + gpio_request(GPIO_FN_SD0_CLK, NULL); + gpio_request(GPIO_FN_SD0_CMD, NULL); + gpio_request(GPIO_FN_SD0_CD, NULL); + gpio_request(GPIO_FN_SD1_DATA0, NULL); + gpio_request(GPIO_FN_SD1_DATA1, NULL); + gpio_request(GPIO_FN_SD1_DATA2, NULL); + gpio_request(GPIO_FN_SD1_DATA3, NULL); + gpio_request(GPIO_FN_SD1_CLK, NULL); + gpio_request(GPIO_FN_SD1_CMD, NULL); + gpio_request(GPIO_FN_SD1_CD, NULL); + + /* SDHI 0 */ + gpio_request(GPIO_GP_2_26, NULL); + gpio_request(GPIO_GP_2_29, NULL); + gpio_direction_output(GPIO_GP_2_26, 1); + gpio_direction_output(GPIO_GP_2_29, 1); + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, + SH_SDHI_QUIRK_16BIT_BUF); + if (ret) + return ret; + + /* SDHI 1 */ + gpio_request(GPIO_GP_4_26, NULL); + gpio_request(GPIO_GP_4_29, NULL); + gpio_direction_output(GPIO_GP_4_26, 1); + gpio_direction_output(GPIO_GP_4_29, 1); + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); +#endif return ret; } @@ -159,3 +214,15 @@ void reset_cpu(ulong addr) val |= 0x02; i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); } + +static const struct sh_serial_platdata serial_platdata = { + .base = SCIF2_BASE, + .type = PORT_SCIF, + .clk = 14745600, + .clk_mode = EXT_CLK, +}; + +U_BOOT_DEVICE(alt_serials) = { + .name = "serial_sh", + .platdata = &serial_platdata, +}; diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c index 677b976aaf..bace439235 100644 --- a/board/renesas/gose/gose.c +++ b/board/renesas/gose/gose.c @@ -8,6 +8,8 @@ #include <common.h> #include <malloc.h> +#include <dm.h> +#include <dm/platform_data/serial_sh.h> #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> @@ -16,6 +18,7 @@ #include <asm/gpio.h> #include <asm/arch/rmobile.h> #include <asm/arch/rcar-mstp.h> +#include <asm/arch/sh_sdhi.h> #include <netdev.h> #include <miiphy.h> #include <i2c.h> @@ -46,6 +49,14 @@ void s_init(void) #define SCIF0_MSTP721 (1 << 21) #define ETHER_MSTP813 (1 << 13) +#define SDHI0_MSTP314 (1 << 14) +#define SDHI1_MSTP312 (1 << 12) +#define SDHI2_MSTP311 (1 << 11) + +#define SD1CKCR 0xE6150078 +#define SD2CKCR 0xE615026C +#define SD_97500KHZ 0x7 + int board_early_init_f(void) { /* TMU0 */ @@ -57,6 +68,12 @@ int board_early_init_f(void) /* ETHER */ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + /* SDHI */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, + SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311); + writel(SD_97500KHZ, SD1CKCR); + writel(SD_97500KHZ, SD2CKCR); + return 0; } @@ -124,6 +141,58 @@ int board_eth_init(bd_t *bis) return ret; } +int board_mmc_init(bd_t *bis) +{ + int ret = -ENODEV; + +#ifdef CONFIG_SH_SDHI + gpio_request(GPIO_FN_SD0_DATA0, NULL); + gpio_request(GPIO_FN_SD0_DATA1, NULL); + gpio_request(GPIO_FN_SD0_DATA2, NULL); + gpio_request(GPIO_FN_SD0_DATA3, NULL); + gpio_request(GPIO_FN_SD0_CLK, NULL); + gpio_request(GPIO_FN_SD0_CMD, NULL); + gpio_request(GPIO_FN_SD0_CD, NULL); + gpio_request(GPIO_FN_SD2_DATA0, NULL); + gpio_request(GPIO_FN_SD2_DATA1, NULL); + gpio_request(GPIO_FN_SD2_DATA2, NULL); + gpio_request(GPIO_FN_SD2_DATA3, NULL); + gpio_request(GPIO_FN_SD2_CLK, NULL); + gpio_request(GPIO_FN_SD2_CMD, NULL); + gpio_request(GPIO_FN_SD2_CD, NULL); + + /* SDHI 0 */ + gpio_request(GPIO_GP_7_17, NULL); + gpio_request(GPIO_GP_2_12, NULL); + gpio_direction_output(GPIO_GP_7_17, 1); /* power on */ + gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, + SH_SDHI_QUIRK_16BIT_BUF); + if (ret) + return ret; + + /* SDHI 1 */ + gpio_request(GPIO_GP_7_18, NULL); + gpio_request(GPIO_GP_2_13, NULL); + gpio_direction_output(GPIO_GP_7_18, 1); /* power on */ + gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); + if (ret) + return ret; + + /* SDHI 2 */ + gpio_request(GPIO_GP_7_19, NULL); + gpio_request(GPIO_GP_2_26, NULL); + gpio_direction_output(GPIO_GP_7_19, 1); /* power on */ + gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); +#endif + return ret; +} + int dram_init(void) { gd->ram_size = CONFIG_SYS_SDRAM_SIZE; @@ -144,3 +213,15 @@ void reset_cpu(ulong addr) val |= 0x02; i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); } + +static const struct sh_serial_platdata serial_platdata = { + .base = SCIF0_BASE, + .type = PORT_SCIF, + .clk = 14745600, + .clk_mode = EXT_CLK, +}; + +U_BOOT_DEVICE(gose_serials) = { + .name = "serial_sh", + .platdata = &serial_platdata, +}; diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 10fa571d07..51e70e222d 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -9,6 +9,8 @@ #include <common.h> #include <malloc.h> +#include <dm.h> +#include <dm/platform_data/serial_sh.h> #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> @@ -17,6 +19,7 @@ #include <asm/gpio.h> #include <asm/arch/rmobile.h> #include <asm/arch/rcar-mstp.h> +#include <asm/arch/sh_sdhi.h> #include <netdev.h> #include <miiphy.h> #include <i2c.h> @@ -48,6 +51,14 @@ void s_init(void) #define SCIF0_MSTP721 (1 << 21) #define ETHER_MSTP813 (1 << 13) +#define SDHI0_MSTP314 (1 << 14) +#define SDHI1_MSTP312 (1 << 12) +#define SDHI2_MSTP311 (1 << 11) + +#define SD1CKCR 0xE6150078 +#define SD2CKCR 0xE615026C +#define SD_97500KHZ 0x7 + int board_early_init_f(void) { mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); @@ -58,6 +69,17 @@ int board_early_init_f(void) /* ETHER */ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + /* SDHI */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, + SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311); + + /* + * SD0 clock is set to 97.5MHz by default. + * Set SD1 and SD2 to the 97.5MHz as well. + */ + writel(SD_97500KHZ, SD1CKCR); + writel(SD_97500KHZ, SD2CKCR); + return 0; } @@ -126,6 +148,58 @@ int board_eth_init(bd_t *bis) #endif } +int board_mmc_init(bd_t *bis) +{ + int ret = -ENODEV; + +#ifdef CONFIG_SH_SDHI + gpio_request(GPIO_FN_SD0_DATA0, NULL); + gpio_request(GPIO_FN_SD0_DATA1, NULL); + gpio_request(GPIO_FN_SD0_DATA2, NULL); + gpio_request(GPIO_FN_SD0_DATA3, NULL); + gpio_request(GPIO_FN_SD0_CLK, NULL); + gpio_request(GPIO_FN_SD0_CMD, NULL); + gpio_request(GPIO_FN_SD0_CD, NULL); + gpio_request(GPIO_FN_SD2_DATA0, NULL); + gpio_request(GPIO_FN_SD2_DATA1, NULL); + gpio_request(GPIO_FN_SD2_DATA2, NULL); + gpio_request(GPIO_FN_SD2_DATA3, NULL); + gpio_request(GPIO_FN_SD2_CLK, NULL); + gpio_request(GPIO_FN_SD2_CMD, NULL); + gpio_request(GPIO_FN_SD2_CD, NULL); + + /* SDHI 0 */ + gpio_request(GPIO_GP_7_17, NULL); + gpio_request(GPIO_GP_2_12, NULL); + gpio_direction_output(GPIO_GP_7_17, 1); /* power on */ + gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, + SH_SDHI_QUIRK_16BIT_BUF); + if (ret) + return ret; + + /* SDHI 1 */ + gpio_request(GPIO_GP_7_18, NULL); + gpio_request(GPIO_GP_2_13, NULL); + gpio_direction_output(GPIO_GP_7_18, 1); /* power on */ + gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); + if (ret) + return ret; + + /* SDHI 2 */ + gpio_request(GPIO_GP_7_19, NULL); + gpio_request(GPIO_GP_2_26, NULL); + gpio_direction_output(GPIO_GP_7_19, 1); /* power on */ + gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); +#endif + return ret; +} + int dram_init(void) { gd->ram_size = CONFIG_SYS_SDRAM_SIZE; @@ -160,3 +234,15 @@ void reset_cpu(ulong addr) val |= 0x02; i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); } + +static const struct sh_serial_platdata serial_platdata = { + .base = SCIF0_BASE, + .type = PORT_SCIF, + .clk = 14745600, + .clk_mode = EXT_CLK, +}; + +U_BOOT_DEVICE(koelsch_serials) = { + .name = "serial_sh", + .platdata = &serial_platdata, +}; diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index d1e29d2cec..83260a1c1a 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -11,6 +11,8 @@ #include <common.h> #include <malloc.h> #include <netdev.h> +#include <dm.h> +#include <dm/platform_data/serial_sh.h> #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> @@ -20,6 +22,7 @@ #include <asm/arch/rmobile.h> #include <asm/arch/rcar-mstp.h> #include <asm/arch/mmc.h> +#include <asm/arch/sh_sdhi.h> #include <miiphy.h> #include <i2c.h> #include <mmc.h> @@ -58,6 +61,15 @@ void s_init(void) #define ETHER_MSTP813 (1 << 13) #define MMC1_MSTP305 (1 << 5) +#define MSTPSR3 0xE6150048 +#define SMSTPCR3 0xE615013C +#define SDHI0_MSTP314 (1 << 14) +#define SDHI1_MSTP313 (1 << 13) +#define SDHI2_MSTP312 (1 << 12) + +#define SD2CKCR 0xE6150078 +#define SD2_97500KHZ 0x7 + int board_early_init_f(void) { /* TMU0 */ @@ -68,6 +80,14 @@ int board_early_init_f(void) mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); /* eMMC */ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC1_MSTP305); + /* SDHI0, 2 */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312); + + /* + * SD0 clock is set to 97.5MHz by default. + * Set SD2 to the 97.5MHz as well. + */ + writel(SD2_97500KHZ, SD2CKCR); return 0; } @@ -148,7 +168,7 @@ int board_phy_config(struct phy_device *phydev) int board_mmc_init(bd_t *bis) { - int ret = 0; + int ret = -ENODEV; #ifdef CONFIG_SH_MMCIF gpio_request(GPIO_FN_MMC1_D0, NULL); @@ -164,6 +184,45 @@ int board_mmc_init(bd_t *bis) ret = mmcif_mmc_init(); #endif + +#ifdef CONFIG_SH_SDHI + gpio_request(GPIO_FN_SD0_DAT0, NULL); + gpio_request(GPIO_FN_SD0_DAT1, NULL); + gpio_request(GPIO_FN_SD0_DAT2, NULL); + gpio_request(GPIO_FN_SD0_DAT3, NULL); + gpio_request(GPIO_FN_SD0_CLK, NULL); + gpio_request(GPIO_FN_SD0_CMD, NULL); + gpio_request(GPIO_FN_SD0_CD, NULL); + gpio_request(GPIO_FN_SD2_DAT0, NULL); + gpio_request(GPIO_FN_SD2_DAT1, NULL); + gpio_request(GPIO_FN_SD2_DAT2, NULL); + gpio_request(GPIO_FN_SD2_DAT3, NULL); + gpio_request(GPIO_FN_SD2_CLK, NULL); + gpio_request(GPIO_FN_SD2_CMD, NULL); + gpio_request(GPIO_FN_SD2_CD, NULL); + + /* + * SDHI 0 + * need JP3 set to pin-1 side on board. + */ + gpio_request(GPIO_GP_5_24, NULL); + gpio_request(GPIO_GP_5_29, NULL); + gpio_direction_output(GPIO_GP_5_24, 1); /* power on */ + gpio_direction_output(GPIO_GP_5_29, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, + SH_SDHI_QUIRK_16BIT_BUF); + if (ret) + return ret; + + /* SDHI 2 */ + gpio_request(GPIO_GP_5_25, NULL); + gpio_request(GPIO_GP_5_30, NULL); + gpio_direction_output(GPIO_GP_5_25, 1); /* power on */ + gpio_direction_output(GPIO_GP_5_30, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); +#endif return ret; } @@ -189,3 +248,15 @@ void reset_cpu(ulong addr) val |= 0x02; i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); } + +static const struct sh_serial_platdata serial_platdata = { + .base = SCIF0_BASE, + .type = PORT_SCIF, + .clk = 14745600, + .clk_mode = EXT_CLK, +}; + +U_BOOT_DEVICE(lager_serials) = { + .name = "serial_sh", + .platdata = &serial_platdata, +}; diff --git a/board/renesas/porter/Kconfig b/board/renesas/porter/Kconfig new file mode 100644 index 0000000000..a6f621b73f --- /dev/null +++ b/board/renesas/porter/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PORTER + +config SYS_BOARD + default "porter" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "porter" + +endif diff --git a/board/renesas/porter/MAINTAINERS b/board/renesas/porter/MAINTAINERS new file mode 100644 index 0000000000..1dc6a1caf2 --- /dev/null +++ b/board/renesas/porter/MAINTAINERS @@ -0,0 +1,6 @@ +PORTER BOARD +M: Cogent Embedded, Inc. <source@cogentembedded.com> +S: Maintained +F: board/renesas/porter/ +F: include/configs/porter.h +F: configs/porter_defconfig diff --git a/board/renesas/porter/Makefile b/board/renesas/porter/Makefile new file mode 100644 index 0000000000..dbf32e9c54 --- /dev/null +++ b/board/renesas/porter/Makefile @@ -0,0 +1,10 @@ +# +# board/renesas/porter/Makefile +# +# Copyright (C) 2015 Renesas Electronics Corporation +# Copyright (C) 2015 Cogent Embedded, Inc. +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := porter.o qos.o ../rcar-gen2-common/common.o diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c new file mode 100644 index 0000000000..b5378defa8 --- /dev/null +++ b/board/renesas/porter/porter.c @@ -0,0 +1,228 @@ +/* + * board/renesas/porter/porter.c + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <dm.h> +#include <dm/platform_data/serial_sh.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> +#include <asm/arch/sh_sdhi.h> +#include <netdev.h> +#include <miiphy.h> +#include <i2c.h> +#include <div64.h> +#include "qos.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + u32 stc; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + /* CPU frequency setting. Set to 1.5GHz */ + stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; + clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); + + /* QoS */ + qos_init(); +} + +#define TMU0_MSTP125 (1 << 25) +#define SDHI0_MSTP314 (1 << 14) +#define SDHI2_MSTP311 (1 << 11) +#define SCIF0_MSTP721 (1 << 21) +#define ETHER_MSTP813 (1 << 13) + +#define SD2CKCR 0xE615026C +#define SD_97500KHZ 0x7 + +int board_early_init_f(void) +{ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + + /* SCIF0 */ + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); + + /* ETHER */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + + /* SDHI */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP311); + + /* + * SD0 clock is set to 97.5MHz by default. + * Set SD2 to the 97.5MHz as well. + */ + writel(SD_97500KHZ, SD2CKCR); + + return 0; +} + +/* LSI pin pull-up control */ +#define PUPR5 0xe6060114 +#define PUPR5_ETH 0x3FFC0000 +#define PUPR5_ETH_MAGIC (1 << 27) +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + /* Init PFC controller */ + r8a7791_pinmux_init(); + + /* Ether Enable */ + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); + gpio_request(GPIO_FN_ETH_RX_ER, NULL); + gpio_request(GPIO_FN_ETH_RXD0, NULL); + gpio_request(GPIO_FN_ETH_RXD1, NULL); + gpio_request(GPIO_FN_ETH_LINK, NULL); + gpio_request(GPIO_FN_ETH_REFCLK, NULL); + gpio_request(GPIO_FN_ETH_MDIO, NULL); + gpio_request(GPIO_FN_ETH_TXD1, NULL); + gpio_request(GPIO_FN_ETH_TX_EN, NULL); + gpio_request(GPIO_FN_ETH_TXD0, NULL); + gpio_request(GPIO_FN_ETH_MDC, NULL); + gpio_request(GPIO_FN_IRQ0, NULL); + + mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); + gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ + mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); + + gpio_direction_output(GPIO_GP_5_22, 0); + mdelay(20); + gpio_set_value(GPIO_GP_5_22, 1); + udelay(1); + + return 0; +} + +#define CXR24 0xEE7003C0 /* MAC address high register */ +#define CXR25 0xEE7003C8 /* MAC address low register */ +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SH_ETHER + int ret = -ENODEV; + u32 val; + unsigned char enetaddr[6]; + + ret = sh_eth_initialize(bis); + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return ret; + + /* Set Mac address */ + val = enetaddr[0] << 24 | enetaddr[1] << 16 | + enetaddr[2] << 8 | enetaddr[3]; + writel(val, CXR24); + + val = enetaddr[4] << 8 | enetaddr[5]; + writel(val, CXR25); + + return ret; +#else + return 0; +#endif +} + +int board_mmc_init(bd_t *bis) +{ + int ret = -ENODEV; + +#ifdef CONFIG_SH_SDHI + gpio_request(GPIO_FN_SD0_DATA0, NULL); + gpio_request(GPIO_FN_SD0_DATA1, NULL); + gpio_request(GPIO_FN_SD0_DATA2, NULL); + gpio_request(GPIO_FN_SD0_DATA3, NULL); + gpio_request(GPIO_FN_SD0_CLK, NULL); + gpio_request(GPIO_FN_SD0_CMD, NULL); + gpio_request(GPIO_FN_SD0_CD, NULL); + gpio_request(GPIO_FN_SD2_DATA0, NULL); + gpio_request(GPIO_FN_SD2_DATA1, NULL); + gpio_request(GPIO_FN_SD2_DATA2, NULL); + gpio_request(GPIO_FN_SD2_DATA3, NULL); + gpio_request(GPIO_FN_SD2_CLK, NULL); + gpio_request(GPIO_FN_SD2_CMD, NULL); + gpio_request(GPIO_FN_SD2_CD, NULL); + + /* SDHI 0 */ + gpio_request(GPIO_GP_2_12, NULL); + gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, + SH_SDHI_QUIRK_16BIT_BUF); + if (ret) + return ret; + + /* SDHI 2 */ + gpio_request(GPIO_GP_2_26, NULL); + gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); +#endif + return ret; +} + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +/* porter has KSZ8041RNLI */ +#define PHY_CONTROL1 0x1E +#define PHY_LED_MODE 0xC0000 +#define PHY_LED_MODE_ACK 0x4000 +int board_phy_config(struct phy_device *phydev) +{ + int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); + ret &= ~PHY_LED_MODE; + ret |= PHY_LED_MODE_ACK; + ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); + + return 0; +} + +const struct rmobile_sysinfo sysinfo = { + CONFIG_RMOBILE_BOARD_STRING +}; + +void reset_cpu(ulong addr) +{ + u8 val; + + i2c_set_bus_num(2); /* PowerIC connected to ch2 */ + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + val |= 0x02; + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); +} + +static const struct sh_serial_platdata serial_platdata = { + .base = SCIF0_BASE, + .type = PORT_SCIF, + .clk = CONFIG_P_CLK_FREQ, +}; + +U_BOOT_DEVICE(porter_serials) = { + .name = "serial_sh", + .platdata = &serial_platdata, +}; diff --git a/board/renesas/porter/qos.c b/board/renesas/porter/qos.c new file mode 100644 index 0000000000..491d1bab86 --- /dev/null +++ b/board/renesas/porter/qos.c @@ -0,0 +1,1312 @@ +/* + * board/renesas/porter/qos.c + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <asm/arch/rmobile.h> + +/* QoS version 0.240 for ES1 and version 0.334 for ES2 */ +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +enum { + DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, + DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, + DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, + DBSC3_15, + DBSC3_NR, +}; + +static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_R0_BASE, + [DBSC3_01] = DBSC3_0_QOS_R1_BASE, + [DBSC3_02] = DBSC3_0_QOS_R2_BASE, + [DBSC3_03] = DBSC3_0_QOS_R3_BASE, + [DBSC3_04] = DBSC3_0_QOS_R4_BASE, + [DBSC3_05] = DBSC3_0_QOS_R5_BASE, + [DBSC3_06] = DBSC3_0_QOS_R6_BASE, + [DBSC3_07] = DBSC3_0_QOS_R7_BASE, + [DBSC3_08] = DBSC3_0_QOS_R8_BASE, + [DBSC3_09] = DBSC3_0_QOS_R9_BASE, + [DBSC3_10] = DBSC3_0_QOS_R10_BASE, + [DBSC3_11] = DBSC3_0_QOS_R11_BASE, + [DBSC3_12] = DBSC3_0_QOS_R12_BASE, + [DBSC3_13] = DBSC3_0_QOS_R13_BASE, + [DBSC3_14] = DBSC3_0_QOS_R14_BASE, + [DBSC3_15] = DBSC3_0_QOS_R15_BASE, +}; + +static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_W0_BASE, + [DBSC3_01] = DBSC3_0_QOS_W1_BASE, + [DBSC3_02] = DBSC3_0_QOS_W2_BASE, + [DBSC3_03] = DBSC3_0_QOS_W3_BASE, + [DBSC3_04] = DBSC3_0_QOS_W4_BASE, + [DBSC3_05] = DBSC3_0_QOS_W5_BASE, + [DBSC3_06] = DBSC3_0_QOS_W6_BASE, + [DBSC3_07] = DBSC3_0_QOS_W7_BASE, + [DBSC3_08] = DBSC3_0_QOS_W8_BASE, + [DBSC3_09] = DBSC3_0_QOS_W9_BASE, + [DBSC3_10] = DBSC3_0_QOS_W10_BASE, + [DBSC3_11] = DBSC3_0_QOS_W11_BASE, + [DBSC3_12] = DBSC3_0_QOS_W12_BASE, + [DBSC3_13] = DBSC3_0_QOS_W13_BASE, + [DBSC3_14] = DBSC3_0_QOS_W14_BASE, + [DBSC3_15] = DBSC3_0_QOS_W15_BASE, +}; + +static u32 dbsc3_1_r_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_1_QOS_R0_BASE, + [DBSC3_01] = DBSC3_1_QOS_R1_BASE, + [DBSC3_02] = DBSC3_1_QOS_R2_BASE, + [DBSC3_03] = DBSC3_1_QOS_R3_BASE, + [DBSC3_04] = DBSC3_1_QOS_R4_BASE, + [DBSC3_05] = DBSC3_1_QOS_R5_BASE, + [DBSC3_06] = DBSC3_1_QOS_R6_BASE, + [DBSC3_07] = DBSC3_1_QOS_R7_BASE, + [DBSC3_08] = DBSC3_1_QOS_R8_BASE, + [DBSC3_09] = DBSC3_1_QOS_R9_BASE, + [DBSC3_10] = DBSC3_1_QOS_R10_BASE, + [DBSC3_11] = DBSC3_1_QOS_R11_BASE, + [DBSC3_12] = DBSC3_1_QOS_R12_BASE, + [DBSC3_13] = DBSC3_1_QOS_R13_BASE, + [DBSC3_14] = DBSC3_1_QOS_R14_BASE, + [DBSC3_15] = DBSC3_1_QOS_R15_BASE, +}; + +static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_1_QOS_W0_BASE, + [DBSC3_01] = DBSC3_1_QOS_W1_BASE, + [DBSC3_02] = DBSC3_1_QOS_W2_BASE, + [DBSC3_03] = DBSC3_1_QOS_W3_BASE, + [DBSC3_04] = DBSC3_1_QOS_W4_BASE, + [DBSC3_05] = DBSC3_1_QOS_W5_BASE, + [DBSC3_06] = DBSC3_1_QOS_W6_BASE, + [DBSC3_07] = DBSC3_1_QOS_W7_BASE, + [DBSC3_08] = DBSC3_1_QOS_W8_BASE, + [DBSC3_09] = DBSC3_1_QOS_W9_BASE, + [DBSC3_10] = DBSC3_1_QOS_W10_BASE, + [DBSC3_11] = DBSC3_1_QOS_W11_BASE, + [DBSC3_12] = DBSC3_1_QOS_W12_BASE, + [DBSC3_13] = DBSC3_1_QOS_W13_BASE, + [DBSC3_14] = DBSC3_1_QOS_W14_BASE, + [DBSC3_15] = DBSC3_1_QOS_W15_BASE, +}; + +void qos_init(void) +{ + int i; + struct rcar_s3c *s3c; + struct rcar_s3c_qos *s3c_qos; + struct rcar_dbsc3_qos *qos_addr; + struct rcar_mxi *mxi; + struct rcar_mxi_qos *mxi_qos; + struct rcar_axi_qos *axi_qos; + + /* DBSC DBADJ2 */ + writel(0x20042004, DBSC3_0_DBADJ2); + writel(0x20042004, DBSC3_1_DBADJ2); + + /* S3C -QoS */ + s3c = (struct rcar_s3c *)S3C_BASE; + if (IS_R8A7791_ES2()) { + /* Linear All mode */ + /* writel(0x00000000, &s3c->s3cadsplcr); */ + /* Linear Linear 0x7000 to 0x7800 mode */ + writel(0x00BF1B0C, &s3c->s3cadsplcr); + /* Split Linear 0x6800 t 0x7000 mode */ + /* writel(0x00DF1B0C, &s3c->s3cadsplcr); */ + /* Ssplit All mode */ + /* writel(0x00FF1B0C, &s3c->s3cadsplcr); */ + writel(0x1F0B0908, &s3c->s3crorr); + writel(0x1F0C0A08, &s3c->s3cworr); + } else { + writel(0x00FF1B1D, &s3c->s3cadsplcr); + writel(0x1F0D0C0C, &s3c->s3crorr); + writel(0x1F0D0C0A, &s3c->s3cworr); + } + /* QoS Control Registers */ + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20DC, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20DC, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20FA, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20FA, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + /* DBSC -QoS */ + /* DBSC0 - Read */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002032, &qos_addr->dbtmval2); + writel(0x00001FB0, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000201E, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* DBSC0 - Write */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002050, &qos_addr->dbtmval2); + writel(0x0000203A, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000203C, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* DBSC1 - Read */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_r_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002032, &qos_addr->dbtmval2); + writel(0x00001FB0, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000201E, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* DBSC1 - Write */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_w_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002050, &qos_addr->dbtmval2); + writel(0x0000203A, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000203C, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* CCI-400 -QoS */ + writel(0x20001000, CCI_400_MAXOT_1); + writel(0x20001000, CCI_400_MAXOT_2); + writel(0x0000000C, CCI_400_QOSCNTL_1); + writel(0x0000000C, CCI_400_QOSCNTL_2); + + /* MXI -QoS */ + /* Transaction Control (MXI) */ + mxi = (struct rcar_mxi *)MXI_BASE; + writel(0x00000013, &mxi->mxrtcr); + writel(0x00000013, &mxi->mxwtcr); + + /* QoS Control (MXI) */ + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; + writel(0x0000000C, &mxi_qos->vspdu0); + writel(0x0000000C, &mxi_qos->vspdu1); + writel(0x0000000E, &mxi_qos->du0); + writel(0x0000000D, &mxi_qos->du1); + + /* AXI -QoS */ + /* Transaction Control (MXI) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (RT-AXI) */ + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002299, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (MP-AXI) */ + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000206E, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (SYS-AXI256) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; + writel(0x00000002, &axi_qos->qosconf); + if (IS_R8A7791_ES2()) + writel(0x000020EB, &axi_qos->qosctset0); + else + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; + writel(0x00000002, &axi_qos->qosconf); + if (IS_R8A7791_ES2()) + writel(0x000020EB, &axi_qos->qosctset0); + else + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; + writel(0x00000002, &axi_qos->qosconf); + if (IS_R8A7791_ES2()) + writel(0x000020EB, &axi_qos->qosctset0); + else + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (CCI-AXI) */ + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (Media-AXI) */ + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + if (IS_R8A7791_ES2()) + writel(0x00001FF0, &axi_qos->qosctset0); + else + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + if (IS_R8A7791_ES2()) + writel(0x00002001, &axi_qos->qosthres2); + else + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000003, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000003, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000003, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000003, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000003, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000000, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); +} +#else /* CONFIG_RMOBILE_EXTRAM_BOOT */ +void qos_init(void) +{ +} +#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */ diff --git a/board/renesas/porter/qos.h b/board/renesas/porter/qos.h new file mode 100644 index 0000000000..75a20bb075 --- /dev/null +++ b/board/renesas/porter/qos.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __QOS_H__ +#define __QOS_H__ + +void qos_init(void); + +#endif diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c index dfd9a9d3e4..021baabc65 100644 --- a/board/renesas/silk/silk.c +++ b/board/renesas/silk/silk.c @@ -9,6 +9,8 @@ #include <common.h> #include <malloc.h> +#include <dm.h> +#include <dm/platform_data/serial_sh.h> #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> @@ -18,6 +20,7 @@ #include <asm/arch/rmobile.h> #include <asm/arch/rcar-mstp.h> #include <asm/arch/mmc.h> +#include <asm/arch/sh_sdhi.h> #include <netdev.h> #include <miiphy.h> #include <i2c.h> @@ -45,6 +48,10 @@ void s_init(void) #define ETHER_MSTP813 (1 << 13) #define IIC1_MSTP323 (1 << 23) #define MMC0_MSTP315 (1 << 15) +#define SDHI1_MSTP312 (1 << 12) + +#define SD1CKCR 0xE6150078 +#define SD1_97500KHZ 0x7 int board_early_init_f(void) { @@ -64,9 +71,24 @@ int board_early_init_f(void) /* MMC */ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); #endif + +#ifdef CONFIG_SH_SDHI + /* SDHI1 */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI1_MSTP312); + + /* + * Set SD1 to the 97.5MHz + */ + writel(SD1_97500KHZ, SD1CKCR); +#endif return 0; } +/* LSI pin pull-up control */ +#define PUPR3 0xe606010C +#define PUPR3_ETH 0x006FF800 +#define PUPR1 0xe6060104 +#define PUPR1_DREQ0_N (1 << 20) int board_init(void) { /* adress of boot parameters */ @@ -91,7 +113,10 @@ int board_init(void) gpio_request(GPIO_FN_IRQ8, NULL); /* PHY reset */ + mstp_clrbits_le32(PUPR3, PUPR3, PUPR3_ETH); gpio_request(GPIO_GP_1_24, NULL); + mstp_clrbits_le32(PUPR1, PUPR1, PUPR1_DREQ0_N); + gpio_direction_output(GPIO_GP_1_24, 0); mdelay(20); gpio_set_value(GPIO_GP_1_24, 1); @@ -129,15 +154,33 @@ int board_eth_init(bd_t *bis) int board_mmc_init(bd_t *bis) { - int ret = 0; + int ret = -ENODEV; #ifdef CONFIG_SH_MMCIF /* MMC0 */ gpio_request(GPIO_GP_4_31, NULL); - gpio_set_value(GPIO_GP_4_31, 1); + gpio_direction_output(GPIO_GP_4_31, 1); ret = mmcif_mmc_init(); #endif + +#ifdef CONFIG_SH_SDHI + gpio_request(GPIO_FN_SD1_DATA0, NULL); + gpio_request(GPIO_FN_SD1_DATA1, NULL); + gpio_request(GPIO_FN_SD1_DATA2, NULL); + gpio_request(GPIO_FN_SD1_DATA3, NULL); + gpio_request(GPIO_FN_SD1_CLK, NULL); + gpio_request(GPIO_FN_SD1_CMD, NULL); + gpio_request(GPIO_FN_SD1_CD, NULL); + + /* SDHI 1 */ + gpio_request(GPIO_GP_4_26, NULL); + gpio_request(GPIO_GP_4_29, NULL); + gpio_direction_output(GPIO_GP_4_26, 1); + gpio_direction_output(GPIO_GP_4_29, 1); + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); +#endif return ret; } @@ -161,3 +204,15 @@ void reset_cpu(ulong addr) val |= 0x02; i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); } + +static const struct sh_serial_platdata serial_platdata = { + .base = SCIF2_BASE, + .type = PORT_SCIF, + .clk = 14745600, + .clk_mode = EXT_CLK, +}; + +U_BOOT_DEVICE(silk_serials) = { + .name = "serial_sh", + .platdata = &serial_platdata, +}; diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index da2245ff9d..2e17da8a7a 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -82,13 +82,19 @@ int board_init(void) } boot_temp_check(); #endif +#ifdef CONFIG_TZSW_RESERVED_DRAM_SIZE + /* The last few MB of memory can be reserved for secure firmware */ + ulong size = CONFIG_TZSW_RESERVED_DRAM_SIZE; + gd->ram_size -= size; + gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; +#endif return exynos_init(); } int dram_init(void) { - int i; + unsigned int i; u32 addr; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { @@ -100,7 +106,7 @@ int dram_init(void) void dram_init_banksize(void) { - int i; + unsigned int i; u32 addr, size; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { @@ -338,9 +344,6 @@ int arch_early_init_r(void) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { -#ifdef CONFIG_SET_DFU_ALT_INFO - set_dfu_alt_info(); -#endif #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG set_board_info(); #endif diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 4538ac7f2a..1a77c820ae 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SET_DFU_ALT_INFO -void set_dfu_alt_info(void) +void set_dfu_alt_info(char *interface, char *devstr) { size_t buf_size = CONFIG_SET_DFU_ALT_BUF_LEN; ALLOC_CACHE_ALIGN_BUFFER(char, buf, buf_size); @@ -34,13 +34,13 @@ void set_dfu_alt_info(void) puts("DFU alt info setting: "); - alt_setting = get_dfu_alt_boot(); + alt_setting = get_dfu_alt_boot(interface, devstr); if (alt_setting) { setenv("dfu_alt_boot", alt_setting); offset = snprintf(buf, buf_size, "%s", alt_setting); } - alt_setting = get_dfu_alt_system(); + alt_setting = get_dfu_alt_system(interface, devstr); if (alt_setting) { if (offset) alt_sep = ";"; diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index bff6ac928c..ae41c29d92 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -15,6 +15,7 @@ #include <power/pmic.h> #include <power/max77686_pmic.h> #include <errno.h> +#include <mmc.h> #include <usb.h> #include <usb/s3c_udc.h> #include <samsung/misc.h> @@ -61,27 +62,29 @@ const char *get_board_type(void) #endif #ifdef CONFIG_SET_DFU_ALT_INFO -char *get_dfu_alt_system(void) +char *get_dfu_alt_system(char *interface, char *devstr) { return getenv("dfu_alt_system"); } -char *get_dfu_alt_boot(void) +char *get_dfu_alt_boot(char *interface, char *devstr) { + struct mmc *mmc; char *alt_boot; + int dev_num; + + dev_num = simple_strtoul(devstr, NULL, 10); + + mmc = find_mmc_device(dev_num); + if (!mmc) + return NULL; + + if (mmc_init(mmc)) + return NULL; + + alt_boot = IS_SD(mmc) ? CONFIG_DFU_ALT_BOOT_SD : + CONFIG_DFU_ALT_BOOT_EMMC; - switch (get_boot_mode()) { - case BOOT_MODE_SD: - alt_boot = CONFIG_DFU_ALT_BOOT_SD; - break; - case BOOT_MODE_EMMC: - case BOOT_MODE_EMMC_SD: - alt_boot = CONFIG_DFU_ALT_BOOT_EMMC; - break; - default: - alt_boot = NULL; - break; - } return alt_boot; } #endif @@ -424,10 +427,6 @@ int exynos_early_init_f(void) int exynos_init(void) { - /* The last MB of memory is reserved for secure firmware */ - gd->ram_size -= SZ_1M; - gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M; - board_gpio_init(); return 0; diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS index d166fa0be3..c99e06dc10 100644 --- a/board/ti/am335x/MAINTAINERS +++ b/board/ti/am335x/MAINTAINERS @@ -1,5 +1,5 @@ AM335X BOARD -M: Tom Rini <trini@ti.com> +M: Tom Rini <trini@konsulko.com> S: Maintained F: board/ti/am335x/ F: include/configs/am335x_evm.h @@ -9,9 +9,4 @@ F: configs/am335x_evm_defconfig F: configs/am335x_evm_nor_defconfig F: configs/am335x_evm_norboot_defconfig F: configs/am335x_evm_spiboot_defconfig -F: configs/am335x_evm_uart1_defconfig -F: configs/am335x_evm_uart2_defconfig -F: configs/am335x_evm_uart3_defconfig -F: configs/am335x_evm_uart4_defconfig -F: configs/am335x_evm_uart5_defconfig F: configs/am335x_evm_usbspl_defconfig diff --git a/board/ti/beagle/MAINTAINERS b/board/ti/beagle/MAINTAINERS index 2225fb63b0..c1d81d4174 100644 --- a/board/ti/beagle/MAINTAINERS +++ b/board/ti/beagle/MAINTAINERS @@ -1,5 +1,5 @@ BEAGLE BOARD -M: Tom Rini <trini@ti.com> +M: Tom Rini <trini@konsulko.com> S: Maintained F: board/ti/beagle/ F: include/configs/omap3_beagle.h diff --git a/board/ti/evm/MAINTAINERS b/board/ti/evm/MAINTAINERS index d0b27882bc..90c3f6b9a7 100644 --- a/board/ti/evm/MAINTAINERS +++ b/board/ti/evm/MAINTAINERS @@ -1,14 +1,10 @@ EVM BOARD -M: Tom Rini <trini@ti.com> +M: Tom Rini <trini@konsulko.com> S: Maintained F: board/ti/evm/ F: include/configs/omap3_evm.h -F: configs/omap3_evm_defconfig - -OMAP3_EVM_QUICK_MMC BOARD -#M: - -S: Maintained F: include/configs/omap3_evm_quick_mmc.h -F: configs/omap3_evm_quick_mmc_defconfig F: include/configs/omap3_evm_quick_nand.h +F: configs/omap3_evm_defconfig +F: configs/omap3_evm_quick_mmc_defconfig F: configs/omap3_evm_quick_nand_defconfig diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c index 8d95e4d174..3def0a6fd0 100644 --- a/board/toradex/colibri_pxa270/colibri_pxa270.c +++ b/board/toradex/colibri_pxa270/colibri_pxa270.c @@ -23,7 +23,7 @@ int board_init(void) dcache_disable(); icache_disable(); - /* arch number of vpac270 */ + /* arch number of Toradex Colibri PXA270 */ gd->bd->bi_arch_number = MACH_TYPE_COLIBRI; /* adress of boot parameters */ diff --git a/board/xilinx/zynqmp/Kconfig b/board/xilinx/zynqmp/Kconfig new file mode 100644 index 0000000000..b07932e805 --- /dev/null +++ b/board/xilinx/zynqmp/Kconfig @@ -0,0 +1,15 @@ +if TARGET_XILINX_ZYNQMP + +config SYS_BOARD + default "zynqmp" + +config SYS_VENDOR + default "xilinx" + +config SYS_SOC + default "zynqmp" + +config SYS_CONFIG_NAME + default "xilinx_zynqmp" + +endif diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS new file mode 100644 index 0000000000..da33340459 --- /dev/null +++ b/board/xilinx/zynqmp/MAINTAINERS @@ -0,0 +1,6 @@ +XILINX_ZYNQMP BOARD +M: Michal Simek <michal.simek@xilinx.com> +S: Maintained +F: board/xilinx/zynqmp/ +F: include/configs/xilinx_zynqmp.h +F: configs/xilinx_zynqmp_defconfig diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile new file mode 100644 index 0000000000..2ab3f190ac --- /dev/null +++ b/board/xilinx/zynqmp/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 - 2015 Xilinx, Inc. +# Michal Simek <michal.simek@xilinx.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := zynqmp.o diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c new file mode 100644 index 0000000000..1325bca5e5 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp.c @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <netdev.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int board_early_init_r(void) +{ + u32 val; + + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + /* Program freq register in System counter and enable system counter */ + writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register); + writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG | + ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, + &iou_scntr->counter_control_register); + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int timer_init(void) +{ + return 0; +} + +void reset_cpu(ulong addr) +{ +} + +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bd) +{ + int ret = 0; + +#if defined(CONFIG_ZYNQ_SDHCI) +# if defined(CONFIG_ZYNQ_SDHCI0) + ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); +# endif +# if defined(CONFIG_ZYNQ_SDHCI1) + ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); +# endif +#endif + + return ret; +} +#endif + +int board_late_init(void) +{ + u32 reg = 0; + u8 bootmode; + + reg = readl(&crlapb_base->boot_mode); + bootmode = reg & BOOT_MODES_MASK; + + switch (bootmode) { + case SD_MODE: + setenv("modeboot", "sdboot"); + break; + default: + printf("Invalid Boot Mode:0x%x\n", bootmode); + break; + } + + return 0; +} diff --git a/common/cmd_fastboot.c b/common/cmd_fastboot.c index b72f4f310d..346ab80454 100644 --- a/common/cmd_fastboot.c +++ b/common/cmd_fastboot.c @@ -20,6 +20,12 @@ static int do_fastboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) if (ret) return ret; + if (!g_dnl_board_usb_cable_connected()) { + puts("\rUSB cable not detected.\n" \ + "Command exit.\n"); + return CMD_RET_FAILURE; + } + while (1) { if (g_dnl_detach()) break; diff --git a/common/fb_mmc.c b/common/fb_mmc.c index 6ea3938d83..75899e4c28 100644 --- a/common/fb_mmc.c +++ b/common/fb_mmc.c @@ -10,6 +10,7 @@ #include <part.h> #include <aboot.h> #include <sparse_format.h> +#include <mmc.h> #ifndef CONFIG_FASTBOOT_GPT_NAME #define CONFIG_FASTBOOT_GPT_NAME GPT_ENTRY_NAME @@ -22,13 +23,13 @@ static char *response_str; void fastboot_fail(const char *s) { - strncpy(response_str, "FAIL", 4); + strncpy(response_str, "FAIL\0", 5); strncat(response_str, s, RESPONSE_LEN - 4 - 1); } void fastboot_okay(const char *s) { - strncpy(response_str, "OKAY", 4); + strncpy(response_str, "OKAY\0", 5); strncat(response_str, s, RESPONSE_LEN - 4 - 1); } @@ -110,3 +111,58 @@ void fb_mmc_flash_write(const char *cmd, void *download_buffer, write_raw_image(dev_desc, &info, cmd, download_buffer, download_bytes); } + +void fb_mmc_erase(const char *cmd, char *response) +{ + int ret; + block_dev_desc_t *dev_desc; + disk_partition_t info; + lbaint_t blks, blks_start, blks_size, grp_size; + struct mmc *mmc = find_mmc_device(CONFIG_FASTBOOT_FLASH_MMC_DEV); + + if (mmc == NULL) { + error("invalid mmc device"); + fastboot_fail("invalid mmc device"); + return; + } + + /* initialize the response buffer */ + response_str = response; + + dev_desc = get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV); + if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) { + error("invalid mmc device"); + fastboot_fail("invalid mmc device"); + return; + } + + ret = get_partition_info_efi_by_name(dev_desc, cmd, &info); + if (ret) { + error("cannot find partition: '%s'", cmd); + fastboot_fail("cannot find partition"); + return; + } + + /* Align blocks to erase group size to avoid erasing other partitions */ + grp_size = mmc->erase_grp_size; + blks_start = (info.start + grp_size - 1) & ~(grp_size - 1); + if (info.size >= grp_size) + blks_size = (info.size - (blks_start - info.start)) & + (~(grp_size - 1)); + else + blks_size = 0; + + printf("Erasing blocks " LBAFU " to " LBAFU " due to alignment\n", + blks_start, blks_start + blks_size); + + blks = dev_desc->block_erase(dev_desc->dev, blks_start, blks_size); + if (blks != blks_size) { + error("failed erasing from device %d", dev_desc->dev); + fastboot_fail("failed erasing from device"); + return; + } + + printf("........ erased " LBAFU " bytes from '%s'\n", + blks_size * info.blksz, cmd); + fastboot_okay(""); +} diff --git a/common/spl/spl.c b/common/spl/spl.c index ded0f30478..cd75bbc4ce 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -281,3 +281,38 @@ void preloader_console_init(void) spl_display_print(); #endif } + +/** + * spl_relocate_stack_gd() - Relocate stack ready for board_init_r() execution + * + * Sometimes board_init_f() runs with a stack in SRAM but we want to use SDRAM + * for the main board_init_r() execution. This is typically because we need + * more stack space for things like the MMC sub-system. + * + * This function calculates the stack position, copies the global_data into + * place and returns the new stack position. The caller is responsible for + * setting up the sp register. + * + * @return new stack location, or 0 to use the same stack + */ +ulong spl_relocate_stack_gd(void) +{ +#ifdef CONFIG_SPL_STACK_R + gd_t *new_gd; + ulong ptr; + + /* Get stack position: use 8-byte alignment for ABI compliance */ + ptr = CONFIG_SPL_STACK_R - sizeof(gd_t); + ptr &= ~7; + new_gd = (gd_t *)ptr; + memcpy(new_gd, (void *)gd, sizeof(gd_t)); + gd = new_gd; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + return ptr; +#else + return 0; +#endif +} diff --git a/configs/alt_defconfig b/configs/alt_defconfig index d722306d4d..ff872302b4 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -1,3 +1,6 @@ CONFIG_ARM=y CONFIG_RMOBILE=y CONFIG_TARGET_ALT=y +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_SH_SDHI=y diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig index b631c410dc..f5b807b059 100644 --- a/configs/am335x_boneblack_defconfig +++ b/configs/am335x_boneblack_defconfig @@ -1,4 +1,6 @@ CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT" +S:CONFIG_ARM=y +S:CONFIG_TARGET_AM335X_EVM=y diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index 51bf370364..db27c3e70b 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -1,4 +1,6 @@ CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT" +S:CONFIG_ARM=y +S:CONFIG_TARGET_AM335X_EVM=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 2e5aeaa4dd..b2f332ea76 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -1,4 +1,6 @@ CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_CONS_INDEX=1 +S:CONFIG_ARM=y diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig index be901633ac..ed72af6d33 100644 --- a/configs/am335x_evm_nor_defconfig +++ b/configs/am335x_evm_nor_defconfig @@ -1,4 +1,6 @@ CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_CONS_INDEX=1 +S:CONFIG_ARM=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index a6188ea726..097dd47320 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -1,4 +1,6 @@ CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT" CONFIG_CONS_INDEX=1 +S:CONFIG_ARM=y diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig index 352c1fb596..773042a393 100644 --- a/configs/am335x_evm_usbspl_defconfig +++ b/configs/am335x_evm_usbspl_defconfig @@ -1,4 +1,6 @@ CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT" CONFIG_CONS_INDEX=1 +S:CONFIG_ARM=y diff --git a/configs/am335x_igep0033_defconfig b/configs/am335x_igep0033_defconfig index f3544b5238..7634d03d3b 100644 --- a/configs/am335x_igep0033_defconfig +++ b/configs/am335x_igep0033_defconfig @@ -1,4 +1,6 @@ CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +S:CONFIG_ARM=y +S:CONFIG_TARGET_AM335X_IGEP0033=y CONFIG_SYS_MALLOC_F=y diff --git a/configs/gose_defconfig b/configs/gose_defconfig index 54a56f5e71..353f854a40 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -1,3 +1,6 @@ CONFIG_ARM=y CONFIG_RMOBILE=y CONFIG_TARGET_GOSE=y +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_SH_SDHI=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index 35f605cb74..b1e35299f5 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -1,3 +1,6 @@ CONFIG_ARM=y CONFIG_RMOBILE=y CONFIG_TARGET_KOELSCH=y +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_SH_SDHI=y diff --git a/configs/lager_defconfig b/configs/lager_defconfig index 8b4aeea9a8..950b037eb8 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -1,3 +1,6 @@ CONFIG_ARM=y CONFIG_RMOBILE=y CONFIG_TARGET_LAGER=y +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_SH_SDHI=y diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig index fa8d291ca1..292f2ca13e 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/ph1_ld4_defconfig @@ -1,9 +1,13 @@ +CONFIG_ARM=y +CONFIG_ARCH_UNIPHIER=y +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_DM_I2C=y +CONFIG_MACH_PH1_LD4=y +CONFIG_PFC_MICRO_SUPPORT_CARD=y +CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -+S:CONFIG_ARM=y -+S:CONFIG_ARCH_UNIPHIER=y -+S:CONFIG_MACH_PH1_LD4=y -+S:CONFIG_DCC_MICRO_SUPPORT_CARD=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BDI=y CONFIG_CMD_CONSOLE=y @@ -28,15 +32,11 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_NFS=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y -CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref" -CONFIG_DM=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 -CONFIG_DM_SERIAL=y +CONFIG_SPL_NAND_DENALI=y CONFIG_UNIPHIER_SERIAL=y -CONFIG_DM_I2C=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -CONFIG_SPL_NAND_DENALI=y diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig index 12f069400f..202186245e 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/ph1_pro4_defconfig @@ -1,9 +1,13 @@ +CONFIG_ARM=y +CONFIG_ARCH_UNIPHIER=y +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_DM_I2C=y +CONFIG_MACH_PH1_PRO4=y +CONFIG_PFC_MICRO_SUPPORT_CARD=y +CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -+S:CONFIG_ARM=y -+S:CONFIG_ARCH_UNIPHIER=y -+S:CONFIG_MACH_PH1_PRO4=y -+S:CONFIG_DCC_MICRO_SUPPORT_CARD=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BDI=y CONFIG_CMD_CONSOLE=y @@ -28,15 +32,11 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_NFS=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y -CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref" -CONFIG_DM=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 -CONFIG_DM_SERIAL=y +CONFIG_SPL_NAND_DENALI=y CONFIG_UNIPHIER_SERIAL=y -CONFIG_DM_I2C=y CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_STORAGE=y -CONFIG_SPL_NAND_DENALI=y diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig index e66d166566..cf229aef25 100644 --- a/configs/ph1_sld8_defconfig +++ b/configs/ph1_sld8_defconfig @@ -1,9 +1,13 @@ +CONFIG_ARM=y +CONFIG_ARCH_UNIPHIER=y +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_DM_I2C=y +CONFIG_MACH_PH1_SLD8=y +CONFIG_PFC_MICRO_SUPPORT_CARD=y +CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -+S:CONFIG_ARM=y -+S:CONFIG_ARCH_UNIPHIER=y -+S:CONFIG_MACH_PH1_SLD8=y -+S:CONFIG_DCC_MICRO_SUPPORT_CARD=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BDI=y CONFIG_CMD_CONSOLE=y @@ -28,15 +32,11 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_NFS=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y -CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref" -CONFIG_DM=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 -CONFIG_DM_SERIAL=y +CONFIG_SPL_NAND_DENALI=y CONFIG_UNIPHIER_SERIAL=y -CONFIG_DM_I2C=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -CONFIG_SPL_NAND_DENALI=y diff --git a/configs/porter_defconfig b/configs/porter_defconfig new file mode 100644 index 0000000000..8d594d97df --- /dev/null +++ b/configs/porter_defconfig @@ -0,0 +1,6 @@ +CONFIG_ARM=y +CONFIG_RMOBILE=y +CONFIG_TARGET_PORTER=y +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_SH_SDHI=y diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 515ee3372b..23d4f5849c 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -1,3 +1,6 @@ CONFIG_ARM=y CONFIG_RMOBILE=y CONFIG_TARGET_SILK=y +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_SH_SDHI=y diff --git a/configs/xilinx_zynqmp_defconfig b/configs/xilinx_zynqmp_defconfig new file mode 100644 index 0000000000..8b6aa70c14 --- /dev/null +++ b/configs/xilinx_zynqmp_defconfig @@ -0,0 +1,14 @@ +CONFIG_ARM=y +CONFIG_TARGET_XILINX_ZYNQMP=y +CONFIG_CMD_BDI=y +CONFIG_CMD_BOOTD=y +CONFIG_CMD_RUN=y +CONFIG_CMD_IMI=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_ECHO=y +CONFIG_CMD_SOURCE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_MISC=y +CONFIG_CMD_TIMER=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp" diff --git a/doc/README.android-fastboot b/doc/README.android-fastboot index 167760968f..5526a4343c 100644 --- a/doc/README.android-fastboot +++ b/doc/README.android-fastboot @@ -6,9 +6,8 @@ Overview The protocol that is used over USB is described in README.android-fastboot-protocol in same directory. -The current implementation does not yet support the erase command or the -"oem format" command, and there is minimal support for the flash command; -it only supports eMMC devices. +The current implementation is a minimal support of the erase command,the +"oem format" command and flash command;it only supports eMMC devices. Client installation =================== diff --git a/doc/README.uniphier b/doc/README.uniphier index aaeb50c4e6..4902533544 100644 --- a/doc/README.uniphier +++ b/doc/README.uniphier @@ -73,7 +73,8 @@ Supported devices - UART (on-chip) - NAND - - USB (2.0) + - USB 2.0 (EHCI) + - USB 3.0 (xHCI) - LAN (on-board SMSC9118) - I2C - EEPROM (connected to the on-board I2C bus) diff --git a/doc/git-mailrc b/doc/git-mailrc index 8ba599cd9d..025c0b3cac 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -45,7 +45,7 @@ alias sjg Simon Glass <sjg@chromium.org> alias smcnutt Scott McNutt <smcnutt@psyent.com> alias sonic Sonic Zhang <sonic.adi@gmail.com> alias stroese Stefan Roese <sr@denx.de> -alias trini Tom Rini <trini@ti.com> +alias trini Tom Rini <trini@konsulko.com> alias vapier Mike Frysinger <vapier@gentoo.org> alias wd Wolfgang Denk <wd@denx.de> diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index ad0a7e7c25..0560afa9ff 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -55,6 +55,9 @@ int dfu_init_env_entities(char *interface, char *devstr) char *env_bkp; int ret; +#ifdef CONFIG_SET_DFU_ALT_INFO + set_dfu_alt_info(interface, devstr); +#endif str_env = getenv("dfu_alt_info"); if (!str_env) { error("\"dfu_alt_info\" env variable not defined!\n"); diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index aa11f15423..fe9a3b2396 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -8,6 +8,10 @@ ifndef CONFIG_SPL_BUILD obj-$(CONFIG_DM_GPIO) += gpio-uclass.o endif +/* TODO(sjg@chromium.org): Only tegra supports driver model in SPL */ +ifdef CONFIG_TEGRA_GPIO +obj-$(CONFIG_DM_GPIO) += gpio-uclass.o +endif obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 43928b8812..f870cdbddf 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -132,21 +132,6 @@ static void set_level(unsigned gpio, int high) writel(u, &bank->gpio_out[GPIO_PORT(gpio)]); } -/* set GPIO pin 'gpio' as an output, with polarity 'value' */ -int tegra_spl_gpio_direction_output(int gpio, int value) -{ - /* Configure as a GPIO */ - set_config(gpio, 1); - - /* Configure GPIO output value. */ - set_level(gpio, value); - - /* Configure GPIO direction as output. */ - set_direction(gpio, 1); - - return 0; -} - /* * Generic_GPIO primitives. */ @@ -338,12 +323,19 @@ static int gpio_tegra_bind(struct udevice *parent) int bank_count; int bank; int ret; - int len; /* If this is a child device, there is nothing to do here */ if (plat) return 0; + /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ +#ifdef CONFIG_SPL_BUILD + ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + bank_count = TEGRA_GPIO_BANKS; +#else + { + int len; + /* * This driver does not make use of interrupts, other than to figure * out the number of GPIO banks @@ -353,6 +345,8 @@ static int gpio_tegra_bind(struct udevice *parent) bank_count = len / 3 / sizeof(u32); ctlr = (struct gpio_ctlr *)fdtdec_get_addr(gd->fdt_blob, parent->of_offset, "reg"); + } +#endif for (bank = 0; bank < bank_count; bank++) { int port; @@ -388,4 +382,5 @@ U_BOOT_DRIVER(gpio_tegra) = { .probe = gpio_tegra_probe, .priv_auto_alloc_size = sizeof(struct tegra_port_info), .ops = &gpio_tegra_ops, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index eb00f1ca8a..03beab5a14 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -80,7 +80,7 @@ static inline int serial_in_shift(unsigned char *addr, int shift) #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) return in_be32(addr); #elif defined(CONFIG_SYS_BIG_ENDIAN) - return readb(addr + (1 << reg_shift) - 1); + return readb(addr + (1 << shift) - 1); #else return readb(addr); #endif diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 3641c9f834..8693c1ed14 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -69,7 +69,7 @@ sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate) if (port->clk_mode == EXT_CLK) { unsigned short dl = DL_VALUE(baudrate, clk); sci_out(port, DL, dl); - /* Need wait: Clock * 1/dl $B!_(B 1/16 */ + /* Need wait: Clock * 1/dl * 1/16 */ udelay((1000000 * dl * 16 / clk) * 1000 + 1); } else { sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk)); diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 528aa7351d..941e6eda4c 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -227,7 +227,8 @@ struct uart_port { #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) # define SCIF_ORER 0x0001 -# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ +# define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30) + /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ #else # error CPU subtype not defined #endif @@ -742,7 +743,7 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk) #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ -#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */ +#define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ #else /* Generic SH */ #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c index e8a1608b99..a6bd27facf 100644 --- a/drivers/serial/serial_uniphier.c +++ b/drivers/serial/serial_uniphier.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012-2014 Panasonic Corporation + * Copyright (C) 2012-2015 Panasonic Corporation * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -13,31 +13,25 @@ #include <serial.h> #include <fdtdec.h> -#define UART_REG(x) \ - u8 x; \ - u8 postpad_##x[3]; - /* * Note: Register map is slightly different from that of 16550. */ struct uniphier_serial { - UART_REG(rbr); /* 0x00 */ - UART_REG(ier); /* 0x04 */ - UART_REG(iir); /* 0x08 */ - UART_REG(fcr); /* 0x0c */ - u8 mcr; /* 0x10 */ - u8 lcr; - u16 __postpad; - UART_REG(lsr); /* 0x14 */ - UART_REG(msr); /* 0x18 */ - u32 __none1; - u32 __none2; - u16 dlr; - u16 __postpad2; + u32 rx; /* In: Receive buffer */ +#define tx rx /* Out: Transmit buffer */ + u32 ier; /* Interrupt Enable Register */ + u32 iir; /* In: Interrupt ID Register */ + u32 char_fcr; /* Charactor / FIFO Control Register */ + u32 lcr_mcr; /* Line/Modem Control Register */ +#define LCR_SHIFT 8 +#define LCR_MASK (0xff << (LCR_SHIFT)) + u32 lsr; /* In: Line Status Register */ + u32 msr; /* In: Modem Status Register */ + u32 __rsv0; + u32 __rsv1; + u32 dlr; /* Divisor Latch Register */ }; -#define thr rbr - struct uniphier_serial_private_data { struct uniphier_serial __iomem *membase; }; @@ -52,11 +46,9 @@ static int uniphier_serial_setbrg(struct udevice *dev, int baudrate) const unsigned int mode_x_div = 16; unsigned int divisor; - writeb(UART_LCR_WLEN8, &port->lcr); - divisor = DIV_ROUND_CLOSEST(plat->uartclk, mode_x_div * baudrate); - writew(divisor, &port->dlr); + writel(divisor, &port->dlr); return 0; } @@ -65,20 +57,20 @@ static int uniphier_serial_getc(struct udevice *dev) { struct uniphier_serial __iomem *port = uniphier_serial_port(dev); - if (!(readb(&port->lsr) & UART_LSR_DR)) + if (!(readl(&port->lsr) & UART_LSR_DR)) return -EAGAIN; - return readb(&port->rbr); + return readl(&port->rx); } static int uniphier_serial_putc(struct udevice *dev, const char c) { struct uniphier_serial __iomem *port = uniphier_serial_port(dev); - if (!(readb(&port->lsr) & UART_LSR_THRE)) + if (!(readl(&port->lsr) & UART_LSR_THRE)) return -EAGAIN; - writeb(c, &port->thr); + writel(c, &port->tx); return 0; } @@ -88,21 +80,29 @@ static int uniphier_serial_pending(struct udevice *dev, bool input) struct uniphier_serial __iomem *port = uniphier_serial_port(dev); if (input) - return readb(&port->lsr) & UART_LSR_DR; + return readl(&port->lsr) & UART_LSR_DR; else - return !(readb(&port->lsr) & UART_LSR_THRE); + return !(readl(&port->lsr) & UART_LSR_THRE); } static int uniphier_serial_probe(struct udevice *dev) { + u32 tmp; struct uniphier_serial_private_data *priv = dev_get_priv(dev); struct uniphier_serial_platform_data *plat = dev_get_platdata(dev); + struct uniphier_serial __iomem *port; - priv->membase = map_sysmem(plat->base, sizeof(struct uniphier_serial)); - - if (!priv->membase) + port = map_sysmem(plat->base, sizeof(struct uniphier_serial)); + if (!port) return -ENOMEM; + priv->membase = port; + + tmp = readl(&port->lcr_mcr); + tmp &= ~LCR_MASK; + tmp |= UART_LCR_WLEN8 << LCR_SHIFT; + writel(tmp, &port->lcr_mcr); + return 0; } diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 310175acfe..751ec9e010 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -55,6 +55,7 @@ static inline struct f_fastboot *func_to_fastboot(struct usb_function *f) static struct f_fastboot *fastboot_func; static unsigned int download_size; static unsigned int download_bytes; +static bool is_high_speed; static struct usb_endpoint_descriptor fs_ep_in = { .bLength = USB_DT_ENDPOINT_SIZE, @@ -136,6 +137,7 @@ static int fastboot_bind(struct usb_configuration *c, struct usb_function *f) int id; struct usb_gadget *gadget = c->cdev->gadget; struct f_fastboot *f_fb = func_to_fastboot(f); + const char *s; /* DYNAMIC interface numbers assignments */ id = usb_interface_id(c, f); @@ -161,6 +163,10 @@ static int fastboot_bind(struct usb_configuration *c, struct usb_function *f) hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress; + s = getenv("serial#"); + if (s) + g_dnl_set_serialnumber((char *)s); + return 0; } @@ -219,10 +225,13 @@ static int fastboot_set_alt(struct usb_function *f, __func__, f->name, interface, alt); /* make sure we don't enable the ep twice */ - if (gadget->speed == USB_SPEED_HIGH) + if (gadget->speed == USB_SPEED_HIGH) { ret = usb_ep_enable(f_fb->out_ep, &hs_ep_out); - else + is_high_speed = true; + } else { ret = usb_ep_enable(f_fb->out_ep, &fs_ep_out); + is_high_speed = false; + } if (ret) { puts("failed to enable out ep\n"); return ret; @@ -370,13 +379,20 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) fastboot_tx_write_str(response); } -static unsigned int rx_bytes_expected(void) +static unsigned int rx_bytes_expected(unsigned int maxpacket) { int rx_remain = download_size - download_bytes; + int rem = 0; if (rx_remain < 0) return 0; if (rx_remain > EP_BUFFER_SIZE) return EP_BUFFER_SIZE; + if (rx_remain < maxpacket) { + rx_remain = maxpacket; + } else if (rx_remain % maxpacket != 0) { + rem = rx_remain % maxpacket; + rx_remain = rx_remain + (maxpacket - rem); + } return rx_remain; } @@ -388,6 +404,7 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) const unsigned char *buffer = req->buf; unsigned int buffer_size = req->actual; unsigned int pre_dot_num, now_dot_num; + unsigned int max; if (req->status != 0) { printf("Bad status: %d\n", req->status); @@ -425,7 +442,9 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) printf("\ndownloading of %d bytes finished\n", download_bytes); } else { - req->length = rx_bytes_expected(); + max = is_high_speed ? hs_ep_out.wMaxPacketSize : + fs_ep_out.wMaxPacketSize; + req->length = rx_bytes_expected(max); if (req->length < ep->maxpacket) req->length = ep->maxpacket; } @@ -438,6 +457,7 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req) { char *cmd = req->buf; char response[RESPONSE_LEN]; + unsigned int max; strsep(&cmd, ":"); download_size = simple_strtoul(cmd, NULL, 16); @@ -453,7 +473,9 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req) } else { sprintf(response, "DATA%08x", download_size); req->complete = rx_handler_dl_image; - req->length = rx_bytes_expected(); + max = is_high_speed ? hs_ep_out.wMaxPacketSize : + fs_ep_out.wMaxPacketSize; + req->length = rx_bytes_expected(max); if (req->length < ep->maxpacket) req->length = ep->maxpacket; } @@ -513,6 +535,50 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req) } #endif +static void cb_oem(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; +#ifdef CONFIG_FASTBOOT_FLASH + if (strncmp("format", cmd + 4, 6) == 0) { + char cmdbuf[32]; + sprintf(cmdbuf, "gpt write mmc %x $partitions", + CONFIG_FASTBOOT_FLASH_MMC_DEV); + if (run_command(cmdbuf, 0)) + fastboot_tx_write_str("FAIL"); + else + fastboot_tx_write_str("OKAY"); + } else +#endif + if (strncmp("unlock", cmd + 4, 8) == 0) { + fastboot_tx_write_str("FAILnot implemented"); + } + else { + fastboot_tx_write_str("FAILunknown oem command"); + } +} + +#ifdef CONFIG_FASTBOOT_FLASH +static void cb_erase(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; + char response[RESPONSE_LEN]; + + strsep(&cmd, ":"); + if (!cmd) { + error("missing partition name"); + fastboot_tx_write_str("FAILmissing partition name"); + return; + } + + strcpy(response, "FAILno flash device defined"); + +#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV + fb_mmc_erase(cmd, response); +#endif + fastboot_tx_write_str(response); +} +#endif + struct cmd_dispatch_info { char *cmd; void (*cb)(struct usb_ep *ep, struct usb_request *req); @@ -539,8 +605,15 @@ static const struct cmd_dispatch_info cmd_dispatch_info[] = { { .cmd = "flash", .cb = cb_flash, + }, { + .cmd = "erase", + .cb = cb_erase, }, #endif + { + .cmd = "oem", + .cb = cb_oem, + }, }; static void rx_handler_command(struct usb_ep *ep, struct usb_request *req) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 30d1457638..24a595fb42 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -17,6 +17,14 @@ config USB_XHCI if USB_XHCI_HCD +config USB_XHCI_UNIPHIER + bool "Support for Panasonic UniPhier on-chip xHCI USB controller" + depends on ARCH_UNIPHIER + default y + ---help--- + Enables support for the on-chip xHCI controller on Panasonic + UniPhier SoCs. + endif config USB_EHCI_HCD @@ -47,7 +55,7 @@ if USB_EHCI_HCD config USB_EHCI_UNIPHIER bool "Support for Panasonic UniPhier on-chip EHCI USB controller" - depends on ARCH_UNIPHIER + depends on ARCH_UNIPHIER && OF_CONTROL default y ---help--- Enables support for the on-chip EHCI controller on Panasonic diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 66d6e9a6d2..eb6f34b53c 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o +obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o # designware obj-$(CONFIG_USB_DWC2) += dwc2.o diff --git a/drivers/usb/host/ehci-uniphier.c b/drivers/usb/host/ehci-uniphier.c index 32a4375279..b5ec296918 100644 --- a/drivers/usb/host/ehci-uniphier.c +++ b/drivers/usb/host/ehci-uniphier.c @@ -7,12 +7,12 @@ #include <common.h> #include <linux/err.h> +#include <asm/io.h> #include <usb.h> -#include <asm/arch/ehci-uniphier.h> +#include <mach/mio-regs.h> +#include <fdtdec.h> #include "ehci.h" -#ifdef CONFIG_OF_CONTROL -#include <fdtdec.h> DECLARE_GLOBAL_DATA_PTR; #define FDT gd->fdt_blob @@ -35,18 +35,19 @@ static int get_uniphier_ehci_base(int index, struct ehci_hccr **base) return -ENODEV; /* not found */ } -#else -static int get_uniphier_ehci_base(int index, struct ehci_hccr **base) + +static void uniphier_ehci_reset(int index, int on) { - *base = (struct ehci_hccr *)uniphier_ehci_platdata[index].base; - return 0; + u32 tmp; + + tmp = readl(MIO_USB_RSTCTRL(index)); + if (on) + tmp &= ~MIO_USB_RSTCTRL_XRST; + else + tmp |= MIO_USB_RSTCTRL_XRST; + writel(tmp, MIO_USB_RSTCTRL(index)); } -#endif -/* - * Create the appropriate control structures to manage - * a new EHCI host controller. - */ int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c index a77c8bc919..3f86fdca89 100644 --- a/drivers/usb/host/xhci-exynos5.c +++ b/drivers/usb/host/xhci-exynos5.c @@ -182,7 +182,7 @@ static void exynos5_usb3_phy_exit(struct exynos_usb3_phy *phy) set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE); } -void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) +static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) { clrsetbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), diff --git a/drivers/usb/host/xhci-uniphier.c b/drivers/usb/host/xhci-uniphier.c new file mode 100644 index 0000000000..08b15e0ad1 --- /dev/null +++ b/drivers/usb/host/xhci-uniphier.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/err.h> +#include <usb.h> +#include <fdtdec.h> +#include "xhci.h" + +static int get_uniphier_xhci_base(int index, struct xhci_hccr **base) +{ + DECLARE_GLOBAL_DATA_PTR; + int node_list[2]; + fdt_addr_t addr; + int count; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "usb", + COMPAT_PANASONIC_XHCI, node_list, + ARRAY_SIZE(node_list)); + + if (index >= count) + return -ENODEV; + + addr = fdtdec_get_addr(gd->fdt_blob, node_list[index], "reg"); + if (addr == FDT_ADDR_T_NONE) + return -ENODEV; + + *base = (struct xhci_hccr *)addr; + + return 0; +} + +#define USB3_RST_CTRL 0x00100040 +#define IOMMU_RST_N (1 << 5) +#define LINK_RST_N (1 << 4) + +static void uniphier_xhci_reset(void __iomem *base, int on) +{ + u32 tmp; + + tmp = readl(base + USB3_RST_CTRL); + + if (on) + tmp &= ~(IOMMU_RST_N | LINK_RST_N); + else + tmp |= IOMMU_RST_N | LINK_RST_N; + + writel(tmp, base + USB3_RST_CTRL); +} + +int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) +{ + int ret; + struct xhci_hccr *cr; + struct xhci_hcor *or; + + ret = get_uniphier_xhci_base(index, &cr); + if (ret < 0) + return ret; + + uniphier_xhci_reset(cr, 0); + + or = (void *)cr + HC_LENGTH(xhci_readl(&cr->cr_capbase)); + + *hccr = cr; + *hcor = or; + + return 0; +} + +void xhci_hcd_stop(int index) +{ + int ret; + struct xhci_hccr *cr; + + ret = get_uniphier_xhci_base(index, &cr); + if (ret < 0) + return; + + uniphier_xhci_reset(cr, 1); +} diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c index 98f4830912..31a280edba 100644 --- a/drivers/usb/musb-new/omap2430.c +++ b/drivers/usb/musb-new/omap2430.c @@ -321,6 +321,7 @@ static int omap2430_musb_init(struct musb *musb) { u32 l; int status = 0; + unsigned long int start; #ifndef __UBOOT__ struct device *dev = musb->controller; struct omap2430_glue *glue = dev_get_drvdata(dev->parent); @@ -331,6 +332,21 @@ static int omap2430_musb_init(struct musb *musb) (struct omap_musb_board_data *)musb->controller; #endif + /* Reset the controller */ + musb_writel(musb->mregs, OTG_SYSCONFIG, SOFTRST); + + start = get_timer(0); + + while (1) { + l = musb_readl(musb->mregs, OTG_SYSCONFIG); + if ((l & SOFTRST) == 0) + break; + + if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { + dev_err(musb->controller, "MUSB reset is taking too long\n"); + return -ENODEV; + } + } #ifndef __UBOOT__ /* We require some kind of external transceiver, hooked diff --git a/include/_exports.h b/include/_exports.h index 594470328e..279017e87f 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -23,7 +23,9 @@ EXPORT_FUNC(dummy, void, free_hdlr, void) #endif EXPORT_FUNC(malloc, void *, malloc, size_t) +#ifndef CONFIG_SYS_MALLOC_SIMPLE EXPORT_FUNC(free, void, free, void *) +#endif EXPORT_FUNC(udelay, void, udelay, unsigned long) EXPORT_FUNC(get_timer, unsigned long, get_timer, unsigned long) EXPORT_FUNC(vprintf, int, vprintf, const char *, va_list) diff --git a/include/configs/alt.h b/include/configs/alt.h index 58eac31358..e9ffa4866b 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -38,8 +38,6 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE -#define CONFIG_CONS_SCIF2 -#define CONFIG_SCIF_USE_EXT_CLK /* FLASH */ #define CONFIG_SPI @@ -70,7 +68,6 @@ #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) -#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ #define CONFIG_SYS_TMU_CLK_DIV 4 @@ -114,4 +111,7 @@ /* SCIF2 */ #define CONFIG_SMSTP7_ENA 0x00080000 +/* SDHI */ +#define CONFIG_SH_SDHI_FREQ 97500000 + #endif /* __ALT_H */ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 09ee10c059..290a6a3e06 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -297,7 +297,6 @@ #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_TEXT_BASE 0x40200800 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 190ef0e71b..3de5079962 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -306,7 +306,6 @@ #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_TEXT_BASE 0x40200800 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h index 35eae76930..eaed7eaa20 100644 --- a/include/configs/atngw100mkii.h +++ b/include/configs/atngw100mkii.h @@ -16,6 +16,10 @@ #define CONFIG_AT32AP7000 #define CONFIG_ATNGW100MKII +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R + /* * Set up the PLL to run at 140 MHz, the CPU to run at the PLL * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h index 2f5a6609b8..848a15832f 100644 --- a/include/configs/balloon3.h +++ b/include/configs/balloon3.h @@ -13,7 +13,7 @@ * High Level Board Configuration Options */ #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ -#define CONFIG_BALLOON3 1 /* Balloon3 board */ +#define CONFIG_BALLOON3 1 /* Balloon3 board */ /* * Environment settings @@ -84,18 +84,17 @@ /* * Clock Configuration */ -#undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ /* * DRAM Map */ -#define CONFIG_NR_DRAM_BANKS 3 /* 2 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 3 /* 3 banks of DRAM */ #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ #define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */ #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ -#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #3 */ #define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */ #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ @@ -135,7 +134,7 @@ #define CONFIG_ENV_IS_IN_FLASH #else #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_NOWHERE #endif #define CONFIG_SYS_MONITOR_BASE 0x000000 @@ -191,7 +190,6 @@ #define CONFIG_SYS_MDMRS_VAL 0x00220022 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 #define CONFIG_SYS_SXCNFG_VAL 0x00000000 -#define CONFIG_SYS_MEM_BUF_IMP 0x0f /* * PCMCIA and CF Interfaces diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index e9d5d01620..49afe46e2a 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -175,7 +175,6 @@ * * ---------------------------------------------------------------------------- */ -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #undef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x80800000 #define CONFIG_SPL_BSS_START_ADDR 0x80A00000 diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index b2a9f35797..9feca1b47b 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -365,7 +365,6 @@ #define CONFIG_SPL_TEXT_BASE 0x40200800 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK /* * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 08bd276b44..7fc364e838 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -2,18 +2,22 @@ * Toradex Colibri PXA270 configuration file * * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com> * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_H +#define __CONFIG_H /* * High Level Board Configuration Options */ #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_TEXT_BASE 0x0 +/* Avoid overwriting factory configuration block */ +#define CONFIG_BOARD_SIZE_LIMIT 0x40000 /* * Environment settings @@ -22,13 +26,13 @@ #define CONFIG_SYS_MALLOC_LEN (128 * 1024) #define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ - "if mmc init && fatload mmc 0 0xa0000000 uImage; then " \ + "if fatload mmc 0 0xa0000000 uImage; then " \ "bootm 0xa0000000; " \ "fi; " \ "if usb reset && fatload usb 0 0xa0000000 uImage; then " \ "bootm 0xa0000000; " \ "fi; " \ - "bootm 0x80000;" + "bootm 0xc0000;" #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" #define CONFIG_TIMESTAMP #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ @@ -50,6 +54,8 @@ */ #include <config_cmd_default.h> +#undef CONFIG_CMD_LOADB /* Both together */ +#undef CONFIG_CMD_LOADS /* saves 10 KB */ #define CONFIG_CMD_NET #define CONFIG_CMD_ENV #undef CONFIG_CMD_IMLS @@ -59,7 +65,6 @@ /* * Networking Configuration - * chip on the Voipac PXA270 board */ #ifdef CONFIG_CMD_NET #define CONFIG_CMD_PING @@ -82,7 +87,7 @@ */ #define CONFIG_SYS_HUSH_PARSER 1 -#define CONFIG_SYS_LONGHELP +#undef CONFIG_SYS_LONGHELP /* Saves 10 KB */ #ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "$ " #else @@ -96,7 +101,6 @@ #define CONFIG_CMDLINE_EDITING 1 #define CONFIG_AUTO_COMPLETE 1 - /* * Clock Configuration */ @@ -142,25 +146,24 @@ #else /* No flash */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_NOWHERE #endif #define CONFIG_SYS_MONITOR_BASE 0x0 -#define CONFIG_SYS_MONITOR_LEN 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x40000 +/* Skip factory configuration block */ #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000) #define CONFIG_ENV_SIZE 0x40000 #define CONFIG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) /* * GPIO settings */ #define CONFIG_SYS_GPSR0_VAL 0x00000000 #define CONFIG_SYS_GPSR1_VAL 0x00020000 -#define CONFIG_SYS_GPSR2_VAL 0x0002C000 +#define CONFIG_SYS_GPSR2_VAL 0x0002c000 #define CONFIG_SYS_GPSR3_VAL 0x00000000 #define CONFIG_SYS_GPCR0_VAL 0x00000000 @@ -168,19 +171,19 @@ #define CONFIG_SYS_GPCR2_VAL 0x00000000 #define CONFIG_SYS_GPCR3_VAL 0x00000000 -#define CONFIG_SYS_GPDR0_VAL 0x08000000 -#define CONFIG_SYS_GPDR1_VAL 0x0002A981 -#define CONFIG_SYS_GPDR2_VAL 0x0202FC00 -#define CONFIG_SYS_GPDR3_VAL 0x00000000 +#define CONFIG_SYS_GPDR0_VAL 0xc8008000 +#define CONFIG_SYS_GPDR1_VAL 0xfc02a981 +#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff +#define CONFIG_SYS_GPDR3_VAL 0x0061e804 -#define CONFIG_SYS_GAFR0_L_VAL 0x00100000 -#define CONFIG_SYS_GAFR0_U_VAL 0x00C00010 -#define CONFIG_SYS_GAFR1_L_VAL 0x999A901A -#define CONFIG_SYS_GAFR1_U_VAL 0xAAA00008 -#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA -#define CONFIG_SYS_GAFR2_U_VAL 0x0109A000 -#define CONFIG_SYS_GAFR3_L_VAL 0x54000300 -#define CONFIG_SYS_GAFR3_U_VAL 0x00024001 +#define CONFIG_SYS_GAFR0_L_VAL 0x80100000 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010 +#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008 +#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002 +#define CONFIG_SYS_GAFR3_L_VAL 0x54000310 +#define CONFIG_SYS_GAFR3_U_VAL 0x00005401 #define CONFIG_SYS_PSSR_VAL 0x30 @@ -193,26 +196,26 @@ /* * Memory settings */ -#define CONFIG_SYS_MSC0_VAL 0x000095f2 -#define CONFIG_SYS_MSC1_VAL 0x00007ff4 -#define CONFIG_SYS_MSC2_VAL 0x00000000 -#define CONFIG_SYS_MDCNFG_VAL 0x08000ac9 -#define CONFIG_SYS_MDREFR_VAL 0x2013e01e -#define CONFIG_SYS_MDMRS_VAL 0x00320032 -#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2 +#define CONFIG_SYS_MSC1_VAL 0x9ee1f994 +#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1 +#define CONFIG_SYS_MDCNFG_VAL 0x090009c9 +#define CONFIG_SYS_MDREFR_VAL 0x2003a031 +#define CONFIG_SYS_MDMRS_VAL 0x00220022 +#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 #define CONFIG_SYS_SXCNFG_VAL 0x40044004 /* * PCMCIA and CF Interfaces */ -#define CONFIG_SYS_MECR_VAL 0x00000001 -#define CONFIG_SYS_MCMEM0_VAL 0x00014307 +#define CONFIG_SYS_MECR_VAL 0x00000000 +#define CONFIG_SYS_MCMEM0_VAL 0x00028307 #define CONFIG_SYS_MCMEM1_VAL 0x00014307 -#define CONFIG_SYS_MCATT0_VAL 0x0001c787 +#define CONFIG_SYS_MCATT0_VAL 0x00038787 #define CONFIG_SYS_MCATT1_VAL 0x0001c787 -#define CONFIG_SYS_MCIO0_VAL 0x0001430f +#define CONFIG_SYS_MCIO0_VAL 0x0002830f #define CONFIG_SYS_MCIO1_VAL 0x0001430f #include "pxa-common.h" -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 1c69551d16..84b047e53f 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -213,8 +213,6 @@ #undef CONFIG_SPL_TEXT_BASE #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ -#undef CONFIG_SPL_STACK -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK /* NAND boot config */ #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index fe72bd0d3b..b42dab7a7f 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -38,4 +38,20 @@ #define CONFIG_BOARD_REV_GPIO_COUNT 2 +#define CONFIG_PHY_IRAM_BASE 0x02020000 + +/* Address for relocating helper code (Last 4 KB of IRAM) */ +#define CONFIG_EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000) + +/* + * Low Power settings + */ +#define CONFIG_LOWPOWER_FLAG 0x02020028 +#define CONFIG_LOWPOWER_ADDR 0x0202002C + +/* + * Number of CPUs available + */ +#define CONFIG_CORE_COUNT 0x8 + #endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/flea3.h b/include/configs/flea3.h index bf02829cde..edff0f54cf 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -124,8 +124,6 @@ #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x10000 -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* diff --git a/include/configs/gose.h b/include/configs/gose.h index 44c8a3053a..0dc28c7ece 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -39,8 +39,6 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE -#define CONFIG_CONS_SCIF0 -#define CONFIG_SCIF_USE_EXT_CLK /* FLASH */ #define CONFIG_SYS_NO_FLASH @@ -68,7 +66,6 @@ #define RMOBILE_XTAL_CLK 20000000u #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) -#define CONFIG_SH_SCIF_CLK_FREQ 14745600 #define CONFIG_SYS_TMU_CLK_DIV 4 /* I2C */ @@ -101,4 +98,10 @@ /* SCIF0 */ #define CONFIG_SMSTP7_ENA 0x00200000 +/* SDHI */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SH_SDHI_FREQ 97500000 + #endif /* __GOSE_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index c14889ce30..1dffab1374 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -39,8 +39,6 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE -#define CONFIG_CONS_SCIF0 -#define CONFIG_SCIF_USE_EXT_CLK /* FLASH */ #define CONFIG_SYS_NO_FLASH @@ -68,7 +66,6 @@ #define RMOBILE_XTAL_CLK 20000000u #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) -#define CONFIG_SH_SCIF_CLK_FREQ 14745600 #define CONFIG_SYS_TMU_CLK_DIV 4 /* i2c */ @@ -92,7 +89,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USB_STORAGE - /* Module stop status bits */ /* INTC-RT */ #define CONFIG_SMSTP0_ENA 0x00400000 @@ -103,4 +99,10 @@ /* SCIF0 */ #define CONFIG_SMSTP7_ENA 0x00200000 +/* SD */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SH_SDHI_FREQ 97500000 + #endif /* __KOELSCH_H */ diff --git a/include/configs/lager.h b/include/configs/lager.h index 291267f0f0..e830c6df0a 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -39,8 +39,6 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE -#define CONFIG_CONS_SCIF0 -#define CONFIG_SCIF_USE_EXT_CLK /* SPI */ #define CONFIG_SPI @@ -83,7 +81,6 @@ #define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) #define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) #define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) -#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ #define CONFIG_SYS_TMU_CLK_DIV 4 @@ -112,4 +109,7 @@ /* SCIF0 */ #define CONFIG_SMSTP7_ENA 0x00200000 +/* SDHI */ +#define CONFIG_SH_SDHI_FREQ 97500000 + #endif /* __LAGER_H */ diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index a145f0812f..603d17cef6 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -146,8 +146,6 @@ #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x10000 -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 8b47537614..5ee0abe02a 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -29,6 +29,9 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +/* Reserve the last 1 MiB for the secure firmware */ +#define CONFIG_SYS_MEM_TOP_HIDE (1UL << 20UL) +#define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE @@ -56,8 +59,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MEM_TOP_HIDE (SZ_1M) /* ram console */ - #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_ENV_IS_IN_MMC diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 9fa86603f6..c395020919 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -25,13 +25,11 @@ #define CONFIG_CMD_MMC -/* - * FIXME: The number of bank is actually 8. But there is no way to reserve the - * last 16 Mib in the last bank now. So I just excluded the last bank - * temporally. - */ -#define CONFIG_NR_DRAM_BANKS 7 +#define CONFIG_NR_DRAM_BANKS 8 #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ +/* Reserve the last 22 MiB for the secure firmware */ +#define CONFIG_SYS_MEM_TOP_HIDE (22UL << 20UL) +#define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE #define CONFIG_ENV_IS_IN_MMC diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 8885e17581..e7df15400d 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -259,7 +259,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x40200800 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ diff --git a/include/configs/palmld.h b/include/configs/palmld.h index 9480d8daf2..7dbc9aee3a 100644 --- a/include/configs/palmld.h +++ b/include/configs/palmld.h @@ -114,7 +114,6 @@ /* * Clock Configuration */ -#undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ /* diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h index 8abce1b425..75506b22f3 100644 --- a/include/configs/palmtc.h +++ b/include/configs/palmtc.h @@ -116,7 +116,6 @@ /* * Clock Configuration */ -#undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */ /* diff --git a/include/configs/palmtreo680.h b/include/configs/palmtreo680.h index 6490be5504..bd0f44b0d8 100644 --- a/include/configs/palmtreo680.h +++ b/include/configs/palmtreo680.h @@ -117,7 +117,6 @@ /* * Clock Configuration */ -#undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ /* diff --git a/include/configs/porter.h b/include/configs/porter.h new file mode 100644 index 0000000000..9703c840b7 --- /dev/null +++ b/include/configs/porter.h @@ -0,0 +1,112 @@ +/* + * include/configs/porter.h + * This file is Porter board configuration. + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __PORTER_H +#define __PORTER_H + +#undef DEBUG +#define CONFIG_R8A7791 +#define CONFIG_RMOBILE_BOARD_STRING "Porter" + +#include "rcar-gen2-common.h" + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x70000000 +#else +#define CONFIG_SYS_TEXT_BASE 0xE6304000 +#endif + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC +#else +#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC +#endif +#define STACK_AREA_SIZE 0xC000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE + +/* FLASH */ +#define CONFIG_SPI +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SH_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_QUAD +#define CONFIG_SYS_NO_FLASH + +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) +#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) +#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) + +#define CONFIG_SYS_TMU_CLK_DIV 4 + +/* i2c */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 +#define CONFIG_SYS_I2C_SH_SPEED0 400000 +#define CONFIG_SYS_I2C_SH_SPEED1 400000 +#define CONFIG_SYS_I2C_SH_SPEED2 400000 +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 10000000 + +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + +/* USB */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_RMOBILE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_STORAGE + +/* SD */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SH_SDHI_FREQ 97500000 + +/* Module stop status bits */ +/* INTC-RT */ +#define CONFIG_SMSTP0_ENA 0x00400000 +/* MSIF */ +#define CONFIG_SMSTP2_ENA 0x00002000 +/* INTC-SYS, IRQC */ +#define CONFIG_SMSTP4_ENA 0x00000180 +/* SCIF0 */ +#define CONFIG_SMSTP7_ENA 0x00200000 + +#endif /* __PORTER_H */ diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index c33f1cb880..e9ef7cc980 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -35,6 +35,8 @@ #define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) + /* Support File sytems */ #define CONFIG_FAT_WRITE #define CONFIG_DOS_PARTITION diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 21e13e5473..c7affd6f3a 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -142,7 +142,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x402F0400 #define CONFIG_SPL_MAX_SIZE (101 * 1024) -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ diff --git a/include/configs/silk.h b/include/configs/silk.h index a4235e94d0..161e0a5e26 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -39,8 +39,6 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE -#define CONFIG_CONS_SCIF2 -#define CONFIG_SCIF_USE_EXT_CLK /* FLASH */ #define CONFIG_SPI @@ -71,7 +69,6 @@ #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) -#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ #define CONFIG_SYS_TMU_CLK_DIV 4 @@ -104,6 +101,9 @@ #define CONFIG_SH_MMCIF_ADDR 0xee200000 #define CONFIG_SH_MMCIF_CLK 48000000 +/* SDHI */ +#define CONFIG_SH_SDHI_FREQ 97500000 + /* Module stop status bits */ /* INTC-RT */ #define CONFIG_SMSTP0_ENA 0x00400000 diff --git a/include/configs/snowball.h b/include/configs/snowball.h index dacb5604cd..126201cf96 100644 --- a/include/configs/snowball.h +++ b/include/configs/snowball.h @@ -175,7 +175,6 @@ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 9fbe68a8a2..38288f69aa 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -237,7 +237,6 @@ #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 7d2c0d2fa7..dd69d4ebab 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -346,7 +346,6 @@ #define CONFIG_SPL_TEXT_BASE 0x40200800 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK /* * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 005fc6aeb3..fa6ccc16ee 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -43,13 +43,7 @@ /* * NS16550 Configuration */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#else #define CONFIG_TEGRA_SERIAL -#endif #define CONFIG_SYS_NS16550 /* diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index deb6bb2b8f..dcc2bdc7f6 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -171,7 +171,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x40300000 #define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024) -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 87a4efcd5a..27a3dd1366 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -58,7 +58,6 @@ + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */ -#undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ #define CONFIG_CMD_ASKEN @@ -137,7 +136,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x40400000 #define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024) -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 2bd116477c..c0c1060216 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -213,10 +213,9 @@ * SPLs). We have our BSS be placed 2MiB after this, to allow for the * default Linux kernel address of 0x80008000 to work with most sized * kernels, in the Falcon Mode case. We have the SPL malloc pool at the - * end of the BSS area. We place our stack at 32MiB after the start of - * DRAM to allow room for all of the above. + * end of the BSS area. We suggest that the stack be placed at 32MiB after + * the start of DRAM to allow room for all of the above (handled in Kconfig). */ -#define CONFIG_SPL_STACK (CONFIG_SYS_SDRAM_BASE + (32 << 20)) #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x80800000 #endif diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 36621a553c..10ac4a46bc 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -354,7 +354,6 @@ #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ #define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 diff --git a/include/configs/u8500_href.h b/include/configs/u8500_href.h index 8d7970a376..5302b1fb81 100644 --- a/include/configs/u8500_href.h +++ b/include/configs/u8500_href.h @@ -131,7 +131,6 @@ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ #define CONFIG_SYS_LOADS_BAUD_CHANGE diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 3f738fb642..df89d14cc3 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -88,6 +88,8 @@ /* #define CONFIG_SYS_ICACHE_OFF */ /* #define CONFIG_SYS_DCACHE_OFF */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* Comment out the following to enable L2 cache */ #define CONFIG_UNIPHIER_L2CACHE_ON @@ -186,6 +188,7 @@ /* USB */ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 #define CONFIG_CMD_FAT #define CONFIG_FAT_WRITE #define CONFIG_DOS_PARTITION diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 2dea921045..989e755279 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -188,7 +188,6 @@ #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 /* Miscellaneous configurable options */ -#undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000) #define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000) #define CONFIG_BOOTDELAY 2 diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 2fb91a8f8c..887433b16f 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -221,7 +221,7 @@ #else /* No flash */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_NOWHERE #endif /* @@ -297,7 +297,6 @@ #define CONFIG_SYS_MDMRS_VAL 0x00000000 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 #define CONFIG_SYS_SXCNFG_VAL 0x40044004 -#define CONFIG_SYS_MEM_BUF_IMP 0x0f /* * PCMCIA and CF Interfaces diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index c7a17f7a49..8e1c7a44cc 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -146,8 +146,6 @@ #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x10000 -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h new file mode 100644 index 0000000000..511ecca0b8 --- /dev/null +++ b/include/configs/xilinx_zynqmp.h @@ -0,0 +1,131 @@ +/* + * Configuration for Xilinx ZynqMP + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * + * Based on Configuration for Versatile Express + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __XILINX_ZYNQMP_H +#define __XILINX_ZYNQMP_H + +#define CONFIG_REMAKE_ELF + +/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_GENERIC_BOARD + +/* Generic Interrupt Controller Definitions */ +#define CONFIG_GICV2 +#define GICD_BASE 0xF9010000 +#define GICC_BASE 0xF9020000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE + +/* Have release address at the end of 256MB for now */ +#define CPU_RELEASE_ADDR 0xFFFFFF0 + +/* Cache Definitions */ +#define CONFIG_SYS_DCACHE_OFF + +#define CONFIG_IDENT_STRING " Xilinx ZynqMP" + +#define CONFIG_SYS_TEXT_BASE 0x8000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT + +/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ +#define COUNTER_FREQUENCY 4000000 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x400000) + +/* Serial setup */ +#define CONFIG_ZYNQ_SERIAL_UART0 +#define CONFIG_ZYNQ_SERIAL + +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE \ + { 4800, 9600, 19200, 38400, 57600, 115200 } + +/* Command line configuration */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_MEMORY +#define CONFIG_DOS_PARTITION + +#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) +# define CONFIG_MMC +# define CONFIG_GENERIC_MMC +# define CONFIG_SDHCI +# define CONFIG_ZYNQ_SDHCI +# define CONFIG_CMD_MMC +#endif + +#if defined(CONFIG_ZYNQ_SDHCI) +# define CONFIG_FAT_WRITE +# define CONFIG_CMD_EXT4_WRITE +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR 0x8000000 + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=0x80000\0" \ + "fdt_addr=0x7000000\0" \ + "fdt_high=0x10000000\0" \ + "sdboot=mmcinfo && fatload mmc 0:0 $fdt_addr system.dtb && " \ + "fatload mmc 0:0 $kernel_addr Image && booti $kernel_addr - $fdt_addr\0" + +#define CONFIG_BOOTARGS "setenv bootargs console=ttyPS0,${baudrate} " \ + "earlycon=cdns,mmio,0xff000000,${baudrate}n8" +#define CONFIG_PREBOOT "run bootargs" +#define CONFIG_BOOTCOMMAND "run $modeboot" +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_BOARD_LATE_INIT + +/* Do not preserve environment */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x1000 + +/* Monitor Command Prompt */ +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_PROMPT "ZynqMP> " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_MAXARGS 64 + +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) + +#define CONFIG_CMD_BOOTI +#define CONFIG_CMD_UNZIP + +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_CLOCKS + +#endif /* __XILINX_ZYNQMP_H */ diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index fe331bc082..1dbbc15256 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -136,7 +136,6 @@ unsigned char zipitz2_spi_read(void); /* * Clock Configuration */ -#undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ /* diff --git a/include/dfu.h b/include/dfu.h index c27856cb72..7d31abdf33 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -140,6 +140,9 @@ struct dfu_entity { unsigned int inited:1; }; +#ifdef CONFIG_SET_DFU_ALT_INFO +void set_dfu_alt_info(char *interface, char *devstr); +#endif int dfu_config_entities(char *s, char *interface, char *devstr); void dfu_free_entities(void); void dfu_show_entities(void); diff --git a/include/exports.h b/include/exports.h index 205affe72d..1a01e430bb 100644 --- a/include/exports.h +++ b/include/exports.h @@ -15,7 +15,9 @@ int printf(const char* fmt, ...); void install_hdlr(int, interrupt_handler_t, void*); void free_hdlr(int); void *malloc(size_t); +#ifndef CONFIG_SYS_MALLOC_SIMPLE void free(void*); +#endif void __udelay(unsigned long); unsigned long get_timer(unsigned long); int vprintf(const char *, va_list); diff --git a/include/fb_mmc.h b/include/fb_mmc.h index 1ad1d1327d..402ba9b1b4 100644 --- a/include/fb_mmc.h +++ b/include/fb_mmc.h @@ -6,3 +6,4 @@ void fb_mmc_flash_write(const char *cmd, void *download_buffer, unsigned int download_bytes, char *response); +void fb_mmc_erase(const char *cmd, char *response); diff --git a/include/fdtdec.h b/include/fdtdec.h index 1bc70dba21..1233dfb280 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -168,6 +168,7 @@ enum fdt_compat_id { COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */ COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ + COMPAT_PANASONIC_XHCI, /* Panasonic UniPhier xHCI */ COMPAT_COUNT, }; diff --git a/include/samsung/misc.h b/include/samsung/misc.h index 607e8d4922..0f957dc367 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -29,9 +29,8 @@ void draw_logo(void); #endif #ifdef CONFIG_SET_DFU_ALT_INFO -char *get_dfu_alt_system(void); -char *get_dfu_alt_boot(void); -void set_dfu_alt_info(void); +char *get_dfu_alt_system(char *interface, char *devstr); +char *get_dfu_alt_boot(char *interface, char *devstr); #endif #ifdef CONFIG_BOARD_TYPES void set_board_type(void); diff --git a/lib/fdtdec.c b/lib/fdtdec.c index dd58bbb482..21933e4a47 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -76,6 +76,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(AMS_AS3722, "ams,as3722"), COMPAT(INTEL_ICH_SPI, "intel,ich-spi"), COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"), + COMPAT(PANASONIC_XHCI, "panasonic,uniphier-xhci"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) diff --git a/scripts/kconfig/confdata.c b/scripts/kconfig/confdata.c index ae6ce669e1..f88d90f202 100644 --- a/scripts/kconfig/confdata.c +++ b/scripts/kconfig/confdata.c @@ -951,14 +951,6 @@ int conf_write_autoconf(void) FILE *out, *tristate, *out_h; int i; - /* - * Added for U-Boot SPL/TPL - */ - name = getenv("KCONFIG_OBJDIR"); - if (name && name[0]) - if (chdir(name)) - return 1; - sym_clear_all_valid(); file_write_dep("include/config/auto.conf.cmd"); |