diff options
| author | Paul Gortmaker <paul.gortmaker@windriver.com> | 2009-09-23 17:30:57 -0400 |
|---|---|---|
| committer | Tom Rix <Tom.Rix@windriver.com> | 2009-10-03 09:04:36 -0500 |
| commit | 9b5cee4344ebec01d989aa4c43cae5a6da1546ab (patch) | |
| tree | 0b05b4dc44a85c7d33a68298d1eaf07391f049e9 | |
| parent | 686d635d4563d229e4e6fc99c147b0ad6c58961b (diff) | |
sbc8548: cosmetic line re-wrap
Fix the extra long lines to be consistent with u-boot coding style.
No functional change here.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
| -rw-r--r-- | board/sbc8548/tlb.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 18d11f6dc7..ddcb532eef 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -31,13 +31,16 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -62,7 +65,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), |