diff options
| author | Tom Rini <trini@konsulko.com> | 2020-06-12 17:20:35 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-06-12 17:20:35 -0400 |
| commit | 9d886fd6a0888f121cd280d11434812a386045a2 (patch) | |
| tree | 29f65a6b8bcd9e98ce5cc1d9bab4fb6dfa94fd93 | |
| parent | be79009f3b9bbdbce283e67a865121e576d790ea (diff) | |
| parent | b45926fa1d5a1be2a55d0eb208bff8f04f00f875 (diff) | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi
- Drop davinci, mxs spi nondm code
- Zap nondm soft_spi
- Switch few board to DM_SPI
- Drop omap3_pandora, pcm051 boards
35 files changed, 130 insertions, 2212 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 21df1c415f..edc9e38c6c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1905,7 +1905,6 @@ source "board/hisilicon/hikey/Kconfig" source "board/hisilicon/hikey960/Kconfig" source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" -source "board/phytec/pcm051/Kconfig" source "board/silica/pengwyn/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index d75fab1530..870dae4d70 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -181,7 +181,6 @@ source "board/isee/igep00x0/Kconfig" source "board/overo/Kconfig" source "board/logicpd/zoom1/Kconfig" source "board/ti/am3517crane/Kconfig" -source "board/pandora/Kconfig" source "board/corscience/tricorder/Kconfig" source "board/logicpd/omap3som/Kconfig" source "board/nokia/rx51/Kconfig" diff --git a/board/pandora/Kconfig b/board/pandora/Kconfig deleted file mode 100644 index 0b33818008..0000000000 --- a/board/pandora/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_OMAP3_PANDORA - -config SYS_BOARD - default "pandora" - -config SYS_CONFIG_NAME - default "omap3_pandora" - -endif diff --git a/board/pandora/MAINTAINERS b/board/pandora/MAINTAINERS deleted file mode 100644 index e12351735c..0000000000 --- a/board/pandora/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PANDORA BOARD -M: Grazvydas Ignotas <notasas@gmail.com> -S: Maintained -F: board/pandora/ -F: include/configs/omap3_pandora.h -F: configs/omap3_pandora_defconfig diff --git a/board/pandora/Makefile b/board/pandora/Makefile deleted file mode 100644 index c05c8fb854..0000000000 --- a/board/pandora/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y := pandora.o diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c deleted file mode 100644 index a93848666f..0000000000 --- a/board/pandora/pandora.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2008 - * Grazvydas Ignotas <notasas@gmail.com> - * - * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * Sunil Kumar <sunilsaini05@gmail.com> - * Shashi Ranjan <shashiranjanmca05@gmail.com> - * - * (C) Copyright 2004-2008 - * Texas Instruments, <www.ti.com> - */ -#include <common.h> -#include <dm.h> -#include <init.h> -#include <ns16550.h> -#include <twl4030.h> -#include <asm/io.h> -#include <asm/gpio.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/mux.h> -#include <asm/arch/gpio.h> -#include <asm/arch/sys_proto.h> -#include <asm/mach-types.h> -#include <linux/delay.h> -#include "pandora.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define TWL4030_BB_CFG_BBCHEN (1 << 4) -#define TWL4030_BB_CFG_BBSEL_3200MV (3 << 2) -#define TWL4030_BB_CFG_BBISEL_500UA 2 - -#define CONTROL_WKUP_CTRL 0x48002a5c -#define GPIO_IO_PWRDNZ (1 << 6) -#define PBIASLITEVMODE1 (1 << 8) - -static const struct ns16550_platdata pandora_serial = { - .base = OMAP34XX_UART3, - .reg_shift = 2, - .clock = V_NS16550_CLK, - .fcr = UART_FCR_DEFVAL, -}; - -U_BOOT_DEVICE(pandora_uart) = { - "ns16550_serial", - &pandora_serial -}; - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_OMAP3_PANDORA; - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - return 0; -} - -static void set_output_gpio(unsigned int gpio, int value) -{ - int ret; - - ret = gpio_request(gpio, ""); - if (ret != 0) { - printf("could not request GPIO %u\n", gpio); - return; - } - ret = gpio_direction_output(gpio, value); - if (ret != 0) - printf("could not set GPIO %u to %d\n", gpio, value); -} - -/* - * Routine: misc_init_r - * Description: Configure board specific parts - */ -int misc_init_r(void) -{ - t2_t *t2_base = (t2_t *)T2_BASE; - u32 pbias_lite; - - twl4030_led_init(TWL4030_LED_LEDEN_LEDBON); - - /* set up dual-voltage GPIOs to 1.8V */ - pbias_lite = readl(&t2_base->pbias_lite); - pbias_lite &= ~PBIASLITEVMODE1; - pbias_lite |= PBIASLITEPWRDNZ1; - writel(pbias_lite, &t2_base->pbias_lite); - if (get_cpu_family() == CPU_OMAP36XX) - writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ, - CONTROL_WKUP_CTRL); - - /* make sure audio and BT chips are in powerdown state */ - set_output_gpio(14, 0); - set_output_gpio(15, 0); - set_output_gpio(118, 0); - - /* enable USB supply */ - set_output_gpio(164, 1); - - /* wifi needs a short pulse to enter powersave state */ - set_output_gpio(23, 1); - udelay(5000); - gpio_direction_output(23, 0); - - /* Enable battery backup capacitor (3.2V, 0.5mA charge current) */ - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, - TWL4030_PM_RECEIVER_BB_CFG, - TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV | - TWL4030_BB_CFG_BBISEL_500UA); - - omap_die_id_display(); - - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_PANDORA(); - if (get_cpu_family() == CPU_OMAP36XX) { - MUX_PANDORA_3730(); - } -} - -#ifdef CONFIG_MMC -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} - -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(0); -} -#endif diff --git a/board/pandora/pandora.h b/board/pandora/pandora.h deleted file mode 100644 index 9c4c5d1cd7..0000000000 --- a/board/pandora/pandora.h +++ /dev/null @@ -1,391 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 - * Grazvydas Ignotas <notasas@gmail.com> - */ -#ifndef _PANDORA_H_ -#define _PANDORA_H_ - -const omap3_sysinfo sysinfo = { - DDR_STACKED, - "OMAP3 Pandora", - "NAND", -}; - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_PANDORA() \ - /*SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - /*GPMC*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - /*DSS*/\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ - /*GPIO based game buttons*/\ - MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | DIS | M4)) /*GPIO_96 - LEFT*/\ - MUX_VAL(CP(CAM_PCLK), (IEN | PTD | DIS | M4)) /*GPIO_97 - L2*/\ - MUX_VAL(CP(CAM_FLD), (IEN | PTD | DIS | M4)) /*GPIO_98 - RIGHT*/\ - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M4)) /*GPIO_99 - MENU*/\ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M4)) /*GPIO_100 - START*/\ - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M4)) /*GPIO_101 - Y*/\ - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M4)) /*GPIO_102 - L1*/\ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M4)) /*GPIO_103 - DOWN*/\ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M4)) /*GPIO_104 - SELECT*/\ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M4)) /*GPIO_105 - R1*/\ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M4)) /*GPIO_106 - B*/\ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M4)) /*GPIO_107 - R2*/\ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M4)) /*GPIO_109 - X*/\ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M4)) /*GPIO_110 - UP*/\ - MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M4)) /*GPIO_111 - A*/\ - /*Audio Interface To External DAC (Headphone, Speakers)*/\ - MUX_VAL(CP(MCBSP2_FSX), (IDIS | PTD | DIS | M0)) /*McBSP2_FSX*/\ - MUX_VAL(CP(MCBSP2_CLKX), (IDIS | PTD | DIS | M0)) /*McBSP2_CLKX*/\ - MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | DIS | M0)) /*McBSP_CLKS*/\ - MUX_VAL(CP(MCBSP2_DR), (IDIS | PTD | DIS | M4)) /*GPIO_118*/\ - /* - nPOWERDOWN_DAC*/\ - /*Expansion card 1*/\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M4)) /*GPIO_126 - MMC1_WP*/\ - /*Expansion card 2*/\ - MUX_VAL(CP(MMC2_CLK), (IDIS | PTD | DIS | M0)) /*MMC2_CLK*/\ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ - MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT0*/\ - MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT1*/\ - MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_CMD */\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M4)) /*GPIO_127 - MMC2_WP*/\ - /*SDIO Interface to WIFI Module*/\ - MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /*MMC3_CLK*/\ - MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\ - /*Audio Interface To Bluetooth chip*/\ - MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/\ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX*/\ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\ - /*Digital Interface to Bluetooth (UART)*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M0)) /*UART1_CTS*/\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ - /*Audio Interface to Triton2 chip (TPS65950)*/\ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\ - MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\ - MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M0)) /*McBSP4_DX*/\ - MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\ - /*GPIO definitions for muxed pins on AV connector*/\ - MUX_VAL(CP(UART2_CTS), (IEN | PTD | EN | M4)) /*GPIO_144,*/\ - /*UART2_CTS*/\ - MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)) /*GPIO_145,*/\ - /*UART2_RTS*/\ - MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)) /*GPIO_146,*/\ - /*UART2_TX*/\ - MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)) /*GPIO_147,*/\ - /*UART2_RX*/\ - /*Serial Interface (Peripheral boot, Linux console, on AV connector)*/\ - /*RX pulled up to avoid noise when nothing is connected to serial port*/\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX*/\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX*/\ - /*LEDs (Controlled by OMAP)*/\ - MUX_VAL(CP(MMC1_DAT6), (IDIS | PTD | DIS | M4)) /*GPIO_128*/\ - /* - LED_MMC1*/\ - MUX_VAL(CP(MMC1_DAT7), (IDIS | PTD | DIS | M4)) /*GPIO_129*/\ - /* - LED_MMC2*/\ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\ - /* - LED_BT*/\ - MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\ - /* - LED_WIFI*/\ - /*Switches*/\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /*GPIO_176*/\ - /* - nHOLD_SWITCH*/\ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M4)) /*GPIO_108*/\ - /* - nLID_SWITCH*/\ - /*External IRQs*/\ - MUX_VAL(CP(CAM_HS), (IEN | PTD | DIS | M4)) /*GPIO_94*/\ - /* - nTOUCH_IRQ*/\ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M4)) /*GPIO_21*/\ - /* - WIFI_IRQ*/\ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M4)) /*GPIO_161*/\ - /* - nIRQ_NUB1*/\ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\ - /* - nIRQ_NUB2*/\ - /*Various other stuff*/\ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | DIS | M4)) /*GPIO_163*/\ - /* - nOC_USB5*/\ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M4)) /*GPIO_22*/\ - /* - MSECURE*/\ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M4)) /*GPIO_115*/\ - /* - POP_OVERHEAT*/\ - /*External Resets and Enables*/\ - MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_14*/\ - /* - nHDPHN_SHUTDOWN*/\ - MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_15*/\ - /* - nBT_SHUTDOWN*/\ - MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_23*/\ - /* - nWIFI_RESET*/\ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)) /*GPIO_157*/\ - /* - nLCD_RESET*/\ - MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\ - /* - RESET_NUBS*/\ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M4)) /*GPIO_164*/\ - /* - EN_USB_5V*/\ - /*Spare GPIOs*/\ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTD | EN | M4)) /*GPIO_58*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTD | EN | M4)) /*GPIO_64*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | EN | M4)) /*GPIO_65*/\ - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) /*GPIO_95*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) /*GPIO_167*/\ - MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) /*GPIO_170*/\ - /*HS USB OTG Port (connects to HSUSB0)*/\ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ - /*I2C Ports*/\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL - T2_CTRL*/\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA - T2_CTRL*/\ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL - NUBS*/\ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA - NUBS*/\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL - T2_SR*/\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA - T2_SR*/\ - /*Serial Interface (Touch, LCD control)*/\ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO*/\ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI*/\ - MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTU | EN | M0)) /*McSPI1_CS0 - TOUCH*/\ - MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTU | EN | M0)) /*McSPI1_CS1 - LCD*/\ - /*HS USB HOST Port (connects to HSUSB2)*/\ - MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*USB_HOST_CLK*/\ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | EN | M3)) /*USB_HOST_STP*/\ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_DIR*/\ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_NXT*/\ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_D0*/\ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_D1*/\ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*USB_HOST_D2*/\ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*USB_HOST_D3*/\ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*USB_HOST_D4*/\ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*USB_HOST_D5*/\ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) /*USB_HOST_D6*/\ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*USB_HOST_D7*/\ - MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_16*/\ - /* - nRESET_USB_HOST*/\ - /*Control and debug */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8*/\ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ - /*JTAG*/\ - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /*JTAG_NTRST*/\ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ - /*Die to Die stuff*/\ - MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ - MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ - MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ - MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ - MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ - MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ - MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ - MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ - MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ - MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ - MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ - MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ - MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ - MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ - MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ - MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ - MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ - MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ - MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ - MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ - MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ - MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ - MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ - MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ - MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ - MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ - MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ - MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ - MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ - MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ - MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ - MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ - MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm*/\ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq*/\ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ - -#define MUX_PANDORA_3730() \ - MUX_VAL(CP(GPIO126), (IEN | PTD | DIS | M4)) /*GPIO_126 - MMC1_WP*/\ - MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M4)) /*GPIO_127 - MMC2_WP*/\ - MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /*GPIO_128 - LED_MMC1*/\ - MUX_VAL(CP(GPIO129), (IDIS | PTD | DIS | M4)) /*GPIO_129 - LED_MMC2*/ - -#endif diff --git a/board/phytec/pcm051/Kconfig b/board/phytec/pcm051/Kconfig deleted file mode 100644 index 2cc0d8872d..0000000000 --- a/board/phytec/pcm051/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_PCM051 - -config SYS_BOARD - default "pcm051" - -config SYS_VENDOR - default "phytec" - -config SYS_SOC - default "am33xx" - -config SYS_CONFIG_NAME - default "pcm051" - -endif diff --git a/board/phytec/pcm051/MAINTAINERS b/board/phytec/pcm051/MAINTAINERS deleted file mode 100644 index 18ea636a83..0000000000 --- a/board/phytec/pcm051/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -PCM051 BOARD -M: Lars Poeschel <poeschel@lemonage.de> -S: Maintained -F: board/phytec/pcm051/ -F: include/configs/pcm051.h -F: configs/pcm051_rev1_defconfig -F: configs/pcm051_rev3_defconfig diff --git a/board/phytec/pcm051/Makefile b/board/phytec/pcm051/Makefile deleted file mode 100644 index ff6f8b4221..0000000000 --- a/board/phytec/pcm051/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Makefile -# -# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - -ifdef CONFIG_SPL_BUILD -obj-y += mux.o -endif - -obj-y += board.o diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c deleted file mode 100644 index 6f1ada82c4..0000000000 --- a/board/phytec/pcm051/board.c +++ /dev/null @@ -1,258 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * board.c - * - * Board functions for Phytec phyCORE-AM335x (pcm051) based boards - * - * Copyright (C) 2013 Lemonage Software GmbH - * Author Lars Poeschel <poeschel@lemonage.de> - */ - -#include <common.h> -#include <env.h> -#include <errno.h> -#include <init.h> -#include <net.h> -#include <spl.h> -#include <asm/arch/cpu.h> -#include <asm/arch/hardware.h> -#include <asm/arch/omap.h> -#include <asm/arch/ddr_defs.h> -#include <asm/arch/clock.h> -#include <asm/arch/gpio.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/sys_proto.h> -#include <asm/io.h> -#include <asm/emif.h> -#include <asm/gpio.h> -#include <i2c.h> -#include <miiphy.h> -#include <cpsw.h> -#include "board.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* MII mode defines */ -#define RMII_RGMII2_MODE_ENABLE 0x49 - -static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - -#ifdef CONFIG_SPL_BUILD - -/* DDR RAM defines */ -#define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */ - -#define OSC (V_OSCK/1000000) -const struct dpll_params dpll_ddr = { - DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1}; - -const struct dpll_params *get_dpll_ddr_params(void) -{ - return &dpll_ddr; -} - -#ifdef CONFIG_REV1 -const struct ctrl_ioregs ioregs = { - .cm0ioctl = MT41J256M8HX15E_IOCTRL_VALUE, - .cm1ioctl = MT41J256M8HX15E_IOCTRL_VALUE, - .cm2ioctl = MT41J256M8HX15E_IOCTRL_VALUE, - .dt0ioctl = MT41J256M8HX15E_IOCTRL_VALUE, - .dt1ioctl = MT41J256M8HX15E_IOCTRL_VALUE, -}; - -static const struct ddr_data ddr3_data = { - .datardsratio0 = MT41J256M8HX15E_RD_DQS, - .datawdsratio0 = MT41J256M8HX15E_WR_DQS, - .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE, - .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA, -}; - -static const struct cmd_control ddr3_cmd_ctrl_data = { - .cmd0csratio = MT41J256M8HX15E_RATIO, - .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT, - - .cmd1csratio = MT41J256M8HX15E_RATIO, - .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT, - - .cmd2csratio = MT41J256M8HX15E_RATIO, - .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT, -}; - -static struct emif_regs ddr3_emif_reg_data = { - .sdram_config = MT41J256M8HX15E_EMIF_SDCFG, - .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF, - .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1, - .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2, - .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3, - .zq_config = MT41J256M8HX15E_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY | - PHY_EN_DYN_PWRDN, -}; - -void sdram_init(void) -{ - config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, - &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -} -#else -const struct ctrl_ioregs ioregs = { - .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, -}; - -static const struct ddr_data ddr3_data = { - .datardsratio0 = MT41K256M16HA125E_RD_DQS, - .datawdsratio0 = MT41K256M16HA125E_WR_DQS, - .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, - .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, -}; - -static const struct cmd_control ddr3_cmd_ctrl_data = { - .cmd0csratio = MT41K256M16HA125E_RATIO, - .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, - - .cmd1csratio = MT41K256M16HA125E_RATIO, - .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, - - .cmd2csratio = MT41K256M16HA125E_RATIO, - .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, -}; - -static struct emif_regs ddr3_emif_reg_data = { - .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, - .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, - .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, - .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, - .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, - .zq_config = MT41K256M16HA125E_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY | - PHY_EN_DYN_PWRDN, -}; - -void sdram_init(void) -{ - config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, - &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -} -#endif - -void set_uart_mux_conf(void) -{ - enable_uart0_pin_mux(); -} - -void set_mux_conf_regs(void) -{ - /* Initalize the board header */ - enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - - enable_board_pin_mux(); -} -#endif - -/* - * Basic board specific setup. Pinmux has been handled already. - */ -int board_init(void) -{ - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -#ifdef CONFIG_DRIVER_TI_CPSW -static void cpsw_control(int enabled) -{ - /* VTP can be added here */ - - return; -} - -static struct cpsw_slave_data cpsw_slaves[] = { - { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 0, - .phy_if = PHY_INTERFACE_MODE_RGMII, - }, - { - .slave_reg_ofs = 0x308, - .sliver_reg_ofs = 0xdc0, - .phy_addr = 1, - .phy_if = PHY_INTERFACE_MODE_RGMII, - }, -}; - -static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, - .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, - .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 1, - .slave_data = cpsw_slaves, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, -}; -#endif - -#if defined(CONFIG_DRIVER_TI_CPSW) || \ - (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) -int board_eth_init(bd_t *bis) -{ - int rv, n = 0; -#ifdef CONFIG_DRIVER_TI_CPSW - uint8_t mac_addr[6]; - uint32_t mac_hi, mac_lo; - - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { - printf("<ethaddr> not set. Reading from E-fuse\n"); - /* try reading mac address from efuse */ - mac_lo = readl(&cdev->macid0l); - mac_hi = readl(&cdev->macid0h); - mac_addr[0] = mac_hi & 0xFF; - mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - mac_addr[3] = (mac_hi & 0xFF000000) >> 24; - mac_addr[4] = mac_lo & 0xFF; - mac_addr[5] = (mac_lo & 0xFF00) >> 8; - - if (is_valid_ethaddr(mac_addr)) - eth_env_set_enetaddr("ethaddr", mac_addr); - else - goto try_usbether; - } - - writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel); - - rv = cpsw_register(&cpsw_data); - if (rv < 0) - printf("Error %d registering CPSW switch\n", rv); - else - n += rv; -try_usbether: -#endif - -#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD) - rv = usb_eth_initialize(bis); - if (rv < 0) - printf("Error %d registering USB_ETHER\n", rv); - else - n += rv; -#endif - return n; -} -#endif diff --git a/board/phytec/pcm051/board.h b/board/phytec/pcm051/board.h deleted file mode 100644 index 3366e51c85..0000000000 --- a/board/phytec/pcm051/board.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * board.h - * - * Phytec phyCORE-AM335x (pcm051) boards information header - * - * Copyright (C) 2013, Lemonage Software GmbH - * Author Lars Poeschel <poeschel@lemonage.de> - */ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * We have three pin mux functions that must exist. We must be able to enable - * uart0, for initial output and i2c0 to read the main EEPROM. We then have a - * main pinmux function that can be overridden to enable all other pinmux that - * is required on the board. - */ -void enable_uart0_pin_mux(void); -void enable_i2c0_pin_mux(void); -void enable_board_pin_mux(void); -void enable_cbmux_pin_mux(void); -#endif diff --git a/board/phytec/pcm051/mux.c b/board/phytec/pcm051/mux.c deleted file mode 100644 index 9bca8eae9f..0000000000 --- a/board/phytec/pcm051/mux.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * mux.c - * - * Copyright (C) 2013 Lemonage Software GmbH - * Author Lars Poeschel <poeschel@lemonage.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <common.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/hardware.h> -#include <asm/arch/mux.h> -#include <asm/io.h> -#include "board.h" - -static struct module_pin_mux uart0_pin_mux[] = { - {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ - {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ - {-1}, -}; - -#ifdef CONFIG_MMC -static struct module_pin_mux mmc0_pin_mux[] = { - {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ - {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ - {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ - {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ - {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ - {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ - {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ - {-1}, -}; -#endif - -#ifdef CONFIG_I2C -static struct module_pin_mux i2c0_pin_mux[] = { - {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | - PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ - {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | - PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ - {-1}, -}; -#endif - -#ifdef CONFIG_SPI -static struct module_pin_mux spi0_pin_mux[] = { - {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */ - {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | - PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */ - {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */ - {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | - PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */ - {-1}, -}; -#endif - -static struct module_pin_mux rmii1_pin_mux[] = { - {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */ - {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */ - {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */ - {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */ - {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */ - {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */ - {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */ - {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ - {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ - {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */ - {-1}, -}; - -static struct module_pin_mux cbmux_pin_mux[] = { - {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */ - {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN}, /* JP4 */ - {-1}, -}; - -#ifdef CONFIG_MTD_RAW_NAND -static struct module_pin_mux nand_pin_mux[] = { - {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ - {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ - {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ - {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ - {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ - {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ - {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ - {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ - {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ - {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ - {-1}, -}; -#endif - -void enable_uart0_pin_mux(void) -{ - configure_module_pin_mux(uart0_pin_mux); -} - -void enable_i2c0_pin_mux(void) -{ - configure_module_pin_mux(i2c0_pin_mux); -} - -void enable_board_pin_mux() -{ - configure_module_pin_mux(rmii1_pin_mux); - configure_module_pin_mux(mmc0_pin_mux); - configure_module_pin_mux(cbmux_pin_mux); -#ifdef CONFIG_MTD_RAW_NAND - configure_module_pin_mux(nand_pin_mux); -#endif -#ifdef CONFIG_SPI - configure_module_pin_mux(spi0_pin_mux); -#endif -} diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 238164a55f..0aeaad577e 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -52,6 +52,7 @@ CONFIG_PHY_SMSC=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y CONFIG_LZO=y diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig index a5c301dbdb..d32c017907 100644 --- a/configs/igep00x0_defconfig +++ b/configs/igep00x0_defconfig @@ -62,6 +62,7 @@ CONFIG_SMC911X_BASE=0x2C000000 CONFIG_SMC911X_32_BIT=y CONFIG_CONS_INDEX=3 CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y CONFIG_BCH=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 644b6e5464..9f91fb9598 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -36,11 +36,13 @@ CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SPL_DM=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y CONFIG_MISC=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 5bc7f7f865..fb8fb250da 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -34,6 +34,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm" CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice" CONFIG_DTB_RESELECT=y @@ -41,6 +42,7 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y +CONFIG_SPL_DM=y CONFIG_DFU_MMC=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_MISC=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index eb5916c2c6..1cd7331653 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -36,11 +36,13 @@ CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SPL_DM=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y CONFIG_MISC=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 71a35e3496..ae4b26b7a9 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -36,11 +36,13 @@ CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SPL_DM=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y CONFIG_MISC=y diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig deleted file mode 100644 index d8ee7995de..0000000000 --- a/configs/omap3_pandora_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_TEXT_BASE=0x80008000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_OMAP3_PANDORA=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_DISTRO_DEFAULTS=y -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SYS_PROMPT="Pandora # " -# CONFIG_CMD_IMI is not set -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(xloader),1920k(uboot),128k(uboot-env),10m(boot),-(rootfs)" -CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_DM=y -CONFIG_TWL4030_LED=y -CONFIG_MMC_OMAP_HS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_DM_SERIAL=y -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig deleted file mode 100644 index ea7a0769f2..0000000000 --- a/configs/pcm051_rev1_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_AM33XX=y -CONFIG_TARGET_PCM051=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_FS_FAT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="REV1" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_ARCH_MISC_INIT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_ETH_SUPPORT=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_NAND_SUPPORT is not set -CONFIG_SPL_NET_SUPPORT=y -CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL" -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_CMD_SPL=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_MMC_OMAP_HS=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=24000000 -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_SMSC=y -CONFIG_MII=y -CONFIG_DRIVER_TI_CPSW=y -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -CONFIG_USB_MUSB_HOST=y -CONFIG_USB_MUSB_GADGET=y -CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_GADGET=y -CONFIG_USB_ETHER=y -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig deleted file mode 100644 index 43e64630ab..0000000000 --- a/configs/pcm051_rev3_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_AM33XX=y -CONFIG_TARGET_PCM051=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_FS_FAT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="REV3" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_ARCH_MISC_INIT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_ETH_SUPPORT=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_NAND_SUPPORT is not set -CONFIG_SPL_NET_SUPPORT=y -CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL" -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_CMD_SPL=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_MMC_OMAP_HS=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=24000000 -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_SMSC=y -CONFIG_MII=y -CONFIG_DRIVER_TI_CPSW=y -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -CONFIG_USB_MUSB_HOST=y -CONFIG_USB_MUSB_GADGET=y -CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_GADGET=y -CONFIG_USB_ETHER=y -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y diff --git a/doc/README.omap3 b/doc/README.omap3 index 00bcbdba9a..8c3667b10c 100644 --- a/doc/README.omap3 +++ b/doc/README.omap3 @@ -41,11 +41,6 @@ make make omap3_evm_config make -* Pandora: - -make omap3_pandora_config -make - * Zoom MDK: make omap3_zoom1_config diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 59415209ee..09b9cb17d8 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -119,6 +119,12 @@ config CF_SPI Enable the ColdFire SPI driver. This driver can be used on some m68k SoCs. +config DAVINCI_SPI + bool "Davinci & Keystone SPI driver" + depends on ARCH_DAVINCI || ARCH_KEYSTONE + help + Enable the Davinci SPI driver + config DESIGNWARE_SPI bool "Designware SPI driver" help @@ -207,6 +213,12 @@ config MVEBU_A3700_SPI used to access the SPI NOR flash on platforms embedding this Marvell IP core. +config MXS_SPI + bool "MXS SPI Driver" + help + Enable the MXS SPI controller driver. This driver can be used + on the i.MX23 and i.MX28 SoCs. + config NXP_FSPI bool "NXP FlexSPI driver" depends on SPI_MEM @@ -280,6 +292,12 @@ config SPI_SIFIVE The SiFive SPI controller driver is found on various SiFive SoCs. +config SOFT_SPI + bool "Soft SPI driver" + help + Enable Soft SPI driver. This driver is to use GPIO simulate + the SPI protocol. + config SPI_SUNXI bool "Allwinner SoC SPI controllers" default ARCH_SUNXI @@ -385,13 +403,6 @@ config ZYNQMP_GQSPI endif # if DM_SPI -config SOFT_SPI - bool "Soft SPI driver" - depends on DM_SPI || (DEPRECATED && !DM_SPI) - help - Enable Soft SPI driver. This driver is to use GPIO simulate - the SPI protocol. - config FSL_ESPI bool "Freescale eSPI driver" imply SPI_FLASH_BAR @@ -400,12 +411,6 @@ config FSL_ESPI access the SPI interface and SPI NOR flash on platforms embedding this Freescale eSPI IP core. -config DAVINCI_SPI - bool "Davinci & Keystone SPI driver" - depends on ARCH_DAVINCI || ARCH_KEYSTONE - help - Enable the Davinci SPI driver - config SH_QSPI bool "Renesas Quad SPI driver" help @@ -424,12 +429,6 @@ config MXC_SPI Enable the MXC SPI controller driver. This driver can be used on various i.MX SoCs such as i.MX31/35/51/6/7. -config MXS_SPI - bool "MXS SPI Driver" - help - Enable the MXS SPI controller driver. This driver can be used - on the i.MX23 and i.MX28 SoCs. - config OMAP3_SPI bool "McSPI driver for OMAP" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 342776404a..54881a7412 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -13,7 +13,6 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o else obj-y += spi.o obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o -obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index f076e92a93..b120664661 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -9,217 +9,102 @@ #include <spi.h> #include <malloc.h> #include <wait_bit.h> - #include <asm/io.h> - #include <asm/arch/clk.h> #include <asm/arch/hardware.h> -#ifdef CONFIG_DM_SPI #include <asm/arch/at91_spi.h> -#endif #if CONFIG_IS_ENABLED(DM_GPIO) #include <asm/gpio.h> #endif +#include <linux/bitops.h> -#include "atmel_spi.h" - -#ifndef CONFIG_DM_SPI - -static int spi_has_wdrbt(struct atmel_spi_slave *slave) -{ - unsigned int ver; - - ver = spi_readl(slave, VERSION); - - return (ATMEL_SPI_VERSION_REV(ver) >= 0x210); -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct atmel_spi_slave *as; - unsigned int scbr; - u32 csrx; - void *regs; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - switch (bus) { - case 0: - regs = (void *)ATMEL_BASE_SPI0; - break; -#ifdef ATMEL_BASE_SPI1 - case 1: - regs = (void *)ATMEL_BASE_SPI1; - break; -#endif -#ifdef ATMEL_BASE_SPI2 - case 2: - regs = (void *)ATMEL_BASE_SPI2; - break; -#endif -#ifdef ATMEL_BASE_SPI3 - case 3: - regs = (void *)ATMEL_BASE_SPI3; - break; -#endif - default: - return NULL; - } - - - scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz; - if (scbr > ATMEL_SPI_CSRx_SCBR_MAX) - /* Too low max SCK rate */ - return NULL; - if (scbr < 1) - scbr = 1; - - csrx = ATMEL_SPI_CSRx_SCBR(scbr); - csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8); - if (!(mode & SPI_CPHA)) - csrx |= ATMEL_SPI_CSRx_NCPHA; - if (mode & SPI_CPOL) - csrx |= ATMEL_SPI_CSRx_CPOL; - - as = spi_alloc_slave(struct atmel_spi_slave, bus, cs); - if (!as) - return NULL; - - as->regs = regs; - as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS - | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf); - if (spi_has_wdrbt(as)) - as->mr |= ATMEL_SPI_MR_WDRBT; - - spi_writel(as, CSR(cs), csrx); - - return &as->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct atmel_spi_slave *as = to_atmel_spi(slave); - - free(as); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct atmel_spi_slave *as = to_atmel_spi(slave); - - /* Enable the SPI hardware */ - spi_writel(as, CR, ATMEL_SPI_CR_SPIEN); - - /* - * Select the slave. This should set SCK to the correct - * initial state, etc. - */ - spi_writel(as, MR, as->mr); - - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - struct atmel_spi_slave *as = to_atmel_spi(slave); - - /* Disable the SPI hardware */ - spi_writel(as, CR, ATMEL_SPI_CR_SPIDIS); -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct atmel_spi_slave *as = to_atmel_spi(slave); - unsigned int len_tx; - unsigned int len_rx; - unsigned int len; - u32 status; - const u8 *txp = dout; - u8 *rxp = din; - u8 value; - - if (bitlen == 0) - /* Finish any previously submitted transfers */ - goto out; - - /* - * TODO: The controller can do non-multiple-of-8 bit - * transfers, but this driver currently doesn't support it. - * - * It's also not clear how such transfers are supposed to be - * represented as a stream of bytes...this is a limitation of - * the current SPI interface. - */ - if (bitlen % 8) { - /* Errors always terminate an ongoing transfer */ - flags |= SPI_XFER_END; - goto out; - } - - len = bitlen / 8; - - /* - * The controller can do automatic CS control, but it is - * somewhat quirky, and it doesn't really buy us much anyway - * in the context of U-Boot. - */ - if (flags & SPI_XFER_BEGIN) { - spi_cs_activate(slave); - /* - * sometimes the RDR is not empty when we get here, - * in theory that should not happen, but it DOES happen. - * Read it here to be on the safe side. - * That also clears the OVRES flag. Required if the - * following loop exits due to OVRES! - */ - spi_readl(as, RDR); - } - - for (len_tx = 0, len_rx = 0; len_rx < len; ) { - status = spi_readl(as, SR); - - if (status & ATMEL_SPI_SR_OVRES) - return -1; - - if (len_tx < len && (status & ATMEL_SPI_SR_TDRE)) { - if (txp) - value = *txp++; - else - value = 0; - spi_writel(as, TDR, value); - len_tx++; - } - if (status & ATMEL_SPI_SR_RDRF) { - value = spi_readl(as, RDR); - if (rxp) - *rxp++ = value; - len_rx++; - } - } - -out: - if (flags & SPI_XFER_END) { - /* - * Wait until the transfer is completely done before - * we deactivate CS. - */ - do { - status = spi_readl(as, SR); - } while (!(status & ATMEL_SPI_SR_TXEMPTY)); - - spi_cs_deactivate(slave); - } - - return 0; -} - -#else +/* + * Register definitions for the Atmel AT32/AT91 SPI Controller + */ +/* Register offsets */ +#define ATMEL_SPI_CR 0x0000 +#define ATMEL_SPI_MR 0x0004 +#define ATMEL_SPI_RDR 0x0008 +#define ATMEL_SPI_TDR 0x000c +#define ATMEL_SPI_SR 0x0010 +#define ATMEL_SPI_IER 0x0014 +#define ATMEL_SPI_IDR 0x0018 +#define ATMEL_SPI_IMR 0x001c +#define ATMEL_SPI_CSR(x) (0x0030 + 4 * (x)) +#define ATMEL_SPI_VERSION 0x00fc + +/* Bits in CR */ +#define ATMEL_SPI_CR_SPIEN BIT(0) +#define ATMEL_SPI_CR_SPIDIS BIT(1) +#define ATMEL_SPI_CR_SWRST BIT(7) +#define ATMEL_SPI_CR_LASTXFER BIT(24) + +/* Bits in MR */ +#define ATMEL_SPI_MR_MSTR BIT(0) +#define ATMEL_SPI_MR_PS BIT(1) +#define ATMEL_SPI_MR_PCSDEC BIT(2) +#define ATMEL_SPI_MR_FDIV BIT(3) +#define ATMEL_SPI_MR_MODFDIS BIT(4) +#define ATMEL_SPI_MR_WDRBT BIT(5) +#define ATMEL_SPI_MR_LLB BIT(7) +#define ATMEL_SPI_MR_PCS(x) (((x) & 15) << 16) +#define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24) + +/* Bits in RDR */ +#define ATMEL_SPI_RDR_RD(x) (x) +#define ATMEL_SPI_RDR_PCS(x) ((x) << 16) + +/* Bits in TDR */ +#define ATMEL_SPI_TDR_TD(x) (x) +#define ATMEL_SPI_TDR_PCS(x) ((x) << 16) +#define ATMEL_SPI_TDR_LASTXFER BIT(24) + +/* Bits in SR/IER/IDR/IMR */ +#define ATMEL_SPI_SR_RDRF BIT(0) +#define ATMEL_SPI_SR_TDRE BIT(1) +#define ATMEL_SPI_SR_MODF BIT(2) +#define ATMEL_SPI_SR_OVRES BIT(3) +#define ATMEL_SPI_SR_ENDRX BIT(4) +#define ATMEL_SPI_SR_ENDTX BIT(5) +#define ATMEL_SPI_SR_RXBUFF BIT(6) +#define ATMEL_SPI_SR_TXBUFE BIT(7) +#define ATMEL_SPI_SR_NSSR BIT(8) +#define ATMEL_SPI_SR_TXEMPTY BIT(9) +#define ATMEL_SPI_SR_SPIENS BIT(16) + +/* Bits in CSRx */ +#define ATMEL_SPI_CSRx_CPOL BIT(0) +#define ATMEL_SPI_CSRx_NCPHA BIT(1) +#define ATMEL_SPI_CSRx_CSAAT BIT(3) +#define ATMEL_SPI_CSRx_BITS(x) ((x) << 4) +#define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8) +#define ATMEL_SPI_CSRx_SCBR_MAX GENMASK(7, 0) +#define ATMEL_SPI_CSRx_DLYBS(x) ((x) << 16) +#define ATMEL_SPI_CSRx_DLYBCT(x) ((x) << 24) + +/* Bits in VERSION */ +#define ATMEL_SPI_VERSION_REV(x) ((x) & 0xfff) +#define ATMEL_SPI_VERSION_MFN(x) ((x) << 16) + +/* Constants for CSRx:BITS */ +#define ATMEL_SPI_BITS_8 0 +#define ATMEL_SPI_BITS_9 1 +#define ATMEL_SPI_BITS_10 2 +#define ATMEL_SPI_BITS_11 3 +#define ATMEL_SPI_BITS_12 4 +#define ATMEL_SPI_BITS_13 5 +#define ATMEL_SPI_BITS_14 6 +#define ATMEL_SPI_BITS_15 7 +#define ATMEL_SPI_BITS_16 8 #define MAX_CS_COUNT 4 +/* Register access macros */ +#define spi_readl(as, reg) \ + readl(as->regs + ATMEL_SPI_##reg) +#define spi_writel(as, reg, value) \ + writel(value, as->regs + ATMEL_SPI_##reg) + struct atmel_spi_platdata { struct at91_spi *regs; }; @@ -507,4 +392,3 @@ U_BOOT_DRIVER(atmel_spi) = { .priv_auto_alloc_size = sizeof(struct atmel_spi_priv), .probe = atmel_spi_probe, }; -#endif diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h index 6167bd164b..9663cca5e6 100644 --- a/drivers/spi/atmel_spi.h +++ b/drivers/spi/atmel_spi.h @@ -79,23 +79,8 @@ #define ATMEL_SPI_BITS_15 7 #define ATMEL_SPI_BITS_16 8 -struct atmel_spi_slave { - struct spi_slave slave; - void *regs; - u32 mr; -}; - -static inline struct atmel_spi_slave *to_atmel_spi(struct spi_slave *slave) -{ - return container_of(slave, struct atmel_spi_slave, slave); -} - /* Register access macros */ #define spi_readl(as, reg) \ readl(as->regs + ATMEL_SPI_##reg) #define spi_writel(as, reg, value) \ writel(value, as->regs + ATMEL_SPI_##reg) - -#if !defined(CONFIG_SYS_SPI_WRITE_TOUT) -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) -#endif diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 97ac97b1a5..e1e9b45cc9 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -55,41 +55,6 @@ /* SPIDEF */ #define SPIDEF_CSDEF0_MASK BIT(0) -#ifndef CONFIG_DM_SPI -#define SPI0_BUS 0 -#define SPI0_BASE CONFIG_SYS_SPI_BASE -/* - * Define default SPI0_NUM_CS as 1 for existing platforms that uses this - * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS - * if more than one CS is supported and by defining CONFIG_SYS_SPI0. - */ -#ifndef CONFIG_SYS_SPI0 -#define SPI0_NUM_CS 1 -#else -#define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS -#endif - -/* - * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and - * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus - */ -#ifdef CONFIG_SYS_SPI1 -#define SPI1_BUS 1 -#define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS -#define SPI1_BASE CONFIG_SYS_SPI1_BASE -#endif - -/* - * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and - * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus - */ -#ifdef CONFIG_SYS_SPI2 -#define SPI2_BUS 2 -#define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS -#define SPI2_BASE CONFIG_SYS_SPI2_BASE -#endif -#endif - DECLARE_GLOBAL_DATA_PTR; /* davinci spi register set */ @@ -122,9 +87,6 @@ struct davinci_spi_regs { /* davinci spi slave */ struct davinci_spi_slave { -#ifndef CONFIG_DM_SPI - struct spi_slave slave; -#endif struct davinci_spi_regs *regs; unsigned int freq; /* current SPI bus frequency */ unsigned int mode; /* current SPI mode used */ @@ -346,124 +308,6 @@ out: return 0; } -#ifndef CONFIG_DM_SPI - -static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave) -{ - return container_of(slave, struct davinci_spi_slave, slave); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - int ret = 0; - - switch (bus) { - case SPI0_BUS: - if (cs < SPI0_NUM_CS) - ret = 1; - break; -#ifdef CONFIG_SYS_SPI1 - case SPI1_BUS: - if (cs < SPI1_NUM_CS) - ret = 1; - break; -#endif -#ifdef CONFIG_SYS_SPI2 - case SPI2_BUS: - if (cs < SPI2_NUM_CS) - ret = 1; - break; -#endif - default: - /* Invalid bus number. Do nothing */ - break; - } - return ret; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - /* do nothing */ -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - /* do nothing */ -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct davinci_spi_slave *ds; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs); - if (!ds) - return NULL; - - switch (bus) { - case SPI0_BUS: - ds->regs = (struct davinci_spi_regs *)SPI0_BASE; - break; -#ifdef CONFIG_SYS_SPI1 - case SPI1_BUS: - ds->regs = (struct davinci_spi_regs *)SPI1_BASE; - break; -#endif -#ifdef CONFIG_SYS_SPI2 - case SPI2_BUS: - ds->regs = (struct davinci_spi_regs *)SPI2_BASE; - break; -#endif - default: /* Invalid bus number */ - return NULL; - } - - ds->freq = max_hz; - ds->mode = mode; - - return &ds->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - - free(ds); -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - - ds->cur_cs = slave->cs; - - return __davinci_spi_xfer(ds, bitlen, dout, din, flags); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - -#ifdef CONFIG_SPI_HALF_DUPLEX - ds->half_duplex = true; -#else - ds->half_duplex = false; -#endif - return __davinci_spi_claim_bus(ds, ds->slave.cs); -} - -void spi_release_bus(struct spi_slave *slave) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - - __davinci_spi_release_bus(ds); -} - -#else static int davinci_spi_set_speed(struct udevice *bus, uint max_hz) { struct davinci_spi_slave *ds = dev_get_priv(bus); @@ -582,4 +426,3 @@ U_BOOT_DRIVER(davinci_spi) = { .ops = &davinci_spi_ops, .priv_auto_alloc_size = sizeof(struct davinci_spi_slave), }; -#endif diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index 1cdb233110..78ad61ca37 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -100,13 +100,6 @@ struct fsl_dspi_priv { struct dspi *regs; }; -#ifndef CONFIG_DM_SPI -struct fsl_dspi { - struct spi_slave slave; - struct fsl_dspi_priv priv; -}; -#endif - __weak void cpu_dspi_port_conf(void) { } @@ -414,131 +407,7 @@ static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed) return 0; } -#ifndef CONFIG_DM_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8))) - return 1; - else - return 0; -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct fsl_dspi *dspi; - uint mcr_cfg_val; - - dspi = spi_alloc_slave(struct fsl_dspi, bus, cs); - if (!dspi) - return NULL; - - cpu_dspi_port_conf(); - -#ifdef CONFIG_SYS_FSL_DSPI_BE - dspi->priv.flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG; -#endif - - dspi->priv.regs = (struct dspi *)MMAP_DSPI; - -#ifdef CONFIG_M68K - dspi->priv.bus_clk = gd->bus_clk; -#else - dspi->priv.bus_clk = mxc_get_clock(MXC_DSPI_CLK); -#endif - dspi->priv.speed_hz = FSL_DSPI_DEFAULT_SCK_FREQ; - - /* default: all CS signals inactive state is high */ - mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK | - DSPI_MCR_CRXF | DSPI_MCR_CTXF; - fsl_dspi_init_mcr(&dspi->priv, mcr_cfg_val); - - for (i = 0; i < FSL_DSPI_MAX_CHIPSELECT; i++) - dspi->priv.ctar_val[i] = DSPI_CTAR_DEFAULT_VALUE; - -#ifdef CONFIG_SYS_DSPI_CTAR0 - if (FSL_DSPI_MAX_CHIPSELECT > 0) - dspi->priv.ctar_val[0] = CONFIG_SYS_DSPI_CTAR0; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR1 - if (FSL_DSPI_MAX_CHIPSELECT > 1) - dspi->priv.ctar_val[1] = CONFIG_SYS_DSPI_CTAR1; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR2 - if (FSL_DSPI_MAX_CHIPSELECT > 2) - dspi->priv.ctar_val[2] = CONFIG_SYS_DSPI_CTAR2; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR3 - if (FSL_DSPI_MAX_CHIPSELECT > 3) - dspi->priv.ctar_val[3] = CONFIG_SYS_DSPI_CTAR3; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR4 - if (FSL_DSPI_MAX_CHIPSELECT > 4) - dspi->priv.ctar_val[4] = CONFIG_SYS_DSPI_CTAR4; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR5 - if (FSL_DSPI_MAX_CHIPSELECT > 5) - dspi->priv.ctar_val[5] = CONFIG_SYS_DSPI_CTAR5; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR6 - if (FSL_DSPI_MAX_CHIPSELECT > 6) - dspi->priv.ctar_val[6] = CONFIG_SYS_DSPI_CTAR6; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR7 - if (FSL_DSPI_MAX_CHIPSELECT > 7) - dspi->priv.ctar_val[7] = CONFIG_SYS_DSPI_CTAR7; -#endif - fsl_dspi_cfg_speed(&dspi->priv, max_hz); - - /* configure transfer mode */ - fsl_dspi_cfg_ctar_mode(&dspi->priv, cs, mode); - - /* configure active state of CSX */ - fsl_dspi_cfg_cs_active_state(&dspi->priv, cs, mode); - - return &dspi->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - free(slave); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - uint sr_val; - struct fsl_dspi *dspi = (struct fsl_dspi *)slave; - - cpu_dspi_claim_bus(slave->bus, slave->cs); - - fsl_dspi_clr_fifo(&dspi->priv); - - /* check module TX and RX status */ - sr_val = dspi_read32(dspi->priv.flags, &dspi->priv.regs->sr); - if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) { - debug("DSPI RX/TX not ready!\n"); - return -EIO; - } - - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - struct fsl_dspi *dspi = (struct fsl_dspi *)slave; - - dspi_halt(&dspi->priv, 1); - cpu_dspi_release_bus(slave->bus.slave->cs); -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) -{ - struct fsl_dspi *dspi = (struct fsl_dspi *)slave; - return dspi_xfer(&dspi->priv, slave->cs, bitlen, dout, din, flags); -} -#else static int fsl_dspi_child_pre_probe(struct udevice *dev) { struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); @@ -745,4 +614,3 @@ U_BOOT_DRIVER(fsl_dspi) = { .child_pre_probe = fsl_dspi_child_pre_probe, .bind = fsl_dspi_bind, }; -#endif diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index 0da4a80d71..e231e96e58 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -13,7 +13,10 @@ */ #include <common.h> +#include <dm.h> +#include <dt-structs.h> #include <cpu_func.h> +#include <errno.h> #include <log.h> #include <malloc.h> #include <memalign.h> @@ -34,34 +37,9 @@ #define MXSSSP_SMALL_TRANSFER 512 -static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs) -{ - writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set); - writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr); -} - -static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs) -{ - writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr); - writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set); -} - -#if !CONFIG_IS_ENABLED(DM_SPI) -struct mxs_spi_slave { - struct spi_slave slave; - uint32_t max_khz; - uint32_t mode; - struct mxs_ssp_regs *regs; -}; - -static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave) -{ - return container_of(slave, struct mxs_spi_slave, slave); -} -#else -#include <dm.h> -#include <errno.h> -#include <dt-structs.h> +/* Base numbers of i.MX2[38] clk for ssp0 IP block */ +#define MXS_SSP_IMX23_CLKID_SSP0 33 +#define MXS_SSP_IMX28_CLKID_SSP0 46 #ifdef CONFIG_MX28 #define dtd_fsl_imx_spi dtd_fsl_imx28_spi @@ -87,20 +65,24 @@ struct mxs_spi_priv { unsigned int clk_id; unsigned int mode; }; -#endif -#if !CONFIG_IS_ENABLED(DM_SPI) -static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave, - char *data, int length, int write, unsigned long flags) +static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs) { - struct mxs_ssp_regs *ssp_regs = slave->regs; -#else + writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set); + writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr); +} + +static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs) +{ + writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr); + writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set); +} + static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv, char *data, int length, int write, unsigned long flags) { struct mxs_ssp_regs *ssp_regs = priv->regs; -#endif if (flags & SPI_XFER_BEGIN) mxs_spi_start_xfer(ssp_regs); @@ -156,17 +138,10 @@ static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv, return 0; } -#if !CONFIG_IS_ENABLED(DM_SPI) -static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, - char *data, int length, int write, unsigned long flags) -{ - struct mxs_ssp_regs *ssp_regs = slave->regs; -#else static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv, char *data, int length, int write, unsigned long flags) { struct mxs_ssp_regs *ssp_regs = priv->regs; -#endif const int xfer_max_sz = 0xff00; const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1; struct mxs_dma_desc *dp; @@ -207,11 +182,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv, /* Invalidate the area, so no writeback into the RAM races with DMA */ invalidate_dcache_range(dstart, dstart + cache_data_count); -#if !CONFIG_IS_ENABLED(DM_SPI) - dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus; -#else dmach = priv->dma_channel; -#endif dp = desc; while (length) { @@ -288,20 +259,12 @@ static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv, return ret; } -#if !CONFIG_IS_ENABLED(DM_SPI) -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); - struct mxs_ssp_regs *ssp_regs = mxs_slave->regs; -#else int mxs_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { struct udevice *bus = dev_get_parent(dev); struct mxs_spi_priv *priv = dev_get_priv(bus); struct mxs_ssp_regs *ssp_regs = priv->regs; -#endif int len = bitlen / 8; char dummy; int write = 0; @@ -345,99 +308,13 @@ int mxs_spi_xfer(struct udevice *dev, unsigned int bitlen, if (!dma || (len < MXSSSP_SMALL_TRANSFER)) { writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); -#if !CONFIG_IS_ENABLED(DM_SPI) - return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags); -#else return mxs_spi_xfer_pio(priv, data, len, write, flags); -#endif } else { writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); -#if !CONFIG_IS_ENABLED(DM_SPI) - return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags); -#else return mxs_spi_xfer_dma(priv, data, len, write, flags); -#endif } } -#if !CONFIG_IS_ENABLED(DM_SPI) -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - /* MXS SPI: 4 ports and 3 chip selects maximum */ - if (!mxs_ssp_bus_id_valid(bus) || cs > 2) - return 0; - else - return 1; -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct mxs_spi_slave *mxs_slave; - - if (!spi_cs_is_valid(bus, cs)) { - printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs); - return NULL; - } - - mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs); - if (!mxs_slave) - return NULL; - - if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus)) - goto err_init; - - mxs_slave->max_khz = max_hz / 1000; - mxs_slave->mode = mode; - mxs_slave->regs = mxs_ssp_regs_by_bus(bus); - - return &mxs_slave->slave; - -err_init: - free(mxs_slave); - return NULL; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); - - free(mxs_slave); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); - struct mxs_ssp_regs *ssp_regs = mxs_slave->regs; - u32 reg = 0; - - mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); - - writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) | - SSP_CTRL0_BUS_WIDTH_ONE_BIT, - &ssp_regs->hw_ssp_ctrl0); - - reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS; - reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0; - reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0; - writel(reg, &ssp_regs->hw_ssp_ctrl1); - - writel(0, &ssp_regs->hw_ssp_cmd0); - - mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz); - - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ -} - -#else /* CONFIG_DM_SPI */ -/* Base numbers of i.MX2[38] clk for ssp0 IP block */ -#define MXS_SSP_IMX23_CLKID_SSP0 33 -#define MXS_SSP_IMX28_CLKID_SSP0 46 - static int mxs_spi_probe(struct udevice *bus) { struct mxs_spi_platdata *plat = dev_get_platdata(bus); @@ -625,4 +502,3 @@ U_BOOT_DRIVER(mxs_spi) = { .priv_auto_alloc_size = sizeof(struct mxs_spi_priv), .probe = mxs_spi_probe, }; -#endif diff --git a/drivers/spi/soft_spi_legacy.c b/drivers/spi/soft_spi_legacy.c deleted file mode 100644 index cc5ab5f991..0000000000 --- a/drivers/spi/soft_spi_legacy.c +++ /dev/null @@ -1,168 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. - * - * Influenced by code from: - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <spi.h> - -#include <malloc.h> - -/*----------------------------------------------------------------------- - * Definitions - */ - -#ifdef DEBUG_SPI -#define PRINTD(fmt,args...) printf (fmt ,##args) -#else -#define PRINTD(fmt,args...) -#endif - -struct soft_spi_slave { - struct spi_slave slave; - unsigned int mode; -}; - -static inline struct soft_spi_slave *to_soft_spi(struct spi_slave *slave) -{ - return container_of(slave, struct soft_spi_slave, slave); -} - -/*=====================================================================*/ -/* Public Functions */ -/*=====================================================================*/ - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct soft_spi_slave *ss; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - ss = spi_alloc_slave(struct soft_spi_slave, bus, cs); - if (!ss) - return NULL; - - ss->mode = mode; - - /* TODO: Use max_hz to limit the SCK rate */ - - return &ss->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct soft_spi_slave *ss = to_soft_spi(slave); - - free(ss); -} - -int spi_claim_bus(struct spi_slave *slave) -{ -#ifdef CONFIG_SYS_IMMR - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; -#endif - struct soft_spi_slave *ss = to_soft_spi(slave); - - /* - * Make sure the SPI clock is in idle state as defined for - * this slave. - */ - if (ss->mode & SPI_CPOL) - SPI_SCL(1); - else - SPI_SCL(0); - - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - /* Nothing to do */ -} - -/*----------------------------------------------------------------------- - * SPI transfer - * - * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks - * "bitlen" bits in the SPI MISO port. That's just the way SPI works. - * - * The source of the outgoing bits is the "dout" parameter and the - * destination of the input bits is the "din" parameter. Note that "dout" - * and "din" can point to the same memory location, in which case the - * input data overwrites the output data (since both are buffered by - * temporary variables, this is OK). - */ -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ -#ifdef CONFIG_SYS_IMMR - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; -#endif - struct soft_spi_slave *ss = to_soft_spi(slave); - uchar tmpdin = 0; - uchar tmpdout = 0; - const u8 *txd = dout; - u8 *rxd = din; - int cpol = ss->mode & SPI_CPOL; - int cpha = ss->mode & SPI_CPHA; - unsigned int j; - - PRINTD("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", - slave->bus, slave->cs, *(uint *)txd, *(uint *)rxd, bitlen); - - if (flags & SPI_XFER_BEGIN) - spi_cs_activate(slave); - - for(j = 0; j < bitlen; j++) { - /* - * Check if it is time to work on a new byte. - */ - if ((j % 8) == 0) { - if (txd) - tmpdout = *txd++; - else - tmpdout = 0; - if(j != 0) { - if (rxd) - *rxd++ = tmpdin; - } - tmpdin = 0; - } - - if (!cpha) - SPI_SCL(!cpol); - SPI_SDA(tmpdout & 0x80); - SPI_DELAY; - if (cpha) - SPI_SCL(!cpol); - else - SPI_SCL(cpol); - tmpdin <<= 1; - tmpdin |= SPI_READ; - tmpdout <<= 1; - SPI_DELAY; - if (cpha) - SPI_SCL(cpol); - } - /* - * If the number of bits isn't a multiple of 8, shift the last - * bits over to left-justify them. Then store the last byte - * read in. - */ - if (rxd) { - if ((bitlen % 8) != 0) - tmpdin <<= 8 - (bitlen % 8); - *rxd++ = tmpdin; - } - - if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); - - return(0); -} diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h deleted file mode 100644 index ecf308e381..0000000000 --- a/include/configs/omap3_pandora.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008-2010 - * GraÅžvydas Ignotas <notasas@gmail.com> - * - * Configuration settings for the OMAP3 Pandora. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* override base for compatibility with MLO the device ships with */ - -#include <configs/ti_omap3_common.h> - -#define CONFIG_REVISION_TAG 1 - -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -/* - * Board NAND Info. - */ -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 - - -#define CONFIG_BOOTCOMMAND \ - "run distro_bootcmd; " \ - "setenv bootargs ${bootargs_ubi}; " \ - "if mmc rescan && load mmc 0:1 ${loadaddr} autoboot.scr; then " \ - "source ${loadaddr}; " \ - "fi; " \ - "ubi part boot && ubifsmount ubi:boot && " \ - "ubifsload ${loadaddr} uImage && bootm ${loadaddr}" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - -#include <config_distro_bootcmd.h> - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "usbtty=cdc_acm\0" \ - "bootargs_ubi=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \ - "rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - BOOTENV \ - -/* memtest works on */ - -#if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE -#endif - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h deleted file mode 100644 index 706a8a2a87..0000000000 --- a/include/configs/pcm051.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * pcm051.h - * - * Phytec phyCORE-AM335x (pcm051) boards information header - * - * Copyright (C) 2013 Lemonage Software GmbH - * Author Lars Poeschel <poeschel@lemonage.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __CONFIG_PCM051_H -#define __CONFIG_PCM051_H - -#include <configs/ti_am335x_common.h> - -#define CONFIG_MACH_TYPE MACH_TYPE_PCM051 - -/* set to negative value for no autoboot */ -#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel #instance "=" \ - "setenv mmcdev " #instance"; "\ - "setenv bootpart " #instance":2 ; "\ - "run mmcboot\0" - -#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel "=" \ - "run nandboot\0" - -#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(LEGACY_MMC, legacy_mmc, 0) \ - func(MMC, mmc, 1) \ - func(LEGACY_MMC, legacy_mmc, 1) \ - func(NAND, nand, 0) - -#define CONFIG_BOOTCOMMAND \ - "run distro_bootcmd" - -#include <config_distro_bootcmd.h> - -#include <environment/ti/dfu.h> -#include <environment/ti/mmc.h> - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - DEFAULT_MMC_TI_ARGS \ - "bootfile=uImage\0" \ - "fdtfile=am335x-wega-rdk.dtb\0" \ - "console=ttyO0,115200n8\0" \ - "optargs=\0" \ - "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ - "ramrootfstype=ext2\0" \ - "bootenv=uEnv.txt\0" \ - "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ - "source ${loadaddr}\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "ramargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${ramroot} " \ - "rootfstype=${ramrootfstype}\0" \ - "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ - "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ - "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run args_mmc; " \ - "bootm ${loadaddr}\0" \ - "ramboot=echo Booting from ramdisk ...; " \ - "run ramargs; " \ - "bootm ${loadaddr}\0" \ - BOOTENV - -/* Clock Defines */ -#define V_OSCK 25000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -/* - * memtest works on 8 MB in DRAM after skipping 32MB from - * start addr of ram disk - */ - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ - -/* I2C Configuration */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ -4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } - -/* CPU */ - -#ifdef CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 -#endif - -/* - * USB configuration - */ -#define CONFIG_AM335X_USB0 -#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL -#define CONFIG_AM335X_USB1 -#define CONFIG_AM335X_USB1_MODE MUSB_HOST - -#endif /* ! __CONFIG_PCM051_H */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 1b014c1022..b632ae010d 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -53,10 +53,6 @@ /* UART Configuration */ #define CONFIG_SYS_NS16550_MEM32 -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#endif #define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE @@ -68,19 +64,6 @@ /* SPI Configuration */ #define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) -#define CONFIG_SYS_SPI0 -#define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE -#define CONFIG_SYS_SPI0_NUM_CS 4 -#define CONFIG_SYS_SPI1 -#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE -#define CONFIG_SYS_SPI1_NUM_CS 4 -#define CONFIG_SYS_SPI2 -#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE -#define CONFIG_SYS_SPI2_NUM_CS 4 -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH -#endif /* Network Configuration */ #define CONFIG_BOOTP_DEFAULT diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 2210f46e44..f6bf6f2474 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3810,7 +3810,6 @@ CONFIG_SYS_SPI_MXC_WAIT CONFIG_SYS_SPI_RTC_DEVID CONFIG_SYS_SPI_ST_ENABLE_WP_PIN CONFIG_SYS_SPI_U_BOOT_SIZE -CONFIG_SYS_SPI_WRITE_TOUT CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SPL_LEN CONFIG_SYS_SPL_MALLOC_SIZE |