diff options
| author | Rick Chen <rick@andestech.com> | 2019-08-29 10:30:13 +0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-09-03 09:31:03 +0800 |
| commit | a8323d1816c978c012ea2fbbc844f0cbd5c82bdc (patch) | |
| tree | 916202c8a8bc70781a2b6bf713ca0c28f8ac3405 | |
| parent | edf0acb3b462732cc236f2a8d00abb82abebf38d (diff) | |
riscv: ax25: add imply v5l2 cache controller
Select the v5l2 UCLASS_CACHE driver for ax25.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| -rw-r--r-- | arch/riscv/cpu/ax25/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index f4b59cb71d..d411a79c21 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -6,6 +6,7 @@ config RISCV_NDS imply RISCV_TIMER imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE) + imply V5L2_CACHE help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. |