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authorLaurentiu Tudor <laurentiu.tudor@nxp.com>2019-10-18 09:01:54 +0000
committerPriyanka Jain <priyanka.jain@nxp.com>2019-11-08 11:13:38 +0530
commitab04dee542f6342d79460c2f6919c49caac89d2a (patch)
treef2a45d34e8da5c3d815f24d10d3dd2f4af406b07
parente33938acc93eb961e9ae2be060fb43553128c709 (diff)
fsl-layerscape: add missing SATA3 and SATA4 base addresses
LX2160A chips have 4 sata controllers. Add missing base addresses for SATA3 and SATA4. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 4f050470dd..0e4bf331fd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -87,6 +87,8 @@
/* SATA */
#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000)
#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)
+#define AHCI_BASE_ADDR3 (CONFIG_SYS_IMMR + 0x02220000)
+#define AHCI_BASE_ADDR4 (CONFIG_SYS_IMMR + 0x02230000)
/* QDMA */
#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000)