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authorTom Rini <trini@konsulko.com>2015-10-16 20:21:04 -0400
committerTom Rini <trini@konsulko.com>2015-10-16 20:21:04 -0400
commitac6a53219a1bf5bd30b754d6d3f04f26e3921d15 (patch)
tree1d4fa108f8ea97108537e1bb282801359c8540ec
parent4b8cdd484c51bb05b47cc83c634ba4a4043aa997 (diff)
parent3790a8c66266de6361c8be1544d244f8adb71fb9 (diff)
Merge git://git.denx.de/u-boot-socfpga
-rw-r--r--arch/arm/dts/socfpga_cyclone5_socdk.dts3
-rw-r--r--arch/arm/include/asm/pl310.h2
-rw-r--r--arch/arm/mach-socfpga/misc.c12
3 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 9650eb0877..546560979b 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -69,6 +69,9 @@
};
&mmc0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
cd-gpios = <&portb 18 0>;
vmmc-supply = <&regulator_3_3v>;
vqmmc-supply = <&regulator_3_3v>;
diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index de7650eae7..d588f94350 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -17,6 +17,8 @@
#define L2X0_CTRL_EN 1
#define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22)
+#define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28)
+#define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29)
struct pl310_regs {
u32 pl310_cache_id;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 0940cc5a4f..bbd31ef7b5 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -52,6 +52,18 @@ void enable_caches(void)
#endif
}
+void v7_outer_cache_enable(void)
+{
+ /* disable the L2 cache */
+ writel(0, &pl310->pl310_ctrl);
+
+ /* enable BRESP, instruction and data prefetch, full line of zeroes */
+ setbits_le32(&pl310->pl310_aux_ctrl,
+ L310_AUX_CTRL_DATA_PREFETCH_MASK |
+ L310_AUX_CTRL_INST_PREFETCH_MASK |
+ L310_SHARED_ATT_OVERRIDE_ENABLE);
+}
+
/*
* DesignWare Ethernet initialization
*/