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authorAnatolij Gustschin <agust@denx.de>2007-07-26 15:08:01 +0200
committerStefan Roese <sr@denx.de>2007-07-26 15:08:01 +0200
commitb66091de6c7390620312c2501db23d8391e7cabb (patch)
tree30b069603610b4894d8bcdfb05c7c9a165a96e2d
parent9f24a808f17fc0f37b7fb4805f734741335caecc (diff)
ppc4xx: lwmon5: Update Lime initialization
Change Lime SDRAM initialization to now support 100MHz and 133MHz (if enabled). Also the framebuffer is initialized to display a blue rectangle with a white border. Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
-rw-r--r--board/lwmon5/lwmon5.c62
-rw-r--r--include/configs/lwmon5.h16
2 files changed, 73 insertions, 5 deletions
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index 66cef2fdd6..830ec1911f 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -221,8 +221,8 @@ int misc_init_r(void)
udelay(500);
gpio_write_bit(CFG_GPIO_LIME_RST, 1);
- /* Lime memory clock adjusted to 133MHz */
- out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ);
+ /* Lime memory clock adjusted to 100MHz */
+ out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ);
/* Wait untill time expired. Because of requirements in lime manual */
udelay(300);
/* Write lime controller memory parameters */
@@ -237,6 +237,64 @@ int misc_init_r(void)
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
+ /*
+ * Init display controller
+ */
+ /* Setup dot clock (internal PLL, division rate 1/16) */
+ out_be32((void *)0xc1fd0100, 0x00000f00);
+
+ /* Lime L0 init (16 bpp, 640x480) */
+ out_be32((void *)0xc1fd0020, 0x801401df);
+ out_be32((void *)0xc1fd0024, 0x0);
+ out_be32((void *)0xc1fd0028, 0x0);
+ out_be32((void *)0xc1fd002c, 0x0);
+ out_be32((void *)0xc1fd0110, 0x0);
+ out_be32((void *)0xc1fd0114, 0x0);
+ out_be32((void *)0xc1fd0118, 0x01df0280);
+
+ /* Display timing init */
+ out_be32((void *)0xc1fd0004, 0x031f0000);
+ out_be32((void *)0xc1fd0008, 0x027f027f);
+ out_be32((void *)0xc1fd000c, 0x015f028f);
+ out_be32((void *)0xc1fd0010, 0x020c0000);
+ out_be32((void *)0xc1fd0014, 0x01df01ea);
+ out_be32((void *)0xc1fd0018, 0x0);
+ out_be32((void *)0xc1fd001c, 0x01e00280);
+
+#if 1
+ /*
+ * Clear framebuffer using Lime's drawing engine
+ * (draw blue rect. with white border around it)
+ */
+ /* Setup mode and fbbase, xres, fg, bg */
+ out_be32((void *)0xc1ff0420, 0x8300);
+ out_be32((void *)0xc1ff0440, 0x0000);
+ out_be32((void *)0xc1ff0444, 0x0280);
+ out_be32((void *)0xc1ff0480, 0x7fff);
+ out_be32((void *)0xc1ff0484, 0x0000);
+ /* Reset clipping rectangle */
+ out_be32((void *)0xc1ff0454, 0x0000);
+ out_be32((void *)0xc1ff0458, 0x0280);
+ out_be32((void *)0xc1ff045c, 0x0000);
+ out_be32((void *)0xc1ff0460, 0x01e0);
+ /* Draw white rect. */
+ out_be32((void *)0xc1ff04a0, 0x09410000);
+ out_be32((void *)0xc1ff04a0, 0x00000000);
+ out_be32((void *)0xc1ff04a0, 0x01e00280);
+ udelay(2000);
+ /* Draw blue rect. */
+ out_be32((void *)0xc1ff0480, 0x001f);
+ out_be32((void *)0xc1ff04a0, 0x09410000);
+ out_be32((void *)0xc1ff04a0, 0x00010001);
+ out_be32((void *)0xc1ff04a0, 0x01de027e);
+#endif
+ /* Display enable, L0 layer */
+ out_be32((void *)0xc1fd0100, 0x80010f00);
+
+ /* TFT-LCD enable - PWM duty, lamp on */
+ out_be32((void *)0xc4000024, 0x64);
+ out_be32((void *)0xc4000020, 0x701);
+
return 0;
}
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 55e2c94d6d..b09b47830a 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -341,14 +341,24 @@
* Graphics (Fujitsu Lime)
*----------------------------------------------------------------------*/
/* SDRAM Clock frequency adjustment register */
-#define CFG_LIME_SDRAM_CLOCK 0xC1FC0000
-/* Lime Clock frequency is to set 133MHz */
+#define CFG_LIME_SDRAM_CLOCK 0xC1FC0038
+/* Lime Clock frequency is to set 100MHz */
+#define CFG_LIME_CLOCK_100MHZ 0x00000
+#if 0
+/* Lime Clock frequency for 133MHz */
#define CFG_LIME_CLOCK_133MHZ 0x10000
+#endif
/* SDRAM Parameter register */
#define CFG_LIME_MMR 0xC1FCFFFC
-/* SDRAM parameter value */
+/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
+ and pixel flare on display when 133MHz was configured. According to
+ SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
+#ifdef CFG_LIME_CLOCK_133MHZ
+#define CFG_LIME_MMR_VALUE 0x414FB7F3
+#else
#define CFG_LIME_MMR_VALUE 0x414FB7F2
+#endif
/*-----------------------------------------------------------------------
* GPIO Setup