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| author | Yinbo Zhu <yinbo.zhu@nxp.com> | 2019-10-15 17:20:40 +0800 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2019-11-25 11:54:26 +0530 |
| commit | b73d5379c534f5419c60e9d10c200972ad627f10 (patch) | |
| tree | 5c7a381e9371d7ef84d1cd3e34991bf14c120760 | |
| parent | 9a0cbae22a613dfd55e15565785749b74c19fdf0 (diff) | |
arch: powerpc: add eSDHC node to p1020 dts
Add eSDHC node to p1020 dts
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| -rw-r--r-- | arch/powerpc/dts/p1020-post.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 1e5e67804b..fb3b203a24 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -24,6 +24,13 @@ single-cpu-affinity; last-interrupt-source = <255>; }; + + esdhc: esdhc@2e000 { + compatible = "fsl,esdhc"; + reg = <0x2e000 0x1000>; + /* Filled in by U-Boot */ + clock-frequency = <0>; + }; }; /* PCIe controller base address 0x9000 */ |