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authorMarek Vasut <marex@denx.de>2019-04-16 14:19:34 +0200
committerMarek Vasut <marex@denx.de>2019-04-29 10:08:55 +0200
commitc1d4b464c8b8826b1d8a6d84ee5202f71ce933d1 (patch)
tree5b522270674ff21cca254a209348725c36a2c6fc
parent8df653c32545171ecede4b740e38e8a4af4ed9eb (diff)
ARM: socfpga: Disable bridges in SPL unless booting from FPGA
Disable bridges between L3 Main switch and FPGA unless booting from FPGA and keep them disabled to prevent glitches and possible hangs of the L3 Main switch. The current version of the code could have enabled the bridges between the L3 Main switch and FPGA for a short period of time in board_init_f() in case the FPGA was programmed and then again disable them at the end of board_init_f(). Replace this with a code which only sets up the handoff registers and let the user enable the bridges later on. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
-rw-r--r--arch/arm/mach-socfpga/spl_gen5.c8
1 files changed, 3 insertions, 5 deletions
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 9dd0afb4bc..bd2a9fe5ae 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -175,8 +175,9 @@ void board_init_f(ulong dummy)
sysmgr_pinmux_init();
sysmgr_config_warmrstcfgio(0);
- /* De-assert reset for bridges based on handoff */
- socfpga_bridges_reset(0);
+ /* De-assert reset for peripherals and bridges based on handoff */
+ reset_deassert_peripherals_handoff();
+ socfpga_bridges_set_handoff_regs(true, true, true);
debug("Unfreezing/Thaw all I/O banks\n");
/* unfreeze / thaw all IO banks */
@@ -205,7 +206,4 @@ void board_init_f(ulong dummy)
debug("DRAM init failed: %d\n", ret);
hang();
}
-
- if (!socfpga_is_booting_from_fpga())
- socfpga_bridges_reset(1);
}