diff options
| author | Emil Medve <Emilian.Medve@freescale.com> | 2010-08-31 22:57:43 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-10-07 09:49:47 -0500 |
| commit | c2b3b6408bb011a618f67aeec1928482b679b319 (patch) | |
| tree | ea4b01dbb0d71aee57f66dfbd10d77abf9e1624f | |
| parent | 3addcb9343dbf1d9c8465210a887180edc326270 (diff) | |
powerpc/corenet_ds: Various updates to initial env cfg
* Make the U-Boot update command sequence conditional. Helps prevent
accidental erasing if an upload or previous step fails
* Make it easier to update other FLASH banks
* Enable DDR controller cache line interleaving and bank cs0/cs1 by default
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| -rw-r--r-- | include/configs/corenet_ds.h | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index d223a4d73b..6486869694 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -607,14 +607,17 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ + "bank_intlv=cs0_cs1\0" \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "ubootaddr=" MK_STR(TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=p4080ds/ramdisk.uboot\0" \ |