diff options
| author | Giulio Benetti <giulio.benetti@benettiengineering.com> | 2020-04-08 17:10:09 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2020-04-18 12:54:43 +0200 |
| commit | caac71b725755abbbb2fb23f4da3bdedb88d507e (patch) | |
| tree | 0efd26b48eb7c3ecad7feee17de2070230ae4d7c | |
| parent | d303f9c356de3628d432195e6ebff00511bc15cc (diff) | |
clk: imx: clk-imxrt1050: setup PLL5 for video in non-SPL
mxsfb needs PLL5 as source, so let's setup it at its default frequency
specified in RM(650Mhz).
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
| -rw-r--r-- | drivers/clk/imx/clk-imxrt1050.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index e33d426363..bb12644605 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -238,9 +238,9 @@ static int imxrt1050_clk_probe(struct udevice *dev) clk_dm(IMXRT1050_CLK_LCDIF, imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28)); -#ifdef CONFIG_SPL_BUILD struct clk *clk, *clk1; +#ifdef CONFIG_SPL_BUILD /* bypass pll1 before setting its rate */ clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk); clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1); @@ -271,7 +271,14 @@ static int imxrt1050_clk_probe(struct udevice *dev) clk_get_by_id(IMXRT1050_CLK_PLL3_BYPASS, &clk1); clk_set_parent(clk1, clk); +#else + /* Set PLL5 for LCDIF to its default 650Mhz */ + clk_get_by_id(IMXRT1050_CLK_PLL5_VIDEO, &clk); + clk_enable(clk); + clk_set_rate(clk, 650000000UL); + clk_get_by_id(IMXRT1050_CLK_PLL5_BYPASS, &clk1); + clk_set_parent(clk1, clk); #endif return 0; |