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authorMichal Simek <michal.simek@xilinx.com>2018-07-13 17:00:13 +0200
committerMichal Simek <michal.simek@xilinx.com>2018-07-19 10:49:55 +0200
commitcae39ae365ed98b7cd0805fcb57ca4ee280b5ebe (patch)
tree417bc42b9fac7a09e97fa30439da142fadf28e94
parent0d832b322109e76953bc58e4d2723d2c73dfb604 (diff)
sysreset: Add support for Microblaze soft reset jump
Microblaze is storing reset vector at address 0x0. It means soft reset can be done by just jumping to this address. This code was in platform code but sysreset interface is providing enough capabilities to have more options how to reset the system. It can go from gpio reset through watchdog reset till soft reset. The driver has not compatible string because this is cpu specific and DM core is not able to detect compatible string in DT root that's why this driver will be instantiated from platform code by calling device_bind_driver(gd->dm_root, "mb_soft_reset", "reset_soft", NULL); It should be bind as the last reset method to ensure that hw reset is called before this. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
-rw-r--r--drivers/sysreset/Kconfig6
-rw-r--r--drivers/sysreset/Makefile1
-rw-r--r--drivers/sysreset/sysreset_microblaze.c30
3 files changed, 37 insertions, 0 deletions
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index cec612ed50..f2524c18b7 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -23,6 +23,12 @@ config SYSRESET_GPIO
example on Microblaze where reset logic can be controlled via GPIO
pin which triggers cpu reset.
+config SYSRESET_MICROBLAZE
+ bool "Enable support for Microblaze soft reset"
+ depends on MICROBLAZE
+ help
+ This is soft reset on Microblaze which does jump to 0x0 address.
+
config SYSRESET_PSCI
bool "Enable support for PSCI System Reset"
depends on ARM_PSCI_FW
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index ca533cfefa..223a0716f0 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -4,6 +4,7 @@
obj-$(CONFIG_SYSRESET) += sysreset-uclass.o
obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
+obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
diff --git a/drivers/sysreset/sysreset_microblaze.c b/drivers/sysreset/sysreset_microblaze.c
new file mode 100644
index 0000000000..514c95817f
--- /dev/null
+++ b/drivers/sysreset/sysreset_microblaze.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Xilinx, Inc. - Michal Simek
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <linux/err.h>
+
+static int microblaze_sysreset_request(struct udevice *dev,
+ enum sysreset_t type)
+{
+ puts("Microblaze soft reset sysreset\n");
+ __asm__ __volatile__ (" mts rmsr, r0;" \
+ "bra r0");
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops microblaze_sysreset = {
+ .request = microblaze_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_microblaze) = {
+ .id = UCLASS_SYSRESET,
+ .name = "mb_soft_reset",
+ .ops = &microblaze_sysreset,
+};