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authorThomas Abraham <thomas.ab@samsung.com>2016-04-23 22:18:11 +0530
committerMinkyu Kang <mk7.kang@samsung.com>2016-05-25 10:00:19 +0900
commitcf75cdf96ef288410222737eca98cf28cdbafbe2 (patch)
tree0343c9911c499e14d5afeb3028764b74e3a7ddbe
parent5ab6c4df27c9188251ff43a536c90ede57ba48fe (diff)
serial: s5p: use clock api to get clock rate
On Exynos platforms that support clock driver API, allow the driver to use clock api get the SCLK clock rate. Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
-rw-r--r--drivers/serial/serial_s5p.c15
1 files changed, 14 insertions, 1 deletions
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 8590dfd418..cb55c5ab71 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -17,6 +17,7 @@
#include <asm/arch/clk.h>
#include <asm/arch/uart.h>
#include <serial.h>
+#include <clk.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -90,7 +91,19 @@ int s5p_serial_setbrg(struct udevice *dev, int baudrate)
{
struct s5p_serial_platdata *plat = dev->platdata;
struct s5p_uart *const uart = plat->reg;
- u32 uclk = get_uart_clk(plat->port_id);
+ u32 uclk;
+
+#ifdef CONFIG_CLK_EXYNOS
+ struct udevice *clk_dev;
+ u32 ret;
+
+ ret = clk_get_by_index(dev, 1, &clk_dev);
+ if (ret < 0)
+ return ret;
+ uclk = clk_get_periph_rate(clk_dev, ret);
+#else
+ uclk = get_uart_clk(plat->port_id);
+#endif
s5p_serial_baud(uart, uclk, baudrate);