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author | Melin Tomas <tomas.melin@vaisala.com> | 2019-06-28 12:08:40 +0000 |
---|---|---|
committer | Heiko Schocher <hs@denx.de> | 2019-07-09 07:02:11 +0200 |
commit | d3826fb052af9e6df22abaefb1b0c7496e469f9e (patch) | |
tree | b5dea82b58a7ef9ec570e53cbafa3ddbd9a9988d | |
parent | 5324e8ef6c3d6b6183b3aadeadeeb7822b4fd68a (diff) |
xilinx_xiic: Fix transfer initialisation
Prior to starting a new transfer, conditionally wait for bus to not
be busy.
Reinitialise controller as otherwise operation is not stable.
For reference, see linux kernel
commit 9656eeebf3f1 ("i2c: Revert i2c: xiic: Do not reset controller before every transfer")
hs: Fixed DOS line endings
added missing '\n'
Fixed git commit description style
Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
-rw-r--r-- | drivers/i2c/xilinx_xiic.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/i2c/xilinx_xiic.c b/drivers/i2c/xilinx_xiic.c index e4ca0ab936..5ce0f869c7 100644 --- a/drivers/i2c/xilinx_xiic.c +++ b/drivers/i2c/xilinx_xiic.c @@ -266,8 +266,20 @@ static void xiic_reinit(struct xilinx_xiic_priv *priv) static int xilinx_xiic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) { + struct xilinx_xiic_priv *priv = dev_get_priv(dev); int ret = 0; + ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET, + XIIC_SR_BUS_BUSY_MASK, false, 1000, true); + + if (ret == -ETIMEDOUT) + dev_err(dev, "timeout waiting for bus not busy condition\n"); + + if (ret) + return ret; + + xiic_reinit(priv); + for (; nmsgs > 0; nmsgs--, msg++) { if (msg->flags & I2C_M_RD) ret = xilinx_xiic_read_common(dev, msg, nmsgs); |