diff options
author | Alison Wang <b18965@freescale.com> | 2014-12-09 17:38:02 +0800 |
---|---|---|
committer | York Sun <yorksun@freescale.com> | 2014-12-11 09:40:14 -0800 |
commit | d612f0ab34b27be4ad50b1236fbd6c84450997f1 (patch) | |
tree | d175f1c357b997510468ebd220712f0a4a414c03 | |
parent | 4c59ab9cfbdd34f5ef1e960470accdc63e2483c1 (diff) |
arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board
This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
-rw-r--r-- | arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 | ||||
-rw-r--r-- | board/freescale/ls1021aqds/MAINTAINERS | 1 | ||||
-rw-r--r-- | board/freescale/ls1021aqds/ls1021aqds.c | 8 | ||||
-rw-r--r-- | board/freescale/ls1021atwr/MAINTAINERS | 1 | ||||
-rw-r--r-- | board/freescale/ls1021atwr/ls1021atwr.c | 14 | ||||
-rw-r--r-- | configs/ls1021aqds_qspi_defconfig | 3 | ||||
-rw-r--r-- | configs/ls1021atwr_qspi_defconfig | 3 | ||||
-rw-r--r-- | include/configs/ls1021aqds.h | 34 | ||||
-rw-r--r-- | include/configs/ls1021atwr.h | 28 |
9 files changed, 93 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index b0c267cfc2..98b268dffe 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -98,6 +98,7 @@ struct ccsr_gur { #define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 +#define SCFG_QSPI_CLKSEL 0xc0100000 /* Supplemental Configuration Unit */ struct ccsr_scfg { diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS index 962176b533..7a704cf25f 100644 --- a/board/freescale/ls1021aqds/MAINTAINERS +++ b/board/freescale/ls1021aqds/MAINTAINERS @@ -7,3 +7,4 @@ F: configs/ls1021aqds_nor_defconfig F: configs/ls1021aqds_ddr4_nor_defconfig F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig F: configs/ls1021aqds_sdcard_defconfig +F: configs/ls1021aqds_qspi_defconfig diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 9eab42d6c7..9fcd129883 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -34,7 +34,9 @@ enum { int checkboard(void) { +#ifndef CONFIG_QSPI_BOOT char buf[64]; +#endif #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) u8 sw; #endif @@ -61,12 +63,14 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); #endif +#ifndef CONFIG_QSPI_BOOT printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", QIXIS_READ(id), QIXIS_READ(arch)); printf("FPGA: v%d (%s), build %d\n", (int)QIXIS_READ(scver), qixis_read_tag(buf), (int)qixis_read_minor()); +#endif return 0; } @@ -164,6 +168,10 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif + /* Workaround for the issue that DDR could not respond to * barrier transaction which is generated by executing DSB/ISB * instruction. Set CCI-400 control override register to diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS index 2312e003cd..91767065fa 100644 --- a/board/freescale/ls1021atwr/MAINTAINERS +++ b/board/freescale/ls1021atwr/MAINTAINERS @@ -6,3 +6,4 @@ F: include/configs/ls1021atwr.h F: configs/ls1021atwr_nor_defconfig F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig F: configs/ls1021atwr_sdcard_defconfig +F: configs/ls1021atwr_qspi_defconfig diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 0faee0afad..5c3a282b30 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -72,6 +72,7 @@ struct cpld_data { u8 rev2; /* Reserved */ }; +#ifndef CONFIG_QSPI_BOOT static void convert_serdes_mux(int type, int need_reset); void cpld_show(void) @@ -107,11 +108,14 @@ void cpld_show(void) in_8(&cpld_data->serdes_mux)); #endif } +#endif int checkboard(void) { puts("Board: LS1021ATWR\n"); +#ifndef CONFIG_QSPI_BOOT cpld_show(); +#endif return 0; } @@ -220,6 +224,7 @@ int board_eth_init(bd_t *bis) } #endif +#ifndef CONFIG_QSPI_BOOT int config_serdes_mux(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -251,6 +256,7 @@ int config_serdes_mux(void) return 0; } +#endif int board_early_init_f(void) { @@ -269,6 +275,10 @@ int board_early_init_f(void) out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); #endif +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif + return 0; } @@ -305,8 +315,10 @@ int board_init(void) #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); +#ifndef CONFIG_QSPI_BOOT config_serdes_mux(); #endif +#endif #ifdef CONFIG_U_QE u_qe_init(); @@ -354,6 +366,7 @@ u16 flash_read16(void *addr) return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); } +#ifndef CONFIG_QSPI_BOOT static void convert_flash_bank(char bank) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); @@ -536,3 +549,4 @@ U_BOOT_CMD( " -change lane C & lane D to PCIeX2\n" "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n" ); +#endif diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig new file mode 100644 index 0000000000..05ec8e6502 --- /dev/null +++ b/configs/ls1021aqds_qspi_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021AQDS=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig new file mode 100644 index 0000000000..611f6e846a --- /dev/null +++ b/configs/ls1021atwr_qspi_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021ATWR=y diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 4496871ff3..6f8b43f351 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -37,8 +37,14 @@ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#define CONFIG_QIXIS_I2C_ACCESS +#else #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#endif #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg @@ -73,6 +79,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_MONITOR_LEN 0x80000 #endif +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_TEXT_BASE 0x40010000 +#define CONFIG_SYS_NO_FLASH +#endif + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x67f80000 #endif @@ -112,6 +123,7 @@ unsigned long get_board_ddr_clk(void); /* * IFC Definitions */ +#ifndef CONFIG_QSPI_BOOT #define CONFIG_FSL_IFC #define CONFIG_SYS_FLASH_BASE 0x60000000 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE @@ -204,6 +216,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#endif /* * QIXIS Definitions @@ -316,6 +329,18 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +/* QSPI */ +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_FSL_QSPI +#define QSPI0_AMBA_BASE 0x40000000 +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#endif + /* * USB */ @@ -394,7 +419,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING +#ifdef CONFIG_QSPI_BOOT +#undef CONFIG_CMD_IMLS +#else #define CONFIG_CMD_IMLS +#endif #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 @@ -458,6 +487,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 972becd9a4..a3271fed05 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -67,6 +67,11 @@ #define CONFIG_SYS_MONITOR_LEN 0x80000 #endif +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_TEXT_BASE 0x40010000 +#define CONFIG_SYS_NO_FLASH +#endif + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x67f80000 #endif @@ -90,6 +95,7 @@ /* * IFC Definitions */ +#ifndef CONFIG_QSPI_BOOT #define CONFIG_FSL_IFC #define CONFIG_SYS_FLASH_BASE 0x60000000 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE @@ -133,6 +139,7 @@ #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #define CONFIG_SYS_WRITE_SWAPPED_DATA +#endif /* CPLD */ @@ -216,6 +223,18 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +/* QSPI */ +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_FSL_QSPI +#define QSPI0_AMBA_BASE 0x40000000 +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#endif + /* * Video */ @@ -287,7 +306,11 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING +#ifdef CONFIG_QSPI_BOOT +#undef CONFIG_CMD_IMLS +#else #define CONFIG_CMD_IMLS +#endif #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 @@ -350,6 +373,11 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x20000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |