diff options
| author | Heiko Schocher <hs@denx.de> | 2015-09-25 12:31:48 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-10-30 15:08:39 +0100 |
| commit | d62f2f8cdfd7ee9bd1e61fa1e71723340f870071 (patch) | |
| tree | 8ad8cf846c4f06ef01fcbed1cf4756b82a443ee3 | |
| parent | 3e020f03e94ffbb5ffda0a4579cf0f3dcfbe0fec (diff) | |
arm, imx: add some gpr register defines
add some missing gpr register defines.
Signed-off-by: Heiko Schocher <hs@denx.de>
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 74512ac08e..0e112e9d31 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -413,10 +413,37 @@ struct src { }; /* GPR1 bitfields */ +#define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30) +#define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28) +#define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27) +#define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26) +#define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25) +#define IOMUXC_GPR1_DPI_OFF BIT(24) +#define IOMUXC_GPR1_EXC_MON_SLVE BIT(22) #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET) +#define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20) +#define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19) +#define IOMUXC_GPR1_PCIE_TEST_PD BIT(18) +#define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17) +#define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16) +#define IOMUXC_GPR1_USB_EXP_MODE BIT(15) +#define IOMUXC_GPR1_PCIE_INT BIT(14) #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET) +#define IOMUXC_GPR1_GINT BIT(12) +#define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10) +#define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10) +#define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10) +#define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10) +#define IOMUXC_GPR1_ACT_CS3 BIT(9) +#define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7) +#define IOMUXC_GPR1_ACT_CS2 BIT(6) +#define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4) +#define IOMUXC_GPR1_ACT_CS1 BIT(3) +#define IOMUXC_GPR1_ADDRS0_OFFSET (1) +#define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1) +#define IOMUXC_GPR1_ACT_CS0 BIT(0) /* GPR3 bitfields */ #define IOMUXC_GPR3_GPU_DBG_OFFSET 29 @@ -465,6 +492,14 @@ struct src { #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET) +/* gpr12 bitfields */ +#define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27) +#define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26) +#define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25) +#define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24) +#define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12) +#define IOMUXC_GPR12_PCIE_CTL_2 BIT(10) +#define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4) struct iomuxc { #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) |