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authorStefan Agner <stefan.agner@toradex.com>2016-08-03 13:08:55 -0700
committerTom Rini <trini@konsulko.com>2016-08-12 09:22:15 -0400
commitda91cfed54ec44d88f93af2adfbdeada8ab4403e (patch)
tree0f33c7db11beb3a000cf119a7b8905b2597fbec0
parent2651a052d8ab13a8609c51053ba0f693f1be3295 (diff)
ARM: non-sec: flush code cacheline aligned
Flush operations need to be cacheline aligned to take effect, make sure to flush always complete cachelines. This avoids messages such as: CACHE: Misaligned operation at range [00900000, 009004d9] Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
-rw-r--r--arch/arm/cpu/armv7/virt-v7.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 9c533060b8..d33e5c61a9 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -54,10 +54,12 @@ static void relocate_secure_section(void)
{
#ifdef CONFIG_ARMV7_SECURE_BASE
size_t sz = __secure_end - __secure_start;
+ unsigned long szflush = ALIGN(sz + 1, CONFIG_SYS_CACHELINE_SIZE);
memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz);
+
flush_dcache_range(CONFIG_ARMV7_SECURE_BASE,
- CONFIG_ARMV7_SECURE_BASE + sz + 1);
+ CONFIG_ARMV7_SECURE_BASE + szflush);
protect_secure_section();
invalidate_icache_all();
#endif