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authorMarek Vasut <marex@denx.de>2020-03-23 02:09:01 +0100
committermarex <marex@desktop.lan>2020-05-01 12:35:21 +0200
commitdd90c2e1ea0a7abdfa501e604523c23d6f77ffdd (patch)
tree305d239beaf6b0afda4583e1b034c43a71fce593
parent83858d87954627af7a576ccc7c93034b055faa7b (diff)
net: dwc_eth_qos: Flush the RX descriptors on init
Currently the code only flushes the first RX descriptor, not every entry in the RX descriptor ring. Fix this, to make sure the DMA engine can pick the RX descriptors correctly. Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stephen Warren <swarren@nvidia.com>
-rw-r--r--drivers/net/dwc_eth_qos.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index e2fb690a1c..e33f3045fe 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1289,8 +1289,8 @@ static int eqos_start(struct udevice *dev)
rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
(i * EQOS_MAX_PACKET_SIZE));
rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
+ eqos->config->ops->eqos_flush_desc(rx_desc);
}
- eqos->config->ops->eqos_flush_desc(eqos->descs);
writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);