diff options
| author | Dave Gerlach <d-gerlach@ti.com> | 2018-03-17 13:24:30 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-04-06 17:04:33 -0400 |
| commit | e18945ad22eb2a8baad1a2dbc8c541411ac9528b (patch) | |
| tree | af4c5e4eee88566d417f41b9e9955286f7ab3b43 | |
| parent | 7619badb9c3776327724b49948cf17ae9ca8edc2 (diff) | |
am43xx: Do not allow EMIF to control DDR_RESET in rtconly config
Prevent EMIF control of DDR_RESET line on DDR3 am43xx platforms for
am43xx_evm_rtconly_config. Without this DDR is unstable and can become
corrupted after multiple iterations of RTC+DDR mode.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[j-keerthy@ti.com Ported to latest master branch]
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
| -rw-r--r-- | arch/arm/mach-omap2/am33xx/emif4.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c index 68c7705178..9b429c9262 100644 --- a/arch/arm/mach-omap2/am33xx/emif4.c +++ b/arch/arm/mach-omap2/am33xx/emif4.c @@ -95,8 +95,13 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) +#ifndef CONFIG_SPL_RTC_DDR_SUPPORT /* Allow EMIF to control DDR_RESET */ writel(0x00000000, &ddrctrl->ddrioctrl); +#else + /* Override EMIF DDR_RESET control */ + writel(0x80000000, &ddrctrl->ddrioctrl); +#endif /* CONFIG_SPL_RTC_DDR_SUPPORT */ #endif /* Program EMIF instance */ |