summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorJan Kiszka <jan.kiszka@siemens.com>2020-06-23 13:15:10 +0200
committerLokesh Vutla <lokeshvutla@ti.com>2020-08-11 10:18:27 +0530
commite1c36685949ebad091f5807f980cae7be5d4ba23 (patch)
tree9d8d69229b0efa1a5693d5358fedf54f6d865982
parentd388f360edacf6292a5ee7a37474799a3fe9f2ac (diff)
arm: dts: k3: Add RTI watchdogs
Add DT entries for main domain watchdog0 and 1 instances on the J721e well as RTI1-based watchdog on the AM65x. RTI0 does not work for this purpose on the AM65x, so leave it out. On AM65x, we mark the power-domain as shared because RTI firmware such as https://github.com/siemens/k3-rti-wdt may request it as well in order to prevent accidental shutdown of the watchdog. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
-rw-r--r--arch/arm/dts/k3-am65-mcu.dtsi9
-rw-r--r--arch/arm/dts/k3-j721e-main.dtsi18
2 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi
index 1355685839..9717cae0a8 100644
--- a/arch/arm/dts/k3-am65-mcu.dtsi
+++ b/arch/arm/dts/k3-am65-mcu.dtsi
@@ -230,4 +230,13 @@
};
};
};
+
+ mcu_rti1: rti@40610000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x0 0x40610000 0x0 0x100>;
+ clocks = <&k3_clks 135 0>;
+ power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
+ assigned-clocks = <&k3_clks 135 0>;
+ assigned-clock-parents = <&k3_clks 135 4>;
+ };
};
diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index 1433932e7f..a285b1afa8 100644
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -543,4 +543,22 @@
clocks = <&k3_clks 193 0>;
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
};
+
+ watchdog0: watchdog@2200000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x0 0x2200000 0x0 0x100>;
+ clocks = <&k3_clks 252 1>;
+ power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 252 1>;
+ assigned-clock-parents = <&k3_clks 252 5>;
+ };
+
+ watchdog1: watchdog@2210000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x0 0x2210000 0x0 0x100>;
+ clocks = <&k3_clks 253 1>;
+ power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 253 1>;
+ assigned-clock-parents = <&k3_clks 253 5>;
+ };
};