diff options
| author | Lokesh Vutla <lokeshvutla@ti.com> | 2019-10-07 19:26:37 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-10-25 17:33:21 -0400 |
| commit | ec2fa9f76e892b9fd38fe39c564bf9348ab135bd (patch) | |
| tree | d4fa23d51738f3a4cb3667bbd89a1ff4ec3ce66a | |
| parent | 3bb3f266ee617384bb282a6818f675b5aca5c371 (diff) | |
arm: dts: k3-j721e: Add ddr node
Use the 3733MTs DDR configuration that is auto generated from
DDR_Regconfig tool.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
| -rw-r--r-- | arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi | 2195 | ||||
| -rw-r--r-- | arch/arm/dts/k3-j721e-ddr.dtsi | 2212 | ||||
| -rw-r--r-- | arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 2 |
3 files changed, 4409 insertions, 0 deletions
diff --git a/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi b/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi new file mode 100644 index 0000000000..135b6193a9 --- /dev/null +++ b/arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi @@ -0,0 +1,2195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool, Revision: 0.1.0 + * This file was generated on 09/06/2019 +*/ + +#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FREQUENCY_1 933000000 +#define DDRSS_PLL_FREQUENCY_2 933000000 + +#define DDRSS_CTL_00_DATA 0x00000B00 +#define DDRSS_CTL_01_DATA 0x00000000 +#define DDRSS_CTL_02_DATA 0x00000000 +#define DDRSS_CTL_03_DATA 0x00000000 +#define DDRSS_CTL_04_DATA 0x00000000 +#define DDRSS_CTL_05_DATA 0x00000000 +#define DDRSS_CTL_06_DATA 0x00000000 +#define DDRSS_CTL_07_DATA 0x00002710 +#define DDRSS_CTL_08_DATA 0x000186A0 +#define DDRSS_CTL_09_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_11_DATA 0x0005B18F +#define DDRSS_CTL_12_DATA 0x0038EF90 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000E94 +#define DDRSS_CTL_15_DATA 0x0005B18F +#define DDRSS_CTL_16_DATA 0x0038EF90 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000E94 +#define DDRSS_CTL_19_DATA 0x01010000 +#define DDRSS_CTL_20_DATA 0x02011001 +#define DDRSS_CTL_21_DATA 0x02010000 +#define DDRSS_CTL_22_DATA 0x00020100 +#define DDRSS_CTL_23_DATA 0x0000000A +#define DDRSS_CTL_24_DATA 0x00000019 +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x02020200 +#define DDRSS_CTL_28_DATA 0x00004B4B +#define DDRSS_CTL_29_DATA 0x00100000 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x040C0000 +#define DDRSS_CTL_35_DATA 0x10401040 +#define DDRSS_CTL_36_DATA 0x00050804 +#define DDRSS_CTL_37_DATA 0x09040008 +#define DDRSS_CTL_38_DATA 0x12000204 +#define DDRSS_CTL_39_DATA 0x1854007A +#define DDRSS_CTL_40_DATA 0x12003A26 +#define DDRSS_CTL_41_DATA 0x1854007A +#define DDRSS_CTL_42_DATA 0x20003A26 +#define DDRSS_CTL_43_DATA 0x000A0A09 +#define DDRSS_CTL_44_DATA 0x040006DB +#define DDRSS_CTL_45_DATA 0x1B130F04 +#define DDRSS_CTL_46_DATA 0x0E00FFCD +#define DDRSS_CTL_47_DATA 0x1B130F0E +#define DDRSS_CTL_48_DATA 0x0E00FFCD +#define DDRSS_CTL_49_DATA 0x0203040E +#define DDRSS_CTL_50_DATA 0x26040500 +#define DDRSS_CTL_51_DATA 0x08282628 +#define DDRSS_CTL_52_DATA 0x14000D0A +#define DDRSS_CTL_53_DATA 0x03010A0A +#define DDRSS_CTL_54_DATA 0x01010003 +#define DDRSS_CTL_55_DATA 0x044E4E08 +#define DDRSS_CTL_56_DATA 0x042B2B04 +#define DDRSS_CTL_57_DATA 0x00002B2B +#define DDRSS_CTL_58_DATA 0x00010100 +#define DDRSS_CTL_59_DATA 0x03010000 +#define DDRSS_CTL_60_DATA 0x00000E08 +#define DDRSS_CTL_61_DATA 0x000000BB +#define DDRSS_CTL_62_DATA 0x0000020B +#define DDRSS_CTL_63_DATA 0x00001C64 +#define DDRSS_CTL_64_DATA 0x0000020B +#define DDRSS_CTL_65_DATA 0x00001C64 +#define DDRSS_CTL_66_DATA 0x00000005 +#define DDRSS_CTL_67_DATA 0x00030000 +#define DDRSS_CTL_68_DATA 0x00830010 +#define DDRSS_CTL_69_DATA 0x00830386 +#define DDRSS_CTL_70_DATA 0x00400386 +#define DDRSS_CTL_71_DATA 0x00120103 +#define DDRSS_CTL_72_DATA 0x000E0005 +#define DDRSS_CTL_73_DATA 0x2908000E +#define DDRSS_CTL_74_DATA 0x05050129 +#define DDRSS_CTL_75_DATA 0x0401030A +#define DDRSS_CTL_76_DATA 0x041B0E0A +#define DDRSS_CTL_77_DATA 0x0E0A0401 +#define DDRSS_CTL_78_DATA 0x0001041B +#define DDRSS_CTL_79_DATA 0x000F000F +#define DDRSS_CTL_80_DATA 0x02190219 +#define DDRSS_CTL_81_DATA 0x02190219 +#define DDRSS_CTL_82_DATA 0x03050505 +#define DDRSS_CTL_83_DATA 0x03010303 +#define DDRSS_CTL_84_DATA 0x1C0A0E0A +#define DDRSS_CTL_85_DATA 0x04040E04 +#define DDRSS_CTL_86_DATA 0x1C0A0E0A +#define DDRSS_CTL_87_DATA 0x04040E04 +#define DDRSS_CTL_88_DATA 0x03010000 +#define DDRSS_CTL_89_DATA 0x00010000 +#define DDRSS_CTL_90_DATA 0x00000000 +#define DDRSS_CTL_91_DATA 0x00000000 +#define DDRSS_CTL_92_DATA 0x01000000 +#define DDRSS_CTL_93_DATA 0x80104002 +#define DDRSS_CTL_94_DATA 0x00000000 +#define DDRSS_CTL_95_DATA 0x00040005 +#define DDRSS_CTL_96_DATA 0x00000000 +#define DDRSS_CTL_97_DATA 0x00050000 +#define DDRSS_CTL_98_DATA 0x00000004 +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x00040005 +#define DDRSS_CTL_101_DATA 0x00000000 +#define DDRSS_CTL_102_DATA 0x00002EC0 +#define DDRSS_CTL_103_DATA 0x00002EC0 +#define DDRSS_CTL_104_DATA 0x00002EC0 +#define DDRSS_CTL_105_DATA 0x00002EC0 +#define DDRSS_CTL_106_DATA 0x00002EC0 +#define DDRSS_CTL_107_DATA 0x00000000 +#define DDRSS_CTL_108_DATA 0x0000051D +#define DDRSS_CTL_109_DATA 0x00071900 +#define DDRSS_CTL_110_DATA 0x00071900 +#define DDRSS_CTL_111_DATA 0x00071900 +#define DDRSS_CTL_112_DATA 0x00071900 +#define DDRSS_CTL_113_DATA 0x00071900 +#define DDRSS_CTL_114_DATA 0x00000000 +#define DDRSS_CTL_115_DATA 0x0000C6BC +#define DDRSS_CTL_116_DATA 0x00071900 +#define DDRSS_CTL_117_DATA 0x00071900 +#define DDRSS_CTL_118_DATA 0x00071900 +#define DDRSS_CTL_119_DATA 0x00071900 +#define DDRSS_CTL_120_DATA 0x00071900 +#define DDRSS_CTL_121_DATA 0x00000000 +#define DDRSS_CTL_122_DATA 0x0000C6BC +#define DDRSS_CTL_123_DATA 0x00000000 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x00000000 +#define DDRSS_CTL_126_DATA 0x00000000 +#define DDRSS_CTL_127_DATA 0x00000000 +#define DDRSS_CTL_128_DATA 0x00000000 +#define DDRSS_CTL_129_DATA 0x00000000 +#define DDRSS_CTL_130_DATA 0x00000000 +#define DDRSS_CTL_131_DATA 0x0A030500 +#define DDRSS_CTL_132_DATA 0x00040A04 +#define DDRSS_CTL_133_DATA 0x0A090000 +#define DDRSS_CTL_134_DATA 0x0A090701 +#define DDRSS_CTL_135_DATA 0x0900000E +#define DDRSS_CTL_136_DATA 0x0907010A +#define DDRSS_CTL_137_DATA 0x00000E0A +#define DDRSS_CTL_138_DATA 0x07010A09 +#define DDRSS_CTL_139_DATA 0x000E0A09 +#define DDRSS_CTL_140_DATA 0x07000401 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x08080000 +#define DDRSS_CTL_149_DATA 0x01000000 +#define DDRSS_CTL_150_DATA 0x800000C0 +#define DDRSS_CTL_151_DATA 0x800000C0 +#define DDRSS_CTL_152_DATA 0x800000C0 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00001500 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x00000001 +#define DDRSS_CTL_157_DATA 0x00000002 +#define DDRSS_CTL_158_DATA 0x0000100E +#define DDRSS_CTL_159_DATA 0x00000000 +#define DDRSS_CTL_160_DATA 0x00000000 +#define DDRSS_CTL_161_DATA 0x00000000 +#define DDRSS_CTL_162_DATA 0x00000000 +#define DDRSS_CTL_163_DATA 0x00000000 +#define DDRSS_CTL_164_DATA 0x000A0000 +#define DDRSS_CTL_165_DATA 0x000D0005 +#define DDRSS_CTL_166_DATA 0x000D0404 +#define DDRSS_CTL_167_DATA 0x00BB0176 +#define DDRSS_CTL_168_DATA 0x0E0E01D3 +#define DDRSS_CTL_169_DATA 0x017601D3 +#define DDRSS_CTL_170_DATA 0x01D300BB +#define DDRSS_CTL_171_DATA 0x01D30E0E +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x00000000 +#define DDRSS_CTL_175_DATA 0x36E40084 +#define DDRSS_CTL_176_DATA 0x330036E4 +#define DDRSS_CTL_177_DATA 0x00003333 +#define DDRSS_CTL_178_DATA 0x56000000 +#define DDRSS_CTL_179_DATA 0x27270056 +#define DDRSS_CTL_180_DATA 0x0F0F0000 +#define DDRSS_CTL_181_DATA 0x00000000 +#define DDRSS_CTL_182_DATA 0x00840606 +#define DDRSS_CTL_183_DATA 0x36E436E4 +#define DDRSS_CTL_184_DATA 0x33333300 +#define DDRSS_CTL_185_DATA 0x00000000 +#define DDRSS_CTL_186_DATA 0x00565600 +#define DDRSS_CTL_187_DATA 0x00002727 +#define DDRSS_CTL_188_DATA 0x00000F0F +#define DDRSS_CTL_189_DATA 0x06060000 +#define DDRSS_CTL_190_DATA 0x00000020 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x00000001 +#define DDRSS_CTL_193_DATA 0x00000000 +#define DDRSS_CTL_194_DATA 0x01000000 +#define DDRSS_CTL_195_DATA 0x00000001 +#define DDRSS_CTL_196_DATA 0x00000000 +#define DDRSS_CTL_197_DATA 0x00000000 +#define DDRSS_CTL_198_DATA 0x00000000 +#define DDRSS_CTL_199_DATA 0x00000000 +#define DDRSS_CTL_200_DATA 0x00000000 +#define DDRSS_CTL_201_DATA 0x00000000 +#define DDRSS_CTL_202_DATA 0x00000000 +#define DDRSS_CTL_203_DATA 0x00000000 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000000 +#define DDRSS_CTL_206_DATA 0x02000000 +#define DDRSS_CTL_207_DATA 0x01080101 +#define DDRSS_CTL_208_DATA 0x00000000 +#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x00000000 +#define DDRSS_CTL_212_DATA 0x00000000 +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x00000000 +#define DDRSS_CTL_215_DATA 0x00000000 +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000000 +#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x00000000 +#define DDRSS_CTL_221_DATA 0x00000000 +#define DDRSS_CTL_222_DATA 0x00001000 +#define DDRSS_CTL_223_DATA 0x006403E8 +#define DDRSS_CTL_224_DATA 0x00000000 +#define DDRSS_CTL_225_DATA 0x00000000 +#define DDRSS_CTL_226_DATA 0x00000000 +#define DDRSS_CTL_227_DATA 0x15110000 +#define DDRSS_CTL_228_DATA 0x00040C18 +#define DDRSS_CTL_229_DATA 0x00000000 +#define DDRSS_CTL_230_DATA 0x00000000 +#define DDRSS_CTL_231_DATA 0x00000000 +#define DDRSS_CTL_232_DATA 0x00000000 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0x00000000 +#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00030000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x00000000 +#define DDRSS_CTL_255_DATA 0x00000000 +#define DDRSS_CTL_256_DATA 0x00000000 +#define DDRSS_CTL_257_DATA 0x01000200 +#define DDRSS_CTL_258_DATA 0x00320040 +#define DDRSS_CTL_259_DATA 0x00020008 +#define DDRSS_CTL_260_DATA 0x00400100 +#define DDRSS_CTL_261_DATA 0x0038074A +#define DDRSS_CTL_262_DATA 0x01000200 +#define DDRSS_CTL_263_DATA 0x074A0040 +#define DDRSS_CTL_264_DATA 0x00000038 +#define DDRSS_CTL_265_DATA 0x005E0003 +#define DDRSS_CTL_266_DATA 0x0100005E +#define DDRSS_CTL_267_DATA 0x00000000 +#define DDRSS_CTL_268_DATA 0x01010000 +#define DDRSS_CTL_269_DATA 0x00000202 +#define DDRSS_CTL_270_DATA 0x00000FFF +#define DDRSS_CTL_271_DATA 0x1FFF1000 +#define DDRSS_CTL_272_DATA 0x01FF0000 +#define DDRSS_CTL_273_DATA 0x000101FF +#define DDRSS_CTL_274_DATA 0xFFFF0B00 +#define DDRSS_CTL_275_DATA 0x01010001 +#define DDRSS_CTL_276_DATA 0x01010101 +#define DDRSS_CTL_277_DATA 0x01180101 +#define DDRSS_CTL_278_DATA 0x00030000 +#define DDRSS_CTL_279_DATA 0x00000000 +#define DDRSS_CTL_280_DATA 0x00000000 +#define DDRSS_CTL_281_DATA 0x00000000 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000000 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00040101 +#define DDRSS_CTL_287_DATA 0x04010100 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x03030300 +#define DDRSS_CTL_291_DATA 0x00000001 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x00000000 +#define DDRSS_CTL_297_DATA 0x00000000 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00000000 +#define DDRSS_CTL_306_DATA 0x00000000 +#define DDRSS_CTL_307_DATA 0x00000000 +#define DDRSS_CTL_308_DATA 0x00000000 +#define DDRSS_CTL_309_DATA 0x00000000 +#define DDRSS_CTL_310_DATA 0x00000000 +#define DDRSS_CTL_311_DATA 0x00000000 +#define DDRSS_CTL_312_DATA 0x00000000 +#define DDRSS_CTL_313_DATA 0x01000000 +#define DDRSS_CTL_314_DATA 0x00020201 +#define DDRSS_CTL_315_DATA 0x01000101 +#define DDRSS_CTL_316_DATA 0x01010001 +#define DDRSS_CTL_317_DATA 0x00010101 +#define DDRSS_CTL_318_DATA 0x05090903 +#define DDRSS_CTL_319_DATA 0x0E081B1B +#define DDRSS_CTL_320_DATA 0x0009030E +#define DDRSS_CTL_321_DATA 0x0A0D030F +#define DDRSS_CTL_322_DATA 0x0A0D0306 +#define DDRSS_CTL_323_DATA 0x0D090006 +#define DDRSS_CTL_324_DATA 0x0100000D +#define DDRSS_CTL_325_DATA 0x07030701 +#define DDRSS_CTL_326_DATA 0x00000003 +#define DDRSS_CTL_327_DATA 0x00000000 +#define DDRSS_CTL_328_DATA 0x00010000 +#define DDRSS_CTL_329_DATA 0x00280D00 +#define DDRSS_CTL_330_DATA 0x00000001 +#define DDRSS_CTL_331_DATA 0x00030001 +#define DDRSS_CTL_332_DATA 0x00000000 +#define DDRSS_CTL_333_DATA 0x00000000 +#define DDRSS_CTL_334_DATA 0x00000000 +#define DDRSS_CTL_335_DATA 0x00000000 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x00000000 +#define DDRSS_CTL_339_DATA 0x00000000 +#define DDRSS_CTL_340_DATA 0x01000000 +#define DDRSS_CTL_341_DATA 0x00000001 +#define DDRSS_CTL_342_DATA 0x00010100 +#define DDRSS_CTL_343_DATA 0x03030000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x000556AA +#define DDRSS_CTL_361_DATA 0x000AAAAA +#define DDRSS_CTL_362_DATA 0x000AA955 +#define DDRSS_CTL_363_DATA 0x00055555 +#define DDRSS_CTL_364_DATA 0x000B3133 +#define DDRSS_CTL_365_DATA 0x0004CD33 +#define DDRSS_CTL_366_DATA 0x0004CECC +#define DDRSS_CTL_367_DATA 0x000B32CC +#define DDRSS_CTL_368_DATA 0x00010300 +#define DDRSS_CTL_369_DATA 0x03000100 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x00000000 +#define DDRSS_CTL_372_DATA 0x00000000 +#define DDRSS_CTL_373_DATA 0x00000000 +#define DDRSS_CTL_374_DATA 0x00000000 +#define DDRSS_CTL_375_DATA 0x00000000 +#define DDRSS_CTL_376_DATA 0x00000000 +#define DDRSS_CTL_377_DATA 0x00010000 +#define DDRSS_CTL_378_DATA 0x00000404 +#define DDRSS_CTL_379_DATA 0x00000000 +#define DDRSS_CTL_380_DATA 0x00000000 +#define DDRSS_CTL_381_DATA 0x00000000 +#define DDRSS_CTL_382_DATA 0x00000000 +#define DDRSS_CTL_383_DATA 0x00000000 +#define DDRSS_CTL_384_DATA 0x00000000 +#define DDRSS_CTL_385_DATA 0x00000000 +#define DDRSS_CTL_386_DATA 0x00000000 +#define DDRSS_CTL_387_DATA 0x37371B00 +#define DDRSS_CTL_388_DATA 0x000A0000 +#define DDRSS_CTL_389_DATA 0x00000176 +#define DDRSS_CTL_390_DATA 0x00000200 +#define DDRSS_CTL_391_DATA 0x00000200 +#define DDRSS_CTL_392_DATA 0x00000200 +#define DDRSS_CTL_393_DATA 0x00000200 +#define DDRSS_CTL_394_DATA 0x00000462 +#define DDRSS_CTL_395_DATA 0x00000E9C +#define DDRSS_CTL_396_DATA 0x00000204 +#define DDRSS_CTL_397_DATA 0x000038C8 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00000200 +#define DDRSS_CTL_400_DATA 0x00000200 +#define DDRSS_CTL_401_DATA 0x00000200 +#define DDRSS_CTL_402_DATA 0x0000AA58 +#define DDRSS_CTL_403_DATA 0x000237D0 +#define DDRSS_CTL_404_DATA 0x00000C12 +#define DDRSS_CTL_405_DATA 0x000038C8 +#define DDRSS_CTL_406_DATA 0x00000200 +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00000200 +#define DDRSS_CTL_409_DATA 0x00000200 +#define DDRSS_CTL_410_DATA 0x0000AA58 +#define DDRSS_CTL_411_DATA 0x000237D0 +#define DDRSS_CTL_412_DATA 0x02020C12 +#define DDRSS_CTL_413_DATA 0x03030202 +#define DDRSS_CTL_414_DATA 0x00000022 +#define DDRSS_CTL_415_DATA 0x00000000 +#define DDRSS_CTL_416_DATA 0x00000000 +#define DDRSS_CTL_417_DATA 0x00001403 +#define DDRSS_CTL_418_DATA 0x000007D0 +#define DDRSS_CTL_419_DATA 0x00000000 +#define DDRSS_CTL_420_DATA 0x00000000 +#define DDRSS_CTL_421_DATA 0x00030000 +#define DDRSS_CTL_422_DATA 0x0006001E +#define DDRSS_CTL_423_DATA 0x00190031 +#define DDRSS_CTL_424_DATA 0x00190031 +#define DDRSS_CTL_425_DATA 0x00000000 +#define DDRSS_CTL_426_DATA 0x00000000 +#define DDRSS_CTL_427_DATA 0x02000000 +#define DDRSS_CTL_428_DATA 0x01000404 +#define DDRSS_CTL_429_DATA 0x091A091A +#define DDRSS_CTL_430_DATA 0x00000105 +#define DDRSS_CTL_431_DATA 0x00010101 +#define DDRSS_CTL_432_DATA 0x00010101 +#define DDRSS_CTL_433_DATA 0x00010001 +#define DDRSS_CTL_434_DATA 0x00000101 +#define DDRSS_CTL_435_DATA 0x02000201 +#define DDRSS_CTL_436_DATA 0x02010000 +#define DDRSS_CTL_437_DATA 0x00000200 +#define DDRSS_CTL_438_DATA 0x22060000 +#define DDRSS_CTL_439_DATA 0x00000122 +#define DDRSS_CTL_440_DATA 0xFFFFFFFF +#define DDRSS_CTL_441_DATA 0xFFFFFFFF +#define DDRSS_CTL_442_DATA 0x00000000 +#define DDRSS_CTL_443_DATA 0x00000000 +#define DDRSS_CTL_444_DATA 0x00000000 +#define DDRSS_CTL_445_DATA 0x00000000 +#define DDRSS_CTL_446_DATA 0x00000000 +#define DDRSS_CTL_447_DATA 0x00000000 +#define DDRSS_CTL_448_DATA 0x00000000 +#define DDRSS_CTL_449_DATA 0x00000000 +#define DDRSS_CTL_450_DATA 0x00000000 +#define DDRSS_CTL_451_DATA 0x00000000 +#define DDRSS_CTL_452_DATA 0x00000000 +#define DDRSS_CTL_453_DATA 0x00000000 +#define DDRSS_CTL_454_DATA 0x00000000 +#define DDRSS_CTL_455_DATA 0x00000000 +#define DDRSS_CTL_456_DATA 0x00000000 +#define DDRSS_CTL_457_DATA 0x00000000 +#define DDRSS_CTL_458_DATA 0x00000000 + +#define DDRSS_PI_00_DATA 0x00000B00 +#define DDRSS_PI_01_DATA 0x00000000 +#define DDRSS_PI_02_DATA 0x00000000 +#define DDRSS_PI_03_DATA 0x00000000 +#define DDRSS_PI_04_DATA 0x00000000 +#define DDRSS_PI_05_DATA 0x00000101 +#define DDRSS_PI_06_DATA 0x00640000 +#define DDRSS_PI_07_DATA 0x00000001 +#define DDRSS_PI_08_DATA 0x00000000 +#define DDRSS_PI_09_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000000 +#define DDRSS_PI_12_DATA 0x00000007 +#define DDRSS_PI_13_DATA 0x00010002 +#define DDRSS_PI_14_DATA 0x0800000F +#define DDRSS_PI_15_DATA 0x00000103 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00000000 +#define DDRSS_PI_24_DATA 0x00000000 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x00010100 +#define DDRSS_PI_27_DATA 0x00280A00 +#define DDRSS_PI_28_DATA 0x00000000 +#define DDRSS_PI_29_DATA 0x0F000000 +#define DDRSS_PI_30_DATA 0x00003200 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x01010102 +#define DDRSS_PI_34_DATA 0x00000000 +#define DDRSS_PI_35_DATA 0x000000AA +#define DDRSS_PI_36_DATA 0x00000055 +#define DDRSS_PI_37_DATA 0x000000B5 +#define DDRSS_PI_38_DATA 0x0000004A +#define DDRSS_PI_39_DATA 0x00000056 +#define DDRSS_PI_40_DATA 0x000000A9 +#define DDRSS_PI_41_DATA 0x000000A9 +#define DDRSS_PI_42_DATA 0x000000B5 +#define DDRSS_PI_43_DATA 0x00000000 +#define DDRSS_PI_44_DATA 0x00000000 +#define DDRSS_PI_45_DATA 0x000F0F00 +#define DDRSS_PI_46_DATA 0x00000019 +#define DDRSS_PI_47_DATA 0x000007D0 +#define DDRSS_PI_48_DATA 0x00000300 +#define DDRSS_PI_49_DATA 0x00000000 +#define DDRSS_PI_50_DATA 0x00000000 +#define DDRSS_PI_51_DATA 0x01000000 +#define DDRSS_PI_52_DATA 0x00010101 +#define DDRSS_PI_53_DATA 0x00000000 +#define DDRSS_PI_54_DATA 0x00030000 +#define DDRSS_PI_55_DATA 0x0F000000 +#define DDRSS_PI_56_DATA 0x00000017 +#define DDRSS_PI_57_DATA 0x00000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x00000000 +#define DDRSS_PI_60_DATA 0x0A0A140A +#define DDRSS_PI_61_DATA 0x10020101 +#define DDRSS_PI_62_DATA 0x00020805 +#define DDRSS_PI_63_DATA 0x01000404 +#define DDRSS_PI_64_DATA 0x00000000 +#define DDRSS_PI_65_DATA 0x00000000 +#define DDRSS_PI_66_DATA 0x00000101 +#define DDRSS_PI_67_DATA 0x0001010F +#define DDRSS_PI_68_DATA 0x00340000 +#define DDRSS_PI_69_DATA 0x00000000 +#define DDRSS_PI_70_DATA 0x00000000 +#define DDRSS_PI_71_DATA 0x00000000 +#define DDRSS_PI_72_DATA 0x01000000 +#define DDRSS_PI_73_DATA 0x00080100 +#define DDRSS_PI_74_DATA 0x02000200 +#define DDRSS_PI_75_DATA 0x01000100 +#define DDRSS_PI_76_DATA 0x01000000 +#define DDRSS_PI_77_DATA 0x02000200 +#define DDRSS_PI_78_DATA 0x00000200 +#define DDRSS_PI_79_DATA 0x00000000 +#define DDRSS_PI_80_DATA 0x00000000 +#define DDRSS_PI_81_DATA 0x00000000 +#define DDRSS_PI_82_DATA 0x00000000 +#define DDRSS_PI_83_DATA 0x00000000 +#define DDRSS_PI_84_DATA 0x00000000 +#define DDRSS_PI_85_DATA 0x00000000 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000400 +#define DDRSS_PI_92_DATA 0x02010000 +#define DDRSS_PI_93_DATA 0x00080003 +#define DDRSS_PI_94_DATA 0x00080000 +#define DDRSS_PI_95_DATA 0x00000001 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x0000AA00 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x00000000 +#define DDRSS_PI_100_DATA 0x00010000 +#define DDRSS_PI_101_DATA 0x00000000 +#define DDRSS_PI_102_DATA 0x00000000 +#define DDRSS_PI_103_DATA 0x00000000 +#define DDRSS_PI_104_DATA 0x00000000 +#define DDRSS_PI_105_DATA 0x00000000 +#define DDRSS_PI_106_DATA 0x00000000 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x00000000 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00000000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000000 +#define DDRSS_PI_125_DATA 0x00000008 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00000000 +#define DDRSS_PI_134_DATA 0x00000002 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x00000000 +#define DDRSS_PI_137_DATA 0x0000000A +#define DDRSS_PI_138_DATA 0x00000019 +#define DDRSS_PI_139_DATA 0x00000100 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x01000000 +#define DDRSS_PI_145_DATA 0x00010003 +#define DDRSS_PI_146_DATA 0x02000101 +#define DDRSS_PI_147_DATA 0x01030001 +#define DDRSS_PI_148_DATA 0x00010400 +#define DDRSS_PI_149_DATA 0x06000105 +#define DDRSS_PI_150_DATA 0x01070001 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00010001 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x00000000 +#define DDRSS_PI_157_DATA 0x00000000 +#define DDRSS_PI_158_DATA 0x00000000 +#define DDRSS_PI_159_DATA 0x00000401 +#define DDRSS_PI_160_DATA 0x00000000 +#define DDRSS_PI_161_DATA 0x00010000 +#define DDRSS_PI_162_DATA 0x00000000 +#define DDRSS_PI_163_DATA 0x26260100 +#define DDRSS_PI_164_DATA 0x00000034 +#define DDRSS_PI_165_DATA 0x0000005E +#define DDRSS_PI_166_DATA 0x0002005E +#define DDRSS_PI_167_DATA 0x02000200 +#define DDRSS_PI_168_DATA 0x40100C04 +#define DDRSS_PI_169_DATA 0x000E4010 +#define DDRSS_PI_170_DATA 0x000000BB +#define DDRSS_PI_171_DATA 0x0000020B +#define DDRSS_PI_172_DATA 0x00001C64 +#define DDRSS_PI_173_DATA 0x0000020B +#define DDRSS_PI_174_DATA 0x04001C64 +#define DDRSS_PI_175_DATA 0x01010404 +#define DDRSS_PI_176_DATA 0x00001501 +#define DDRSS_PI_177_DATA 0x00150015 +#define DDRSS_PI_178_DATA 0x01000100 +#define DDRSS_PI_179_DATA 0x00000100 +#define DDRSS_PI_180_DATA 0x00000000 +#define DDRSS_PI_181_DATA 0x01010101 +#define DDRSS_PI_182_DATA 0x00000101 +#define DDRSS_PI_183_DATA 0x00000000 +#define DDRSS_PI_184_DATA 0x00000000 +#define DDRSS_PI_185_DATA 0x12040000 +#define DDRSS_PI_186_DATA 0x0C0C0212 +#define DDRSS_PI_187_DATA 0x00040402 +#define DDRSS_PI_188_DATA 0x000C8034 +#define DDRSS_PI_189_DATA 0x001F0047 +#define DDRSS_PI_190_DATA 0x001F0047 +#define DDRSS_PI_191_DATA 0x01010101 +#define DDRSS_PI_192_DATA 0x0003000D +#define DDRSS_PI_193_DATA 0x000301D3 +#define DDRSS_PI_194_DATA 0x010001D3 +#define DDRSS_PI_195_DATA 0x000E000E +#define DDRSS_PI_196_DATA 0x01D40100 +#define DDRSS_PI_197_DATA 0x010001D4 +#define DDRSS_PI_198_DATA 0x01D401D4 +#define DDRSS_PI_199_DATA 0x32103200 +#define DDRSS_PI_200_DATA 0x01013210 +#define DDRSS_PI_201_DATA 0x0A070601 +#define DDRSS_PI_202_DATA 0x1C11090D +#define DDRSS_PI_203_DATA 0x1C110913 +#define DDRSS_PI_204_DATA 0x0000C013 +#define DDRSS_PI_205_DATA 0x00C01000 +#define DDRSS_PI_206_DATA 0x00C01000 +#define DDRSS_PI_207_DATA 0x00021000 +#define DDRSS_PI_208_DATA 0x0021000D +#define DDRSS_PI_209_DATA 0x002101D3 +#define DDRSS_PI_210_DATA 0x001101D3 +#define DDRSS_PI_211_DATA 0x32000056 +#define DDRSS_PI_212_DATA 0x00000101 +#define DDRSS_PI_213_DATA 0x005A0035 +#define DDRSS_PI_214_DATA 0x01013212 +#define DDRSS_PI_215_DATA 0x00003500 +#define DDRSS_PI_216_DATA 0x3212005A +#define DDRSS_PI_217_DATA 0x09000101 +#define DDRSS_PI_218_DATA 0x04010504 +#define DDRSS_PI_219_DATA 0x0400062B +#define DDRSS_PI_220_DATA 0x0A032001 +#define DDRSS_PI_221_DATA 0x262B0F0A +#define DDRSS_PI_222_DATA 0x00002819 +#define DDRSS_PI_223_DATA 0x5400E638 +#define DDRSS_PI_224_DATA 0x1B1C2007 +#define DDRSS_PI_225_DATA 0x262B0F13 +#define DDRSS_PI_226_DATA 0x00002819 +#define DDRSS_PI_227_DATA 0x5400E638 +#define DDRSS_PI_228_DATA 0x1B1C2007 +#define DDRSS_PI_229_DATA 0x00017613 +#define DDRSS_PI_230_DATA 0x00000E9C +#define DDRSS_PI_231_DATA 0x000038C8 +#define DDRSS_PI_232_DATA 0x000237D0 +#define DDRSS_PI_233_DATA 0x000038C8 +#define DDRSS_PI_234_DATA 0x000237D0 +#define DDRSS_PI_235_DATA 0x0219000F +#define DDRSS_PI_236_DATA 0x03030219 +#define DDRSS_PI_237_DATA 0x00271003 +#define DDRSS_PI_238_DATA 0x000186A0 +#define DDRSS_PI_239_DATA 0x00000005 +#define DDRSS_PI_240_DATA 0x00000064 +#define DDRSS_PI_241_DATA 0x0000000F +#define DDRSS_PI_242_DATA 0x0005B18F +#define DDRSS_PI_243_DATA 0x000186A0 +#define DDRSS_PI_244_DATA 0x00000005 +#define DDRSS_PI_245_DATA 0x00000E94 +#define DDRSS_PI_246_DATA 0x00000219 +#define DDRSS_PI_247_DATA 0x0005B18F +#define DDRSS_PI_248_DATA 0x000186A0 +#define DDRSS_PI_249_DATA 0x00000005 +#define DDRSS_PI_250_DATA 0x00000E94 +#define DDRSS_PI_251_DATA 0x01000219 +#define DDRSS_PI_252_DATA 0x00320040 +#define DDRSS_PI_253_DATA 0x00010008 +#define DDRSS_PI_254_DATA 0x074A0040 +#define DDRSS_PI_255_DATA 0x00010038 +#define DDRSS_PI_256_DATA 0x074A0040 +#define DDRSS_PI_257_DATA 0x00000338 +#define DDRSS_PI_258_DATA 0x005E005E +#define DDRSS_PI_259_DATA 0x00040404 +#define DDRSS_PI_260_DATA 0x00000055 +#define DDRSS_PI_261_DATA 0x55003C5A +#define DDRSS_PI_262_DATA 0x5A000000 +#define DDRSS_PI_263_DATA 0x0055003C +#define DDRSS_PI_264_DATA 0x3C5A0000 +#define DDRSS_PI_265_DATA 0x00005500 +#define DDRSS_PI_266_DATA 0x0C3C5A00 +#define DDRSS_PI_267_DATA 0x080F0E0D +#define DDRSS_PI_268_DATA 0x000B0A09 +#define DDRSS_PI_269_DATA 0x00030201 +#define DDRSS_PI_270_DATA 0x01000000 +#define DDRSS_PI_271_DATA 0x04020201 +#define DDRSS_PI_272_DATA 0x00080804 +#define DDRSS_PI_273_DATA 0x00000000 +#define DDRSS_PI_274_DATA 0x00000000 +#define DDRSS_PI_275_DATA 0x00330084 +#define DDRSS_PI_276_DATA 0x00160000 +#define DDRSS_PI_277_DATA 0x563336E4 +#define DDRSS_PI_278_DATA 0x00160F27 +#define DDRSS_PI_279_DATA 0x563336E4 +#define DDRSS_PI_280_DATA 0x00160F27 +#define DDRSS_PI_281_DATA 0x00330084 +#define DDRSS_PI_282_DATA 0x00160000 +#define DDRSS_PI_283_DATA 0x563336E4 +#define DDRSS_PI_284_DATA 0x00160F27 +#define DDRSS_PI_285_DATA 0x563336E4 +#define DDRSS_PI_286_DATA 0x00160F27 +#define DDRSS_PI_287_DATA 0x00330084 +#define DDRSS_PI_288_DATA 0x00160000 +#define DDRSS_PI_289_DATA 0x563336E4 +#define DDRSS_PI_290_DATA 0x00160F27 +#define DDRSS_PI_291_DATA 0x563336E4 +#define DDRSS_PI_292_DATA 0x00160F27 +#define DDRSS_PI_293_DATA 0x00330084 +#define DDRSS_PI_294_DATA 0x00160000 +#define DDRSS_PI_295_DATA 0x563336E4 +#define DDRSS_PI_296_DATA 0x00160F27 +#define DDRSS_PI_297_DATA 0x563336E4 +#define DDRSS_PI_298_DATA 0x00160F27 +#define DDRSS_PI_299_DATA 0x00000000 + +#define DDRSS_PHY_00_DATA 0x000004F0 +#define DDRSS_PHY_01_DATA 0x00000000 +#define DDRSS_PHY_02_DATA 0x00030200 +#define DDRSS_PHY_03_DATA 0x00000000 +#define DDRSS_PHY_04_DATA 0x00000000 +#define DDRSS_PHY_05_DATA 0x01030000 +#define DDRSS_PHY_06_DATA 0x00010000 +#define DDRSS_PHY_07_DATA 0x01030004 +#define DDRSS_PHY_08_DATA 0x01000000 +#define DDRSS_PHY_09_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x01000001 +#define DDRSS_PHY_12_DATA 0x00000100 +#define DDRSS_PHY_13_DATA 0x000800C0 +#define DDRSS_PHY_14_DATA 0x060100CC +#define DDRSS_PHY_15_DATA 0x00030066 +#define DDRSS_PHY_16_DATA 0x00000000 +#define DDRSS_PHY_17_DATA 0x00000001 +#define DDRSS_PHY_18_DATA 0x0000AAAA +#define DDRSS_PHY_19_DATA 0x00005555 +#define DDRSS_PHY_20_DATA 0x0000B5B5 +#define DDRSS_PHY_21_DATA 0x00004A4A +#define DDRSS_PHY_22_DATA 0x00005656 +#define DDRSS_PHY_23_DATA 0x0000A9A9 +#define DDRSS_PHY_24_DATA 0x0000A9A9 +#define DDRSS_PHY_25_DATA 0x0000B5B5 +#define DDRSS_PHY_26_DATA 0x00000000 +#define DDRSS_PHY_27_DATA 0x00000000 +#define DDRSS_PHY_28_DATA 0x2A000000 +#define DDRSS_PHY_29_DATA 0x00000808 +#define DDRSS_PHY_30_DATA 0x0F000000 +#define DDRSS_PHY_31_DATA 0x00000F0F +#define DDRSS_PHY_32_DATA 0x10200000 +#define DDRSS_PHY_33_DATA 0x0C002004 +#define DDRSS_PHY_34_DATA 0x00000000 +#define DDRSS_PHY_35_DATA 0x00000000 +#define DDRSS_PHY_36_DATA 0x55555555 +#define DDRSS_PHY_37_DATA 0xAAAAAAAA +#define DDRSS_PHY_38_DATA 0x55555555 +#define DDRSS_PHY_39_DATA 0xAAAAAAAA +#define DDRSS_PHY_40_DATA 0x00005555 +#define DDRSS_PHY_41_DATA 0x01000100 +#define DDRSS_PHY_42_DATA 0x00800180 +#define DDRSS_PHY_43_DATA 0x00000001 +#define DDRSS_PHY_44_DATA 0x00000000 +#define DDRSS_PHY_45_DATA 0x00000000 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000000 +#define DDRSS_PHY_66_DATA 0x00000104 +#define DDRSS_PHY_67_DATA 0x00000120 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x00000000 +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x00000000 +#define DDRSS_PHY_75_DATA 0x00000001 +#define DDRSS_PHY_76_DATA 0x07FF0000 +#define DDRSS_PHY_77_DATA 0x0080081F +#define DDRSS_PHY_78_DATA 0x00081020 +#define DDRSS_PHY_79_DATA 0x04010000 +#define DDRSS_PHY_80_DATA 0x00000000 +#define DDRSS_PHY_81_DATA 0x00000000 +#define DDRSS_PHY_82_DATA 0x00000000 +#define DDRSS_PHY_83_DATA 0x00000100 +#define DDRSS_PHY_84_DATA 0x01CC0C01 +#define DDRSS_PHY_85_DATA 0x0003CC0C +#define DDRSS_PHY_86_DATA 0x20000140 +#define DDRSS_PHY_87_DATA 0x07FF0200 +#define DDRSS_PHY_88_DATA 0x0000DD01 +#define DDRSS_PHY_89_DATA 0x10100303 +#define DDRSS_PHY_90_DATA 0x10101010 +#define DDRSS_PHY_91_DATA 0x10101010 +#define DDRSS_PHY_92_DATA 0x00041010 +#define DDRSS_PHY_93_DATA 0x00100010 +#define DDRSS_PHY_94_DATA 0x00100010 +#define DDRSS_PHY_95_DATA 0x00100010 +#define DDRSS_PHY_96_DATA 0x00100010 +#define DDRSS_PHY_97_DATA 0x00050010 +#define DDRSS_PHY_98_DATA 0x51517041 +#define DDRSS_PHY_99_DATA 0x31C06000 +#define DDRSS_PHY_100_DATA 0x07AB0340 +#define DDRSS_PHY_101_DATA 0x00C0C001 +#define DDRSS_PHY_102_DATA 0x0D0C0001 +#define DDRSS_PHY_103_DATA 0x10001000 +#define DDRSS_PHY_104_DATA 0x0C063E42 +#define DDRSS_PHY_105_DATA 0x0F0C3201 +#define DDRSS_PHY_106_DATA 0x01000140 +#define DDRSS_PHY_107_DATA 0x0C000420 +#define DDRSS_PHY_108_DATA 0x000002DD +#define DDRSS_PHY_109_DATA 0x0A0000D0 +#define DDRSS_PHY_110_DATA 0x00030200 +#define DDRSS_PHY_111_DATA 0x02800000 +#define DDRSS_PHY_112_DATA 0x80800000 +#define DDRSS_PHY_113_DATA 0x000D2010 +#define DDRSS_PHY_114_DATA 0x76543210 +#define DDRSS_PHY_115_DATA 0x00000008 +#define DDRSS_PHY_116_DATA 0x02800280 +#define DDRSS_PHY_117_DATA 0x02800280 +#define DDRSS_PHY_118_DATA 0x02800280 +#define DDRSS_PHY_119_DATA 0x02800280 +#define DDRSS_PHY_120_DATA 0x00000280 +#define DDRSS_PHY_121_DATA 0x0000A000 +#define DDRSS_PHY_122_DATA 0x00A000A0 +#define DDRSS_PHY_123_DATA 0x00A000A0 +#define DDRSS_PHY_124_DATA 0x00A000A0 +#define DDRSS_PHY_125_DATA 0x00A000A0 +#define DDRSS_PHY_126_DATA 0x00A000A0 +#define DDRSS_PHY_127_DATA 0x00A000A0 +#define DDRSS_PHY_128_DATA 0x00A000A0 +#define DDRSS_PHY_129_DATA 0x00A000A0 +#define DDRSS_PHY_130_DATA 0x006D00A0 +#define DDRSS_PHY_131_DATA 0x01A00005 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x00000000 +#define DDRSS_PHY_134_DATA 0x00080200 +#define DDRSS_PHY_135_DATA 0x00000000 +#define DDRSS_PHY_136_DATA 0x20202020 +#define DDRSS_PHY_137_DATA 0x20202020 +#define DDRSS_PHY_138_DATA 0xF0F02020 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x000004F0 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01030000 +#define DDRSS_PHY_262_DATA 0x00010000 +#define DDRSS_PHY_263_DATA 0x01030004 +#define DDRSS_PHY_264_DATA 0x01000000 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x01000001 +#define DDRSS_PHY_268_DATA 0x00000100 +#define DDRSS_PHY_269_DATA 0x000800C0 +#define DDRSS_PHY_270_DATA 0x060100CC +#define DDRSS_PHY_271_DATA 0x00030066 +#define DDRSS_PHY_272_DATA 0x00000000 +#define DDRSS_PHY_273_DATA 0x00000001 +#define DDRSS_PHY_274_DATA 0x0000AAAA +#define DDRSS_PHY_275_DATA 0x00005555 +#define DDRSS_PHY_276_DATA 0x0000B5B5 +#define DDRSS_PHY_277_DATA 0x00004A4A +#define DDRSS_PHY_278_DATA 0x00005656 +#define DDRSS_PHY_279_DATA 0x0000A9A9 +#define DDRSS_PHY_280_DATA 0x0000A9A9 +#define DDRSS_PHY_281_DATA 0x0000B5B5 +#define DDRSS_PHY_282_DATA 0x00000000 +#define DDRSS_PHY_283_DATA 0x00000000 +#define DDRSS_PHY_284_DATA 0x2A000000 +#define DDRSS_PHY_285_DATA 0x00000808 +#define DDRSS_PHY_286_DATA 0x0F000000 +#define DDRSS_PHY_287_DATA 0x00000F0F +#define DDRSS_PHY_288_DATA 0x10200000 +#define DDRSS_PHY_289_DATA 0x0C002004 +#define DDRSS_PHY_290_DATA 0x00000000 +#define DDRSS_PHY_291_DATA 0x00000000 +#define DDRSS_PHY_292_DATA 0x55555555 +#define DDRSS_PHY_293_DATA 0xAAAAAAAA +#define DDRSS_PHY_294_DATA 0x55555555 +#define DDRSS_PHY_295_DATA 0xAAAAAAAA +#define DDRSS_PHY_296_DATA 0x00005555 +#define DDRSS_PHY_297_DATA 0x01000100 +#define DDRSS_PHY_298_DATA 0x00800180 +#define DDRSS_PHY_299_DATA 0x00000000 +#define DDRSS_PHY_300_DATA 0x00000000 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000000 +#define DDRSS_PHY_322_DATA 0x00000104 +#define DDRSS_PHY_323_DATA 0x00000120 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x00000000 +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x00000000 +#define DDRSS_PHY_331_DATA 0x00000001 +#define DDRSS_PHY_332_DATA 0x07FF0000 +#define DDRSS_PHY_333_DATA 0x0080081F +#define DDRSS_PHY_334_DATA 0x00081020 +#define DDRSS_PHY_335_DATA 0x04010000 +#define DDRSS_PHY_336_DATA 0x00000000 +#define DDRSS_PHY_337_DATA 0x00000000 +#define DDRSS_PHY_338_DATA 0x00000000 +#define DDRSS_PHY_339_DATA 0x00000100 +#define DDRSS_PHY_340_DATA 0x01CC0C01 +#define DDRSS_PHY_341_DATA 0x0003CC0C +#define DDRSS_PHY_342_DATA 0x20000140 +#define DDRSS_PHY_343_DATA 0x07FF0200 +#define DDRSS_PHY_344_DATA 0x0000DD01 +#define DDRSS_PHY_345_DATA 0x10100303 +#define DDRSS_PHY_346_DATA 0x10101010 +#define DDRSS_PHY_347_DATA 0x10101010 +#define DDRSS_PHY_348_DATA 0x00041010 +#define DDRSS_PHY_349_DATA 0x00100010 +#define DDRSS_PHY_350_DATA 0x00100010 +#define DDRSS_PHY_351_DATA 0x00100010 +#define DDRSS_PHY_352_DATA 0x00100010 +#define DDRSS_PHY_353_DATA 0x00050010 +#define DDRSS_PHY_354_DATA 0x51517041 +#define DDRSS_PHY_355_DATA 0x31C06000 +#define DDRSS_PHY_356_DATA 0x07AB0340 +#define DDRSS_PHY_357_DATA 0x00C0C001 +#define DDRSS_PHY_358_DATA 0x0D0C0001 +#define DDRSS_PHY_359_DATA 0x10001000 +#define DDRSS_PHY_360_DATA 0x0C063E42 +#define DDRSS_PHY_361_DATA 0x0F0C3201 +#define DDRSS_PHY_362_DATA 0x01000140 +#define DDRSS_PHY_363_DATA 0x0C000420 +#define DDRSS_PHY_364_DATA 0x000002DD +#define DDRSS_PHY_365_DATA 0x0A0000D0 +#define DDRSS_PHY_366_DATA 0x00030200 +#define DDRSS_PHY_367_DATA 0x02800000 +#define DDRSS_PHY_368_DATA 0x80800000 +#define DDRSS_PHY_369_DATA 0x000D2010 +#define DDRSS_PHY_370_DATA 0x76543210 +#define DDRSS_PHY_371_DATA 0x00000008 +#define DDRSS_PHY_372_DATA 0x02800280 +#define DDRSS_PHY_373_DATA 0x02800280 +#define DDRSS_PHY_374_DATA 0x02800280 +#define DDRSS_PHY_375_DATA 0x02800280 +#define DDRSS_PHY_376_DATA 0x00000280 +#define DDRSS_PHY_377_DATA 0x0000A000 +#define DDRSS_PHY_378_DATA 0x00A000A0 +#define DDRSS_PHY_379_DATA 0x00A000A0 +#define DDRSS_PHY_380_DATA 0x00A000A0 +#define DDRSS_PHY_381_DATA 0x00A000A0 +#define DDRSS_PHY_382_DATA 0x00A000A0 +#define DDRSS_PHY_383_DATA 0x00A000A0 +#define DDRSS_PHY_384_DATA 0x00A000A0 +#define DDRSS_PHY_385_DATA 0x00A000A0 +#define DDRSS_PHY_386_DATA 0x006D00A0 +#define DDRSS_PHY_387_DATA 0x01A00005 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x00000000 +#define DDRSS_PHY_390_DATA 0x00080200 +#define DDRSS_PHY_391_DATA 0x00000000 +#define DDRSS_PHY_392_DATA 0x20202020 +#define DDRSS_PHY_393_DATA 0x20202020 +#define DDRSS_PHY_394_DATA 0xF0F02020 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x000004F0 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00030200 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x01030000 +#define DDRSS_PHY_518_DATA 0x00010000 +#define DDRSS_PHY_519_DATA 0x01030004 +#define DDRSS_PHY_520_DATA 0x01000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x01000001 +#define DDRSS_PHY_524_DATA 0x00000100 +#define DDRSS_PHY_525_DATA 0x000800C0 +#define DDRSS_PHY_526_DATA 0x060100CC +#define DDRSS_PHY_527_DATA 0x00030066 +#define DDRSS_PHY_528_DATA 0x00000000 +#define DDRSS_PHY_529_DATA 0x00000001 +#define DDRSS_PHY_530_DATA 0x0000AAAA +#define DDRSS_PHY_531_DATA 0x00005555 +#define DDRSS_PHY_532_DATA 0x0000B5B5 +#define DDRSS_PHY_533_DATA 0x00004A4A +#define DDRSS_PHY_534_DATA 0x00005656 +#define DDRSS_PHY_535_DATA 0x0000A9A9 +#define DDRSS_PHY_536_DATA 0x0000A9A9 +#define DDRSS_PHY_537_DATA 0x0000B5B5 +#define DDRSS_PHY_538_DATA 0x00000000 +#define DDRSS_PHY_539_DATA 0x00000000 +#define DDRSS_PHY_540_DATA 0x2A000000 +#define DDRSS_PHY_541_DATA 0x00000808 +#define DDRSS_PHY_542_DATA 0x0F000000 +#define DDRSS_PHY_543_DATA 0x00000F0F +#define DDRSS_PHY_544_DATA 0x10200000 +#define DDRSS_PHY_545_DATA 0x0C002004 +#define DDRSS_PHY_546_DATA 0x00000000 +#define DDRSS_PHY_547_DATA 0x00000000 +#define DDRSS_PHY_548_DATA 0x55555555 +#define DDRSS_PHY_549_DATA 0xAAAAAAAA +#define DDRSS_PHY_550_DATA 0x55555555 +#define DDRSS_PHY_551_DATA 0xAAAAAAAA +#define DDRSS_PHY_552_DATA 0x00005555 +#define DDRSS_PHY_553_DATA 0x01000100 +#define DDRSS_PHY_554_DATA 0x00800180 +#define DDRSS_PHY_555_DATA 0x00000001 +#define DDRSS_PHY_556_DATA 0x00000000 +#define DDRSS_PHY_557_DATA 0x00000000 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000104 +#define DDRSS_PHY_579_DATA 0x00000120 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x00000000 +#define DDRSS_PHY_587_DATA 0x00000001 +#define DDRSS_PHY_588_DATA 0x07FF0000 +#define DDRSS_PHY_589_DATA 0x0080081F +#define DDRSS_PHY_590_DATA 0x00081020 +#define DDRSS_PHY_591_DATA 0x04010000 +#define DDRSS_PHY_592_DATA 0x00000000 +#define DDRSS_PHY_593_DATA 0x00000000 +#define DDRSS_PHY_594_DATA 0x00000000 +#define DDRSS_PHY_595_DATA 0x00000100 +#define DDRSS_PHY_596_DATA 0x01CC0C01 +#define DDRSS_PHY_597_DATA 0x0003CC0C +#define DDRSS_PHY_598_DATA 0x20000140 +#define DDRSS_PHY_599_DATA 0x07FF0200 +#define DDRSS_PHY_600_DATA 0x0000DD01 +#define DDRSS_PHY_601_DATA 0x10100303 +#define DDRSS_PHY_602_DATA 0x10101010 +#define DDRSS_PHY_603_DATA 0x10101010 +#define DDRSS_PHY_604_DATA 0x00041010 +#define DDRSS_PHY_605_DATA 0x00100010 +#define DDRSS_PHY_606_DATA 0x00100010 +#define DDRSS_PHY_607_DATA 0x00100010 +#define DDRSS_PHY_608_DATA 0x00100010 +#define DDRSS_PHY_609_DATA 0x00050010 +#define DDRSS_PHY_610_DATA 0x51517041 +#define DDRSS_PHY_611_DATA 0x31C06000 +#define DDRSS_PHY_612_DATA 0x07AB0340 +#define DDRSS_PHY_613_DATA 0x00C0C001 +#define DDRSS_PHY_614_DATA 0x0D0C0001 +#define DDRSS_PHY_615_DATA 0x10001000 +#define DDRSS_PHY_616_DATA 0x0C063E42 +#define DDRSS_PHY_617_DATA 0x0F0C3201 +#define DDRSS_PHY_618_DATA 0x01000140 +#define DDRSS_PHY_619_DATA 0x0C000420 +#define DDRSS_PHY_620_DATA 0x000002DD +#define DDRSS_PHY_621_DATA 0x0A0000D0 +#define DDRSS_PHY_622_DATA 0x00030200 +#define DDRSS_PHY_623_DATA 0x02800000 +#define DDRSS_PHY_624_DATA 0x80800000 +#define DDRSS_PHY_625_DATA 0x000D2010 +#define DDRSS_PHY_626_DATA 0x76543210 +#define DDRSS_PHY_627_DATA 0x00000008 +#define DDRSS_PHY_628_DATA 0x02800280 +#define DDRSS_PHY_629_DATA 0x02800280 +#define DDRSS_PHY_630_DATA 0x02800280 +#define DDRSS_PHY_631_DATA 0x02800280 +#define DDRSS_PHY_632_DATA 0x00000280 +#define DDRSS_PHY_633_DATA 0x0000A000 +#define DDRSS_PHY_634_DATA 0x00A000A0 +#define DDRSS_PHY_635_DATA 0x00A000A0 +#define DDRSS_PHY_636_DATA 0x00A000A0 +#define DDRSS_PHY_637_DATA 0x00A000A0 +#define DDRSS_PHY_638_DATA 0x00A000A0 +#define DDRSS_PHY_639_DATA 0x00A000A0 +#define DDRSS_PHY_640_DATA 0x00A000A0 +#define DDRSS_PHY_641_DATA 0x00A000A0 +#define DDRSS_PHY_642_DATA 0x006D00A0 +#define DDRSS_PHY_643_DATA 0x01A00005 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x00000000 +#define DDRSS_PHY_646_DATA 0x00080200 +#define DDRSS_PHY_647_DATA 0x00000000 +#define DDRSS_PHY_648_DATA 0x20202020 +#define DDRSS_PHY_649_DATA 0x20202020 +#define DDRSS_PHY_650_DATA 0xF0F02020 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x000004F0 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00030200 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x01030000 +#define DDRSS_PHY_774_DATA 0x00010000 +#define DDRSS_PHY_775_DATA 0x01030004 +#define DDRSS_PHY_776_DATA 0x01000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x01000001 +#define DDRSS_PHY_780_DATA 0x00000100 +#define DDRSS_PHY_781_DATA 0x000800C0 +#define DDRSS_PHY_782_DATA 0x060100CC +#define DDRSS_PHY_783_DATA 0x00030066 +#define DDRSS_PHY_784_DATA 0x00000000 +#define DDRSS_PHY_785_DATA 0x00000001 +#define DDRSS_PHY_786_DATA 0x0000AAAA +#define DDRSS_PHY_787_DATA 0x00005555 +#define DDRSS_PHY_788_DATA 0x0000B5B5 +#define DDRSS_PHY_789_DATA 0x00004A4A +#define DDRSS_PHY_790_DATA 0x00005656 +#define DDRSS_PHY_791_DATA 0x0000A9A9 +#define DDRSS_PHY_792_DATA 0x0000A9A9 +#define DDRSS_PHY_793_DATA 0x0000B5B5 +#define DDRSS_PHY_794_DATA 0x00000000 +#define DDRSS_PHY_795_DATA 0x00000000 +#define DDRSS_PHY_796_DATA 0x2A000000 +#define DDRSS_PHY_797_DATA 0x00000808 +#define DDRSS_PHY_798_DATA 0x0F000000 +#define DDRSS_PHY_799_DATA 0x00000F0F +#define DDRSS_PHY_800_DATA 0x10200000 +#define DDRSS_PHY_801_DATA 0x0C002004 +#define DDRSS_PHY_802_DATA 0x00000000 +#define DDRSS_PHY_803_DATA 0x00000000 +#define DDRSS_PHY_804_DATA 0x55555555 +#define DDRSS_PHY_805_DATA 0xAAAAAAAA +#define DDRSS_PHY_806_DATA 0x55555555 +#define DDRSS_PHY_807_DATA 0xAAAAAAAA +#define DDRSS_PHY_808_DATA 0x00005555 +#define DDRSS_PHY_809_DATA 0x01000100 +#define DDRSS_PHY_810_DATA 0x00800180 +#define DDRSS_PHY_811_DATA 0x00000000 +#define DDRSS_PHY_812_DATA 0x00000000 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000104 +#define DDRSS_PHY_835_DATA 0x00000120 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x00000000 +#define DDRSS_PHY_843_DATA 0x00000001 +#define DDRSS_PHY_844_DATA 0x07FF0000 +#define DDRSS_PHY_845_DATA 0x0080081F +#define DDRSS_PHY_846_DATA 0x00081020 +#define DDRSS_PHY_847_DATA 0x04010000 +#define DDRSS_PHY_848_DATA 0x00000000 +#define DDRSS_PHY_849_DATA 0x00000000 +#define DDRSS_PHY_850_DATA 0x00000000 +#define DDRSS_PHY_851_DATA 0x00000100 +#define DDRSS_PHY_852_DATA 0x01CC0C01 +#define DDRSS_PHY_853_DATA 0x0003CC0C +#define DDRSS_PHY_854_DATA 0x20000140 +#define DDRSS_PHY_855_DATA 0x07FF0200 +#define DDRSS_PHY_856_DATA 0x0000DD01 +#define DDRSS_PHY_857_DATA 0x10100303 +#define DDRSS_PHY_858_DATA 0x10101010 +#define DDRSS_PHY_859_DATA 0x10101010 +#define DDRSS_PHY_860_DATA 0x00041010 +#define DDRSS_PHY_861_DATA 0x00100010 +#define DDRSS_PHY_862_DATA 0x00100010 +#define DDRSS_PHY_863_DATA 0x00100010 +#define DDRSS_PHY_864_DATA 0x00100010 +#define DDRSS_PHY_865_DATA 0x00050010 +#define DDRSS_PHY_866_DATA 0x51517041 +#define DDRSS_PHY_867_DATA 0x31C06000 +#define DDRSS_PHY_868_DATA 0x07AB0340 +#define DDRSS_PHY_869_DATA 0x00C0C001 +#define DDRSS_PHY_870_DATA 0x0D0C0001 +#define DDRSS_PHY_871_DATA 0x10001000 +#define DDRSS_PHY_872_DATA 0x0C063E42 +#define DDRSS_PHY_873_DATA 0x0F0C3201 +#define DDRSS_PHY_874_DATA 0x01000140 +#define DDRSS_PHY_875_DATA 0x0C000420 +#define DDRSS_PHY_876_DATA 0x000002DD +#define DDRSS_PHY_877_DATA 0x0A0000D0 +#define DDRSS_PHY_878_DATA 0x00030200 +#define DDRSS_PHY_879_DATA 0x02800000 +#define DDRSS_PHY_880_DATA 0x80800000 +#define DDRSS_PHY_881_DATA 0x000D2010 +#define DDRSS_PHY_882_DATA 0x76543210 +#define DDRSS_PHY_883_DATA 0x00000008 +#define DDRSS_PHY_884_DATA 0x02800280 +#define DDRSS_PHY_885_DATA 0x02800280 +#define DDRSS_PHY_886_DATA 0x02800280 +#define DDRSS_PHY_887_DATA 0x02800280 +#define DDRSS_PHY_888_DATA 0x00000280 +#define DDRSS_PHY_889_DATA 0x0000A000 +#define DDRSS_PHY_890_DATA 0x00A000A0 +#define DDRSS_PHY_891_DATA 0x00A000A0 +#define DDRSS_PHY_892_DATA 0x00A000A0 +#define DDRSS_PHY_893_DATA 0x00A000A0 +#define DDRSS_PHY_894_DATA 0x00A000A0 +#define DDRSS_PHY_895_DATA 0x00A000A0 +#define DDRSS_PHY_896_DATA 0x00A000A0 +#define DDRSS_PHY_897_DATA 0x00A000A0 +#define DDRSS_PHY_898_DATA 0x006D00A0 +#define DDRSS_PHY_899_DATA 0x01A00005 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x00000000 +#define DDRSS_PHY_902_DATA 0x00080200 +#define DDRSS_PHY_903_DATA 0x00000000 +#define DDRSS_PHY_904_DATA 0x20202020 +#define DDRSS_PHY_905_DATA 0x20202020 +#define DDRSS_PHY_906_DATA 0xF0F02020 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x00000000 +#define DDRSS_PHY_1045_DATA 0x0000002A +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x00000015 +#define DDRSS_PHY_1048_DATA 0x0000002A +#define DDRSS_PHY_1049_DATA 0x00000033 +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x0000000C +#define DDRSS_PHY_1052_DATA 0x00000033 +#define DDRSS_PHY_1053_DATA 0x00543210 +#define DDRSS_PHY_1054_DATA 0x003F0000 +#define DDRSS_PHY_1055_DATA 0x000F013F +#define DDRSS_PHY_1056_DATA 0x20202003 +#define DDRSS_PHY_1057_DATA 0x00202020 +#define DDRSS_PHY_1058_DATA 0x20008008 +#define DDRSS_PHY_1059_DATA 0x00000810 +#define DDRSS_PHY_1060_DATA 0x00000F00 +#define DDRSS_PHY_1061_DATA 0x00000000 +#define DDRSS_PHY_1062_DATA 0x00000000 +#define DDRSS_PHY_1063_DATA 0x00000000 +#define DDRSS_PHY_1064_DATA 0x000505FF +#define DDRSS_PHY_1065_DATA 0x00030000 +#define DDRSS_PHY_1066_DATA 0x00000300 +#define DDRSS_PHY_1067_DATA 0x00000300 +#define DDRSS_PHY_1068_DATA 0x00000300 +#define DDRSS_PHY_1069_DATA 0x00000300 +#define DDRSS_PHY_1070_DATA 0x00000300 +#define DDRSS_PHY_1071_DATA 0x42080010 +#define DDRSS_PHY_1072_DATA 0x0000803E +#define DDRSS_PHY_1073_DATA 0x00000001 +#define DDRSS_PHY_1074_DATA 0x01000102 +#define DDRSS_PHY_1075_DATA 0x00008000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00010100 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00050000 +#define DDRSS_PHY_1285_DATA 0x04000000 +#define DDRSS_PHY_1286_DATA 0x00000055 +#define DDRSS_PHY_1287_DATA 0x00000000 +#define DDRSS_PHY_1288_DATA 0x00000000 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00002001 +#define DDRSS_PHY_1292_DATA 0x0000400F +#define DDRSS_PHY_1293_DATA 0x50020028 +#define DDRSS_PHY_1294_DATA 0x01010000 +#define DDRSS_PHY_1295_DATA 0x80080001 +#define DDRSS_PHY_1296_DATA 0x10200000 +#define DDRSS_PHY_1297_DATA 0x00000008 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x01090E00 +#define DDRSS_PHY_1300_DATA 0x00040101 +#define DDRSS_PHY_1301_DATA 0x0000010F +#define DDRSS_PHY_1302_DATA 0x00000000 +#define DDRSS_PHY_1303_DATA 0x0000FFFF +#define DDRSS_PHY_1304_DATA 0x00000000 +#define DDRSS_PHY_1305_DATA 0x01010000 +#define DDRSS_PHY_1306_DATA 0x01080402 +#define DDRSS_PHY_1307_DATA 0x01200F02 +#define DDRSS_PHY_1308_DATA 0x00194280 +#define DDRSS_PHY_1309_DATA 0x00000004 +#define DDRSS_PHY_1310_DATA 0x00050000 +#define DDRSS_PHY_1311_DATA 0x00000000 +#define DDRSS_PHY_1312_DATA 0x00000000 +#define DDRSS_PHY_1313_DATA 0x00000000 +#define DDRSS_PHY_1314_DATA 0x00000000 +#define DDRSS_PHY_1315_DATA 0x00000000 +#define DDRSS_PHY_1316_DATA 0x00000000 +#define DDRSS_PHY_1317_DATA 0x01000000 +#define DDRSS_PHY_1318_DATA 0x00000705 +#define DDRSS_PHY_1319_DATA 0x00000054 +#define DDRSS_PHY_1320_DATA 0x00030820 +#define DDRSS_PHY_1321_DATA 0x00010820 +#define DDRSS_PHY_1322_DATA 0x00010820 +#define DDRSS_PHY_1323_DATA 0x00010820 +#define DDRSS_PHY_1324_DATA 0x00010820 +#define DDRSS_PHY_1325_DATA 0x00010820 +#define DDRSS_PHY_1326_DATA 0x00010820 +#define DDRSS_PHY_1327_DATA 0x00010820 +#define DDRSS_PHY_1328_DATA 0x00010820 +#define DDRSS_PHY_1329_DATA 0x00000000 +#define DDRSS_PHY_1330_DATA 0x00000074 +#define DDRSS_PHY_1331_DATA 0x00000400 +#define DDRSS_PHY_1332_DATA 0x00000108 +#define DDRSS_PHY_1333_DATA 0x00000000 +#define DDRSS_PHY_1334_DATA 0x00000000 +#define DDRSS_PHY_1335_DATA 0x00000000 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x03000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x00000000 +#define DDRSS_PHY_1342_DATA 0x04102006 +#define DDRSS_PHY_1343_DATA 0x00041020 +#define DDRSS_PHY_1344_DATA 0x01C98C98 +#define DDRSS_PHY_1345_DATA 0x3F400000 +#define DDRSS_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS_PHY_1347_DATA 0x0000001F +#define DDRSS_PHY_1348_DATA 0x00000000 +#define DDRSS_PHY_1349_DATA 0x00000000 +#define DDRSS_PHY_1350_DATA 0x00000000 +#define DDRSS_PHY_1351_DATA 0x00010000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000000 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x76543210 +#define DDRSS_PHY_1357_DATA 0x00010198 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x00000000 +#define DDRSS_PHY_1360_DATA 0x00000000 +#define DDRSS_PHY_1361_DATA 0x00040700 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00000000 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000002 +#define DDRSS_PHY_1368_DATA 0x00000000 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x00000000 +#define DDRSS_PHY_1372_DATA 0x00000000 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00080000 +#define DDRSS_PHY_1375_DATA 0x000007FF +#define DDRSS_PHY_1376_DATA 0x00000000 +#define DDRSS_PHY_1377_DATA 0x00000000 +#define DDRSS_PHY_1378_DATA 0x00000000 +#define DDRSS_PHY_1379_DATA 0x00000000 +#define DDRSS_PHY_1380_DATA 0x00000000 +#define DDRSS_PHY_1381_DATA 0x00000000 +#define DDRSS_PHY_1382_DATA 0x000FFFFF +#define DDRSS_PHY_1383_DATA 0x000FFFFF +#define DDRSS_PHY_1384_DATA 0x0000FFFF +#define DDRSS_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS_PHY_1386_DATA 0x030FFFFF +#define DDRSS_PHY_1387_DATA 0x01FFFFFF +#define DDRSS_PHY_1388_DATA 0x0000FFFF +#define DDRSS_PHY_1389_DATA 0x00000000 +#define DDRSS_PHY_1390_DATA 0x00000000 +#define DDRSS_PHY_1391_DATA 0x00000000 +#define DDRSS_PHY_1392_DATA 0x00000000 +#define DDRSS_PHY_1393_DATA 0x0001F7C5 +#define DDRSS_PHY_1394_DATA 0x00000005 +#define DDRSS_PHY_1395_DATA 0x00000000 +#define DDRSS_PHY_1396_DATA 0x00001142 +#define DDRSS_PHY_1397_DATA 0x010207AB +#define DDRSS_PHY_1398_DATA 0x01000080 +#define DDRSS_PHY_1399_DATA 0x03900390 +#define DDRSS_PHY_1400_DATA 0x03900390 +#define DDRSS_PHY_1401_DATA 0x00000390 +#define DDRSS_PHY_1402_DATA 0x00000390 +#define DDRSS_PHY_1403_DATA 0x00000390 +#define DDRSS_PHY_1404_DATA 0x00000390 +#define DDRSS_PHY_1405_DATA 0x00000005 +#define DDRSS_PHY_1406_DATA 0x01813FFF +#define DDRSS_PHY_1407_DATA 0x000000FF +#define DDRSS_PHY_1408_DATA 0x0C000DFF +#define DDRSS_PHY_1409_DATA 0x30000DFF +#define DDRSS_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS_PHY_1411_DATA 0x000100F0 +#define DDRSS_PHY_1412_DATA 0x780DFFFF +#define DDRSS_PHY_1413_DATA 0x00007E31 +#define DDRSS_PHY_1414_DATA 0x000CBF11 +#define DDRSS_PHY_1415_DATA 0x01FF0010 +#define DDRSS_PHY_1416_DATA 0x000CBF11 +#define DDRSS_PHY_1417_DATA 0x01FF0010 +#define DDRSS_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS_PHY_1419_DATA 0x01FF00F0 +#define DDRSS_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS_PHY_1421_DATA 0x01FF00F0 +#define DDRSS_PHY_1422_DATA 0x20040006 diff --git a/arch/arm/dts/k3-j721e-ddr.dtsi b/arch/arm/dts/k3-j721e-ddr.dtsi new file mode 100644 index 0000000000..21d63802a5 --- /dev/null +++ b/arch/arm/dts/k3-j721e-ddr.dtsi @@ -0,0 +1,2212 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ +*/ + +/ { + memorycontroller: memorycontroller@0298e000 { + compatible = "ti,j721e-ddrss"; + reg = <0x0 0x02990000 0x0 0x4000>, + <0x0 0x0114000 0x0 0x100>; + reg-names = "cfg", "ctrl_mmr_lp4"; + power-domains = <&k3_pds 47 TI_SCI_PD_SHARED>, + <&k3_pds 90 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 47 2>, <&k3_clks 30 9>; + ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>; + ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>; + ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>; + + u-boot,dm-spl; + + ti,ctl-data = < + DDRSS_CTL_00_DATA + DDRSS_CTL_01_DATA + DDRSS_CTL_02_DATA + DDRSS_CTL_03_DATA + DDRSS_CTL_04_DATA + DDRSS_CTL_05_DATA + DDRSS_CTL_06_DATA + DDRSS_CTL_07_DATA + DDRSS_CTL_08_DATA + DDRSS_CTL_09_DATA + DDRSS_CTL_10_DATA + DDRSS_CTL_11_DATA + DDRSS_CTL_12_DATA + DDRSS_CTL_13_DATA + DDRSS_CTL_14_DATA + DDRSS_CTL_15_DATA + DDRSS_CTL_16_DATA + DDRSS_CTL_17_DATA + DDRSS_CTL_18_DATA + DDRSS_CTL_19_DATA + DDRSS_CTL_20_DATA + DDRSS_CTL_21_DATA + DDRSS_CTL_22_DATA + DDRSS_CTL_23_DATA + DDRSS_CTL_24_DATA + DDRSS_CTL_25_DATA + DDRSS_CTL_26_DATA + DDRSS_CTL_27_DATA + DDRSS_CTL_28_DATA + DDRSS_CTL_29_DATA + DDRSS_CTL_30_DATA + DDRSS_CTL_31_DATA + DDRSS_CTL_32_DATA + DDRSS_CTL_33_DATA + DDRSS_CTL_34_DATA + DDRSS_CTL_35_DATA + DDRSS_CTL_36_DATA + DDRSS_CTL_37_DATA + DDRSS_CTL_38_DATA + DDRSS_CTL_39_DATA + DDRSS_CTL_40_DATA + DDRSS_CTL_41_DATA + DDRSS_CTL_42_DATA + DDRSS_CTL_43_DATA + DDRSS_CTL_44_DATA + DDRSS_CTL_45_DATA + DDRSS_CTL_46_DATA + DDRSS_CTL_47_DATA + DDRSS_CTL_48_DATA + DDRSS_CTL_49_DATA + DDRSS_CTL_50_DATA + DDRSS_CTL_51_DATA + DDRSS_CTL_52_DATA + DDRSS_CTL_53_DATA + DDRSS_CTL_54_DATA + DDRSS_CTL_55_DATA + DDRSS_CTL_56_DATA + DDRSS_CTL_57_DATA + DDRSS_CTL_58_DATA + DDRSS_CTL_59_DATA + DDRSS_CTL_60_DATA + DDRSS_CTL_61_DATA + DDRSS_CTL_62_DATA + DDRSS_CTL_63_DATA + DDRSS_CTL_64_DATA + DDRSS_CTL_65_DATA + DDRSS_CTL_66_DATA + DDRSS_CTL_67_DATA + DDRSS_CTL_68_DATA + DDRSS_CTL_69_DATA + DDRSS_CTL_70_DATA + DDRSS_CTL_71_DATA + DDRSS_CTL_72_DATA + DDRSS_CTL_73_DATA + DDRSS_CTL_74_DATA + DDRSS_CTL_75_DATA + DDRSS_CTL_76_DATA + DDRSS_CTL_77_DATA + DDRSS_CTL_78_DATA + DDRSS_CTL_79_DATA + DDRSS_CTL_80_DATA + DDRSS_CTL_81_DATA + DDRSS_CTL_82_DATA + DDRSS_CTL_83_DATA + DDRSS_CTL_84_DATA + DDRSS_CTL_85_DATA + DDRSS_CTL_86_DATA + DDRSS_CTL_87_DATA + DDRSS_CTL_88_DATA + DDRSS_CTL_89_DATA + DDRSS_CTL_90_DATA + DDRSS_CTL_91_DATA + DDRSS_CTL_92_DATA + DDRSS_CTL_93_DATA + DDRSS_CTL_94_DATA + DDRSS_CTL_95_DATA + DDRSS_CTL_96_DATA + DDRSS_CTL_97_DATA + DDRSS_CTL_98_DATA + DDRSS_CTL_99_DATA + DDRSS_CTL_100_DATA + DDRSS_CTL_101_DATA + DDRSS_CTL_102_DATA + DDRSS_CTL_103_DATA + DDRSS_CTL_104_DATA + DDRSS_CTL_105_DATA + DDRSS_CTL_106_DATA + DDRSS_CTL_107_DATA + DDRSS_CTL_108_DATA + DDRSS_CTL_109_DATA + DDRSS_CTL_110_DATA + DDRSS_CTL_111_DATA + DDRSS_CTL_112_DATA + DDRSS_CTL_113_DATA + DDRSS_CTL_114_DATA + DDRSS_CTL_115_DATA + DDRSS_CTL_116_DATA + DDRSS_CTL_117_DATA + DDRSS_CTL_118_DATA + DDRSS_CTL_119_DATA + DDRSS_CTL_120_DATA + DDRSS_CTL_121_DATA + DDRSS_CTL_122_DATA + DDRSS_CTL_123_DATA + DDRSS_CTL_124_DATA + DDRSS_CTL_125_DATA + DDRSS_CTL_126_DATA + DDRSS_CTL_127_DATA + DDRSS_CTL_128_DATA + DDRSS_CTL_129_DATA + DDRSS_CTL_130_DATA + DDRSS_CTL_131_DATA + DDRSS_CTL_132_DATA + DDRSS_CTL_133_DATA + DDRSS_CTL_134_DATA + DDRSS_CTL_135_DATA + DDRSS_CTL_136_DATA + DDRSS_CTL_137_DATA + DDRSS_CTL_138_DATA + DDRSS_CTL_139_DATA + DDRSS_CTL_140_DATA + DDRSS_CTL_141_DATA + DDRSS_CTL_142_DATA + DDRSS_CTL_143_DATA + DDRSS_CTL_144_DATA + DDRSS_CTL_145_DATA + DDRSS_CTL_146_DATA + DDRSS_CTL_147_DATA + DDRSS_CTL_148_DATA + DDRSS_CTL_149_DATA + DDRSS_CTL_150_DATA + DDRSS_CTL_151_DATA + DDRSS_CTL_152_DATA + DDRSS_CTL_153_DATA + DDRSS_CTL_154_DATA + DDRSS_CTL_155_DATA + DDRSS_CTL_156_DATA + DDRSS_CTL_157_DATA + DDRSS_CTL_158_DATA + DDRSS_CTL_159_DATA + DDRSS_CTL_160_DATA + DDRSS_CTL_161_DATA + DDRSS_CTL_162_DATA + DDRSS_CTL_163_DATA + DDRSS_CTL_164_DATA + DDRSS_CTL_165_DATA + DDRSS_CTL_166_DATA + DDRSS_CTL_167_DATA + DDRSS_CTL_168_DATA + DDRSS_CTL_169_DATA + DDRSS_CTL_170_DATA + DDRSS_CTL_171_DATA + DDRSS_CTL_172_DATA + DDRSS_CTL_173_DATA + DDRSS_CTL_174_DATA + DDRSS_CTL_175_DATA + DDRSS_CTL_176_DATA + DDRSS_CTL_177_DATA + DDRSS_CTL_178_DATA + DDRSS_CTL_179_DATA + DDRSS_CTL_180_DATA + DDRSS_CTL_181_DATA + DDRSS_CTL_182_DATA + DDRSS_CTL_183_DATA + DDRSS_CTL_184_DATA + DDRSS_CTL_185_DATA + DDRSS_CTL_186_DATA + DDRSS_CTL_187_DATA + DDRSS_CTL_188_DATA + DDRSS_CTL_189_DATA + DDRSS_CTL_190_DATA + DDRSS_CTL_191_DATA + DDRSS_CTL_192_DATA + DDRSS_CTL_193_DATA + DDRSS_CTL_194_DATA + DDRSS_CTL_195_DATA + DDRSS_CTL_196_DATA + DDRSS_CTL_197_DATA + DDRSS_CTL_198_DATA + DDRSS_CTL_199_DATA + DDRSS_CTL_200_DATA + DDRSS_CTL_201_DATA + DDRSS_CTL_202_DATA + DDRSS_CTL_203_DATA + DDRSS_CTL_204_DATA + DDRSS_CTL_205_DATA + DDRSS_CTL_206_DATA + DDRSS_CTL_207_DATA + DDRSS_CTL_208_DATA + DDRSS_CTL_209_DATA + DDRSS_CTL_210_DATA + DDRSS_CTL_211_DATA + DDRSS_CTL_212_DATA + DDRSS_CTL_213_DATA + DDRSS_CTL_214_DATA + DDRSS_CTL_215_DATA + DDRSS_CTL_216_DATA + DDRSS_CTL_217_DATA + DDRSS_CTL_218_DATA + DDRSS_CTL_219_DATA + DDRSS_CTL_220_DATA + DDRSS_CTL_221_DATA + DDRSS_CTL_222_DATA + DDRSS_CTL_223_DATA + DDRSS_CTL_224_DATA + DDRSS_CTL_225_DATA + DDRSS_CTL_226_DATA + DDRSS_CTL_227_DATA + DDRSS_CTL_228_DATA + DDRSS_CTL_229_DATA + DDRSS_CTL_230_DATA + DDRSS_CTL_231_DATA + DDRSS_CTL_232_DATA + DDRSS_CTL_233_DATA + DDRSS_CTL_234_DATA + DDRSS_CTL_235_DATA + DDRSS_CTL_236_DATA + DDRSS_CTL_237_DATA + DDRSS_CTL_238_DATA + DDRSS_CTL_239_DATA + DDRSS_CTL_240_DATA + DDRSS_CTL_241_DATA + DDRSS_CTL_242_DATA + DDRSS_CTL_243_DATA + DDRSS_CTL_244_DATA + DDRSS_CTL_245_DATA + DDRSS_CTL_246_DATA + DDRSS_CTL_247_DATA + DDRSS_CTL_248_DATA + DDRSS_CTL_249_DATA + DDRSS_CTL_250_DATA + DDRSS_CTL_251_DATA + DDRSS_CTL_252_DATA + DDRSS_CTL_253_DATA + DDRSS_CTL_254_DATA + DDRSS_CTL_255_DATA + DDRSS_CTL_256_DATA + DDRSS_CTL_257_DATA + DDRSS_CTL_258_DATA + DDRSS_CTL_259_DATA + DDRSS_CTL_260_DATA + DDRSS_CTL_261_DATA + DDRSS_CTL_262_DATA + DDRSS_CTL_263_DATA + DDRSS_CTL_264_DATA + DDRSS_CTL_265_DATA + DDRSS_CTL_266_DATA + DDRSS_CTL_267_DATA + DDRSS_CTL_268_DATA + DDRSS_CTL_269_DATA + DDRSS_CTL_270_DATA + DDRSS_CTL_271_DATA + DDRSS_CTL_272_DATA + DDRSS_CTL_273_DATA + DDRSS_CTL_274_DATA + DDRSS_CTL_275_DATA + DDRSS_CTL_276_DATA + DDRSS_CTL_277_DATA + DDRSS_CTL_278_DATA + DDRSS_CTL_279_DATA + DDRSS_CTL_280_DATA + DDRSS_CTL_281_DATA + DDRSS_CTL_282_DATA + DDRSS_CTL_283_DATA + DDRSS_CTL_284_DATA + DDRSS_CTL_285_DATA + DDRSS_CTL_286_DATA + DDRSS_CTL_287_DATA + DDRSS_CTL_288_DATA + DDRSS_CTL_289_DATA + DDRSS_CTL_290_DATA + DDRSS_CTL_291_DATA + DDRSS_CTL_292_DATA + DDRSS_CTL_293_DATA + DDRSS_CTL_294_DATA + DDRSS_CTL_295_DATA + DDRSS_CTL_296_DATA + DDRSS_CTL_297_DATA + DDRSS_CTL_298_DATA + DDRSS_CTL_299_DATA + DDRSS_CTL_300_DATA + DDRSS_CTL_301_DATA + DDRSS_CTL_302_DATA + DDRSS_CTL_303_DATA + DDRSS_CTL_304_DATA + DDRSS_CTL_305_DATA + DDRSS_CTL_306_DATA + DDRSS_CTL_307_DATA + DDRSS_CTL_308_DATA + DDRSS_CTL_309_DATA + DDRSS_CTL_310_DATA + DDRSS_CTL_311_DATA + DDRSS_CTL_312_DATA + DDRSS_CTL_313_DATA + DDRSS_CTL_314_DATA + DDRSS_CTL_315_DATA + DDRSS_CTL_316_DATA + DDRSS_CTL_317_DATA + DDRSS_CTL_318_DATA + DDRSS_CTL_319_DATA + DDRSS_CTL_320_DATA + DDRSS_CTL_321_DATA + DDRSS_CTL_322_DATA + DDRSS_CTL_323_DATA + DDRSS_CTL_324_DATA + DDRSS_CTL_325_DATA + DDRSS_CTL_326_DATA + DDRSS_CTL_327_DATA + DDRSS_CTL_328_DATA + DDRSS_CTL_329_DATA + DDRSS_CTL_330_DATA + DDRSS_CTL_331_DATA + DDRSS_CTL_332_DATA + DDRSS_CTL_333_DATA + DDRSS_CTL_334_DATA + DDRSS_CTL_335_DATA + DDRSS_CTL_336_DATA + DDRSS_CTL_337_DATA + DDRSS_CTL_338_DATA + DDRSS_CTL_339_DATA + DDRSS_CTL_340_DATA + DDRSS_CTL_341_DATA + DDRSS_CTL_342_DATA + DDRSS_CTL_343_DATA + DDRSS_CTL_344_DATA + DDRSS_CTL_345_DATA + DDRSS_CTL_346_DATA + DDRSS_CTL_347_DATA + DDRSS_CTL_348_DATA + DDRSS_CTL_349_DATA + DDRSS_CTL_350_DATA + DDRSS_CTL_351_DATA + DDRSS_CTL_352_DATA + DDRSS_CTL_353_DATA + DDRSS_CTL_354_DATA + DDRSS_CTL_355_DATA + DDRSS_CTL_356_DATA + DDRSS_CTL_357_DATA + DDRSS_CTL_358_DATA + DDRSS_CTL_359_DATA + DDRSS_CTL_360_DATA + DDRSS_CTL_361_DATA + DDRSS_CTL_362_DATA + DDRSS_CTL_363_DATA + DDRSS_CTL_364_DATA + DDRSS_CTL_365_DATA + DDRSS_CTL_366_DATA + DDRSS_CTL_367_DATA + DDRSS_CTL_368_DATA + DDRSS_CTL_369_DATA + DDRSS_CTL_370_DATA + DDRSS_CTL_371_DATA + DDRSS_CTL_372_DATA + DDRSS_CTL_373_DATA + DDRSS_CTL_374_DATA + DDRSS_CTL_375_DATA + DDRSS_CTL_376_DATA + DDRSS_CTL_377_DATA + DDRSS_CTL_378_DATA + DDRSS_CTL_379_DATA + DDRSS_CTL_380_DATA + DDRSS_CTL_381_DATA + DDRSS_CTL_382_DATA + DDRSS_CTL_383_DATA + DDRSS_CTL_384_DATA + DDRSS_CTL_385_DATA + DDRSS_CTL_386_DATA + DDRSS_CTL_387_DATA + DDRSS_CTL_388_DATA + DDRSS_CTL_389_DATA + DDRSS_CTL_390_DATA + DDRSS_CTL_391_DATA + DDRSS_CTL_392_DATA + DDRSS_CTL_393_DATA + DDRSS_CTL_394_DATA + DDRSS_CTL_395_DATA + DDRSS_CTL_396_DATA + DDRSS_CTL_397_DATA + DDRSS_CTL_398_DATA + DDRSS_CTL_399_DATA + DDRSS_CTL_400_DATA + DDRSS_CTL_401_DATA + DDRSS_CTL_402_DATA + DDRSS_CTL_403_DATA + DDRSS_CTL_404_DATA + DDRSS_CTL_405_DATA + DDRSS_CTL_406_DATA + DDRSS_CTL_407_DATA + DDRSS_CTL_408_DATA + DDRSS_CTL_409_DATA + DDRSS_CTL_410_DATA + DDRSS_CTL_411_DATA + DDRSS_CTL_412_DATA + DDRSS_CTL_413_DATA + DDRSS_CTL_414_DATA + DDRSS_CTL_415_DATA + DDRSS_CTL_416_DATA + DDRSS_CTL_417_DATA + DDRSS_CTL_418_DATA + DDRSS_CTL_419_DATA + DDRSS_CTL_420_DATA + DDRSS_CTL_421_DATA + DDRSS_CTL_422_DATA + DDRSS_CTL_423_DATA + DDRSS_CTL_424_DATA + DDRSS_CTL_425_DATA + DDRSS_CTL_426_DATA + DDRSS_CTL_427_DATA + DDRSS_CTL_428_DATA + DDRSS_CTL_429_DATA + DDRSS_CTL_430_DATA + DDRSS_CTL_431_DATA + DDRSS_CTL_432_DATA + DDRSS_CTL_433_DATA + DDRSS_CTL_434_DATA + DDRSS_CTL_435_DATA + DDRSS_CTL_436_DATA + DDRSS_CTL_437_DATA + DDRSS_CTL_438_DATA + DDRSS_CTL_439_DATA + DDRSS_CTL_440_DATA + DDRSS_CTL_441_DATA + DDRSS_CTL_442_DATA + DDRSS_CTL_443_DATA + DDRSS_CTL_444_DATA + DDRSS_CTL_445_DATA + DDRSS_CTL_446_DATA + DDRSS_CTL_447_DATA + DDRSS_CTL_448_DATA + DDRSS_CTL_449_DATA + DDRSS_CTL_450_DATA + DDRSS_CTL_451_DATA + DDRSS_CTL_452_DATA + DDRSS_CTL_453_DATA + DDRSS_CTL_454_DATA + DDRSS_CTL_455_DATA + DDRSS_CTL_456_DATA + DDRSS_CTL_457_DATA + DDRSS_CTL_458_DATA + >; + + ti,pi-data = < + DDRSS_PI_00_DATA + DDRSS_PI_01_DATA + DDRSS_PI_02_DATA + DDRSS_PI_03_DATA + DDRSS_PI_04_DATA + DDRSS_PI_05_DATA + DDRSS_PI_06_DATA + DDRSS_PI_07_DATA + DDRSS_PI_08_DATA + DDRSS_PI_09_DATA + DDRSS_PI_10_DATA + DDRSS_PI_11_DATA + DDRSS_PI_12_DATA + DDRSS_PI_13_DATA + DDRSS_PI_14_DATA + DDRSS_PI_15_DATA + DDRSS_PI_16_DATA + DDRSS_PI_17_DATA + DDRSS_PI_18_DATA + DDRSS_PI_19_DATA + DDRSS_PI_20_DATA + DDRSS_PI_21_DATA + DDRSS_PI_22_DATA + DDRSS_PI_23_DATA + DDRSS_PI_24_DATA + DDRSS_PI_25_DATA + DDRSS_PI_26_DATA + DDRSS_PI_27_DATA + DDRSS_PI_28_DATA + DDRSS_PI_29_DATA + DDRSS_PI_30_DATA + DDRSS_PI_31_DATA + DDRSS_PI_32_DATA + DDRSS_PI_33_DATA + DDRSS_PI_34_DATA + DDRSS_PI_35_DATA + DDRSS_PI_36_DATA + DDRSS_PI_37_DATA + DDRSS_PI_38_DATA + DDRSS_PI_39_DATA + DDRSS_PI_40_DATA + DDRSS_PI_41_DATA + DDRSS_PI_42_DATA + DDRSS_PI_43_DATA + DDRSS_PI_44_DATA + DDRSS_PI_45_DATA + DDRSS_PI_46_DATA + DDRSS_PI_47_DATA + DDRSS_PI_48_DATA + DDRSS_PI_49_DATA + DDRSS_PI_50_DATA + DDRSS_PI_51_DATA + DDRSS_PI_52_DATA + DDRSS_PI_53_DATA + DDRSS_PI_54_DATA + DDRSS_PI_55_DATA + DDRSS_PI_56_DATA + DDRSS_PI_57_DATA + DDRSS_PI_58_DATA + DDRSS_PI_59_DATA + DDRSS_PI_60_DATA + DDRSS_PI_61_DATA + DDRSS_PI_62_DATA + DDRSS_PI_63_DATA + DDRSS_PI_64_DATA + DDRSS_PI_65_DATA + DDRSS_PI_66_DATA + DDRSS_PI_67_DATA + DDRSS_PI_68_DATA + DDRSS_PI_69_DATA + DDRSS_PI_70_DATA + DDRSS_PI_71_DATA + DDRSS_PI_72_DATA + DDRSS_PI_73_DATA + DDRSS_PI_74_DATA + DDRSS_PI_75_DATA + DDRSS_PI_76_DATA + DDRSS_PI_77_DATA + DDRSS_PI_78_DATA + DDRSS_PI_79_DATA + DDRSS_PI_80_DATA + DDRSS_PI_81_DATA + DDRSS_PI_82_DATA + DDRSS_PI_83_DATA + DDRSS_PI_84_DATA + DDRSS_PI_85_DATA + DDRSS_PI_86_DATA + DDRSS_PI_87_DATA + DDRSS_PI_88_DATA + DDRSS_PI_89_DATA + DDRSS_PI_90_DATA + DDRSS_PI_91_DATA + DDRSS_PI_92_DATA + DDRSS_PI_93_DATA + DDRSS_PI_94_DATA + DDRSS_PI_95_DATA + DDRSS_PI_96_DATA + DDRSS_PI_97_DATA + DDRSS_PI_98_DATA + DDRSS_PI_99_DATA + DDRSS_PI_100_DATA + DDRSS_PI_101_DATA + DDRSS_PI_102_DATA + DDRSS_PI_103_DATA + DDRSS_PI_104_DATA + DDRSS_PI_105_DATA + DDRSS_PI_106_DATA + DDRSS_PI_107_DATA + DDRSS_PI_108_DATA + DDRSS_PI_109_DATA + DDRSS_PI_110_DATA + DDRSS_PI_111_DATA + DDRSS_PI_112_DATA + DDRSS_PI_113_DATA + DDRSS_PI_114_DATA + DDRSS_PI_115_DATA + DDRSS_PI_116_DATA + DDRSS_PI_117_DATA + DDRSS_PI_118_DATA + DDRSS_PI_119_DATA + DDRSS_PI_120_DATA + DDRSS_PI_121_DATA + DDRSS_PI_122_DATA + DDRSS_PI_123_DATA + DDRSS_PI_124_DATA + DDRSS_PI_125_DATA + DDRSS_PI_126_DATA + DDRSS_PI_127_DATA + DDRSS_PI_128_DATA + DDRSS_PI_129_DATA + DDRSS_PI_130_DATA + DDRSS_PI_131_DATA + DDRSS_PI_132_DATA + DDRSS_PI_133_DATA + DDRSS_PI_134_DATA + DDRSS_PI_135_DATA + DDRSS_PI_136_DATA + DDRSS_PI_137_DATA + DDRSS_PI_138_DATA + DDRSS_PI_139_DATA + DDRSS_PI_140_DATA + DDRSS_PI_141_DATA + DDRSS_PI_142_DATA + DDRSS_PI_143_DATA + DDRSS_PI_144_DATA + DDRSS_PI_145_DATA + DDRSS_PI_146_DATA + DDRSS_PI_147_DATA + DDRSS_PI_148_DATA + DDRSS_PI_149_DATA + DDRSS_PI_150_DATA + DDRSS_PI_151_DATA + DDRSS_PI_152_DATA + DDRSS_PI_153_DATA + DDRSS_PI_154_DATA + DDRSS_PI_155_DATA + DDRSS_PI_156_DATA + DDRSS_PI_157_DATA + DDRSS_PI_158_DATA + DDRSS_PI_159_DATA + DDRSS_PI_160_DATA + DDRSS_PI_161_DATA + DDRSS_PI_162_DATA + DDRSS_PI_163_DATA + DDRSS_PI_164_DATA + DDRSS_PI_165_DATA + DDRSS_PI_166_DATA + DDRSS_PI_167_DATA + DDRSS_PI_168_DATA + DDRSS_PI_169_DATA + DDRSS_PI_170_DATA + DDRSS_PI_171_DATA + DDRSS_PI_172_DATA + DDRSS_PI_173_DATA + DDRSS_PI_174_DATA + DDRSS_PI_175_DATA + DDRSS_PI_176_DATA + DDRSS_PI_177_DATA + DDRSS_PI_178_DATA + DDRSS_PI_179_DATA + DDRSS_PI_180_DATA + DDRSS_PI_181_DATA + DDRSS_PI_182_DATA + DDRSS_PI_183_DATA + DDRSS_PI_184_DATA + DDRSS_PI_185_DATA + DDRSS_PI_186_DATA + DDRSS_PI_187_DATA + DDRSS_PI_188_DATA + DDRSS_PI_189_DATA + DDRSS_PI_190_DATA + DDRSS_PI_191_DATA + DDRSS_PI_192_DATA + DDRSS_PI_193_DATA + DDRSS_PI_194_DATA + DDRSS_PI_195_DATA + DDRSS_PI_196_DATA + DDRSS_PI_197_DATA + DDRSS_PI_198_DATA + DDRSS_PI_199_DATA + DDRSS_PI_200_DATA + DDRSS_PI_201_DATA + DDRSS_PI_202_DATA + DDRSS_PI_203_DATA + DDRSS_PI_204_DATA + DDRSS_PI_205_DATA + DDRSS_PI_206_DATA + DDRSS_PI_207_DATA + DDRSS_PI_208_DATA + DDRSS_PI_209_DATA + DDRSS_PI_210_DATA + DDRSS_PI_211_DATA + DDRSS_PI_212_DATA + DDRSS_PI_213_DATA + DDRSS_PI_214_DATA + DDRSS_PI_215_DATA + DDRSS_PI_216_DATA + DDRSS_PI_217_DATA + DDRSS_PI_218_DATA + DDRSS_PI_219_DATA + DDRSS_PI_220_DATA + DDRSS_PI_221_DATA + DDRSS_PI_222_DATA + DDRSS_PI_223_DATA + DDRSS_PI_224_DATA + DDRSS_PI_225_DATA + DDRSS_PI_226_DATA + DDRSS_PI_227_DATA + DDRSS_PI_228_DATA + DDRSS_PI_229_DATA + DDRSS_PI_230_DATA + DDRSS_PI_231_DATA + DDRSS_PI_232_DATA + DDRSS_PI_233_DATA + DDRSS_PI_234_DATA + DDRSS_PI_235_DATA + DDRSS_PI_236_DATA + DDRSS_PI_237_DATA + DDRSS_PI_238_DATA + DDRSS_PI_239_DATA + DDRSS_PI_240_DATA + DDRSS_PI_241_DATA + DDRSS_PI_242_DATA + DDRSS_PI_243_DATA + DDRSS_PI_244_DATA + DDRSS_PI_245_DATA + DDRSS_PI_246_DATA + DDRSS_PI_247_DATA + DDRSS_PI_248_DATA + DDRSS_PI_249_DATA + DDRSS_PI_250_DATA + DDRSS_PI_251_DATA + DDRSS_PI_252_DATA + DDRSS_PI_253_DATA + DDRSS_PI_254_DATA + DDRSS_PI_255_DATA + DDRSS_PI_256_DATA + DDRSS_PI_257_DATA + DDRSS_PI_258_DATA + DDRSS_PI_259_DATA + DDRSS_PI_260_DATA + DDRSS_PI_261_DATA + DDRSS_PI_262_DATA + DDRSS_PI_263_DATA + DDRSS_PI_264_DATA + DDRSS_PI_265_DATA + DDRSS_PI_266_DATA + DDRSS_PI_267_DATA + DDRSS_PI_268_DATA + DDRSS_PI_269_DATA + DDRSS_PI_270_DATA + DDRSS_PI_271_DATA + DDRSS_PI_272_DATA + DDRSS_PI_273_DATA + DDRSS_PI_274_DATA + DDRSS_PI_275_DATA + DDRSS_PI_276_DATA + DDRSS_PI_277_DATA + DDRSS_PI_278_DATA + DDRSS_PI_279_DATA + DDRSS_PI_280_DATA + DDRSS_PI_281_DATA + DDRSS_PI_282_DATA + DDRSS_PI_283_DATA + DDRSS_PI_284_DATA + DDRSS_PI_285_DATA + DDRSS_PI_286_DATA + DDRSS_PI_287_DATA + DDRSS_PI_288_DATA + DDRSS_PI_289_DATA + DDRSS_PI_290_DATA + DDRSS_PI_291_DATA + DDRSS_PI_292_DATA + DDRSS_PI_293_DATA + DDRSS_PI_294_DATA + DDRSS_PI_295_DATA + DDRSS_PI_296_DATA + DDRSS_PI_297_DATA + DDRSS_PI_298_DATA + DDRSS_PI_299_DATA + >; + + ti,phy-data = < + DDRSS_PHY_00_DATA + DDRSS_PHY_01_DATA + DDRSS_PHY_02_DATA + DDRSS_PHY_03_DATA + DDRSS_PHY_04_DATA + DDRSS_PHY_05_DATA + DDRSS_PHY_06_DATA + DDRSS_PHY_07_DATA + DDRSS_PHY_08_DATA + DDRSS_PHY_09_DATA + DDRSS_PHY_10_DATA + DDRSS_PHY_11_DATA + DDRSS_PHY_12_DATA + DDRSS_PHY_13_DATA + DDRSS_PHY_14_DATA + DDRSS_PHY_15_DATA + DDRSS_PHY_16_DATA + DDRSS_PHY_17_DATA + DDRSS_PHY_18_DATA + DDRSS_PHY_19_DATA + DDRSS_PHY_20_DATA + DDRSS_PHY_21_DATA + DDRSS_PHY_22_DATA + DDRSS_PHY_23_DATA + DDRSS_PHY_24_DATA + DDRSS_PHY_25_DATA + DDRSS_PHY_26_DATA + DDRSS_PHY_27_DATA + DDRSS_PHY_28_DATA + DDRSS_PHY_29_DATA + DDRSS_PHY_30_DATA + DDRSS_PHY_31_DATA + DDRSS_PHY_32_DATA + DDRSS_PHY_33_DATA + DDRSS_PHY_34_DATA + DDRSS_PHY_35_DATA + DDRSS_PHY_36_DATA + DDRSS_PHY_37_DATA + DDRSS_PHY_38_DATA + DDRSS_PHY_39_DATA + DDRSS_PHY_40_DATA + DDRSS_PHY_41_DATA + DDRSS_PHY_42_DATA + DDRSS_PHY_43_DATA + DDRSS_PHY_44_DATA + DDRSS_PHY_45_DATA + DDRSS_PHY_46_DATA + DDRSS_PHY_47_DATA + DDRSS_PHY_48_DATA + DDRSS_PHY_49_DATA + DDRSS_PHY_50_DATA + DDRSS_PHY_51_DATA + DDRSS_PHY_52_DATA + DDRSS_PHY_53_DATA + DDRSS_PHY_54_DATA + DDRSS_PHY_55_DATA + DDRSS_PHY_56_DATA + DDRSS_PHY_57_DATA + DDRSS_PHY_58_DATA + DDRSS_PHY_59_DATA + DDRSS_PHY_60_DATA + DDRSS_PHY_61_DATA + DDRSS_PHY_62_DATA + DDRSS_PHY_63_DATA + DDRSS_PHY_64_DATA + DDRSS_PHY_65_DATA + DDRSS_PHY_66_DATA + DDRSS_PHY_67_DATA + DDRSS_PHY_68_DATA + DDRSS_PHY_69_DATA + DDRSS_PHY_70_DATA + DDRSS_PHY_71_DATA + DDRSS_PHY_72_DATA + DDRSS_PHY_73_DATA + DDRSS_PHY_74_DATA + DDRSS_PHY_75_DATA + DDRSS_PHY_76_DATA + DDRSS_PHY_77_DATA + DDRSS_PHY_78_DATA + DDRSS_PHY_79_DATA + DDRSS_PHY_80_DATA + DDRSS_PHY_81_DATA + DDRSS_PHY_82_DATA + DDRSS_PHY_83_DATA + DDRSS_PHY_84_DATA + DDRSS_PHY_85_DATA + DDRSS_PHY_86_DATA + DDRSS_PHY_87_DATA + DDRSS_PHY_88_DATA + DDRSS_PHY_89_DATA + DDRSS_PHY_90_DATA + DDRSS_PHY_91_DATA + DDRSS_PHY_92_DATA + DDRSS_PHY_93_DATA + DDRSS_PHY_94_DATA + DDRSS_PHY_95_DATA + DDRSS_PHY_96_DATA + DDRSS_PHY_97_DATA + DDRSS_PHY_98_DATA + DDRSS_PHY_99_DATA + DDRSS_PHY_100_DATA + DDRSS_PHY_101_DATA + DDRSS_PHY_102_DATA + DDRSS_PHY_103_DATA + DDRSS_PHY_104_DATA + DDRSS_PHY_105_DATA + DDRSS_PHY_106_DATA + DDRSS_PHY_107_DATA + DDRSS_PHY_108_DATA + DDRSS_PHY_109_DATA + DDRSS_PHY_110_DATA + DDRSS_PHY_111_DATA + DDRSS_PHY_112_DATA + DDRSS_PHY_113_DATA + DDRSS_PHY_114_DATA + DDRSS_PHY_115_DATA + DDRSS_PHY_116_DATA + DDRSS_PHY_117_DATA + DDRSS_PHY_118_DATA + DDRSS_PHY_119_DATA + DDRSS_PHY_120_DATA + DDRSS_PHY_121_DATA + DDRSS_PHY_122_DATA + DDRSS_PHY_123_DATA + DDRSS_PHY_124_DATA + DDRSS_PHY_125_DATA + DDRSS_PHY_126_DATA + DDRSS_PHY_127_DATA + DDRSS_PHY_128_DATA + DDRSS_PHY_129_DATA + DDRSS_PHY_130_DATA + DDRSS_PHY_131_DATA + DDRSS_PHY_132_DATA + DDRSS_PHY_133_DATA + DDRSS_PHY_134_DATA + DDRSS_PHY_135_DATA + DDRSS_PHY_136_DATA + DDRSS_PHY_137_DATA + DDRSS_PHY_138_DATA + DDRSS_PHY_139_DATA + DDRSS_PHY_140_DATA + DDRSS_PHY_141_DATA + DDRSS_PHY_142_DATA + DDRSS_PHY_143_DATA + DDRSS_PHY_144_DATA + DDRSS_PHY_145_DATA + DDRSS_PHY_146_DATA + DDRSS_PHY_147_DATA + DDRSS_PHY_148_DATA + DDRSS_PHY_149_DATA + DDRSS_PHY_150_DATA + DDRSS_PHY_151_DATA + DDRSS_PHY_152_DATA + DDRSS_PHY_153_DATA + DDRSS_PHY_154_DATA + DDRSS_PHY_155_DATA + DDRSS_PHY_156_DATA + DDRSS_PHY_157_DATA + DDRSS_PHY_158_DATA + DDRSS_PHY_159_DATA + DDRSS_PHY_160_DATA + DDRSS_PHY_161_DATA + DDRSS_PHY_162_DATA + DDRSS_PHY_163_DATA + DDRSS_PHY_164_DATA + DDRSS_PHY_165_DATA + DDRSS_PHY_166_DATA + DDRSS_PHY_167_DATA + DDRSS_PHY_168_DATA + DDRSS_PHY_169_DATA + DDRSS_PHY_170_DATA + DDRSS_PHY_171_DATA + DDRSS_PHY_172_DATA + DDRSS_PHY_173_DATA + DDRSS_PHY_174_DATA + DDRSS_PHY_175_DATA + DDRSS_PHY_176_DATA + DDRSS_PHY_177_DATA + DDRSS_PHY_178_DATA + DDRSS_PHY_179_DATA + DDRSS_PHY_180_DATA + DDRSS_PHY_181_DATA + DDRSS_PHY_182_DATA + DDRSS_PHY_183_DATA + DDRSS_PHY_184_DATA + DDRSS_PHY_185_DATA + DDRSS_PHY_186_DATA + DDRSS_PHY_187_DATA + DDRSS_PHY_188_DATA + DDRSS_PHY_189_DATA + DDRSS_PHY_190_DATA + DDRSS_PHY_191_DATA + DDRSS_PHY_192_DATA + DDRSS_PHY_193_DATA + DDRSS_PHY_194_DATA + DDRSS_PHY_195_DATA + DDRSS_PHY_196_DATA + DDRSS_PHY_197_DATA + DDRSS_PHY_198_DATA + DDRSS_PHY_199_DATA + DDRSS_PHY_200_DATA + DDRSS_PHY_201_DATA + DDRSS_PHY_202_DATA + DDRSS_PHY_203_DATA + DDRSS_PHY_204_DATA + DDRSS_PHY_205_DATA + DDRSS_PHY_206_DATA + DDRSS_PHY_207_DATA + DDRSS_PHY_208_DATA + DDRSS_PHY_209_DATA + DDRSS_PHY_210_DATA + DDRSS_PHY_211_DATA + DDRSS_PHY_212_DATA + DDRSS_PHY_213_DATA + DDRSS_PHY_214_DATA + DDRSS_PHY_215_DATA + DDRSS_PHY_216_DATA + DDRSS_PHY_217_DATA + DDRSS_PHY_218_DATA + DDRSS_PHY_219_DATA + DDRSS_PHY_220_DATA + DDRSS_PHY_221_DATA + DDRSS_PHY_222_DATA + DDRSS_PHY_223_DATA + DDRSS_PHY_224_DATA + DDRSS_PHY_225_DATA + DDRSS_PHY_226_DATA + DDRSS_PHY_227_DATA + DDRSS_PHY_228_DATA + DDRSS_PHY_229_DATA + DDRSS_PHY_230_DATA + DDRSS_PHY_231_DATA + DDRSS_PHY_232_DATA + DDRSS_PHY_233_DATA + DDRSS_PHY_234_DATA + DDRSS_PHY_235_DATA + DDRSS_PHY_236_DATA + DDRSS_PHY_237_DATA + DDRSS_PHY_238_DATA + DDRSS_PHY_239_DATA + DDRSS_PHY_240_DATA + DDRSS_PHY_241_DATA + DDRSS_PHY_242_DATA + DDRSS_PHY_243_DATA + DDRSS_PHY_244_DATA + DDRSS_PHY_245_DATA + DDRSS_PHY_246_DATA + DDRSS_PHY_247_DATA + DDRSS_PHY_248_DATA + DDRSS_PHY_249_DATA + DDRSS_PHY_250_DATA + DDRSS_PHY_251_DATA + DDRSS_PHY_252_DATA + DDRSS_PHY_253_DATA + DDRSS_PHY_254_DATA + DDRSS_PHY_255_DATA + DDRSS_PHY_256_DATA + DDRSS_PHY_257_DATA + DDRSS_PHY_258_DATA + DDRSS_PHY_259_DATA + DDRSS_PHY_260_DATA + DDRSS_PHY_261_DATA + DDRSS_PHY_262_DATA + DDRSS_PHY_263_DATA + DDRSS_PHY_264_DATA + DDRSS_PHY_265_DATA + DDRSS_PHY_266_DATA + DDRSS_PHY_267_DATA + DDRSS_PHY_268_DATA + DDRSS_PHY_269_DATA + DDRSS_PHY_270_DATA + DDRSS_PHY_271_DATA + DDRSS_PHY_272_DATA + DDRSS_PHY_273_DATA + DDRSS_PHY_274_DATA + DDRSS_PHY_275_DATA + DDRSS_PHY_276_DATA + DDRSS_PHY_277_DATA + DDRSS_PHY_278_DATA + DDRSS_PHY_279_DATA + DDRSS_PHY_280_DATA + DDRSS_PHY_281_DATA + DDRSS_PHY_282_DATA + DDRSS_PHY_283_DATA + DDRSS_PHY_284_DATA + DDRSS_PHY_285_DATA + DDRSS_PHY_286_DATA + DDRSS_PHY_287_DATA + DDRSS_PHY_288_DATA + DDRSS_PHY_289_DATA + DDRSS_PHY_290_DATA + DDRSS_PHY_291_DATA + DDRSS_PHY_292_DATA + DDRSS_PHY_293_DATA + DDRSS_PHY_294_DATA + DDRSS_PHY_295_DATA + DDRSS_PHY_296_DATA + DDRSS_PHY_297_DATA + DDRSS_PHY_298_DATA + DDRSS_PHY_299_DATA + DDRSS_PHY_300_DATA + DDRSS_PHY_301_DATA + DDRSS_PHY_302_DATA + DDRSS_PHY_303_DATA + DDRSS_PHY_304_DATA + DDRSS_PHY_305_DATA + DDRSS_PHY_306_DATA + DDRSS_PHY_307_DATA + DDRSS_PHY_308_DATA + DDRSS_PHY_309_DATA + DDRSS_PHY_310_DATA + DDRSS_PHY_311_DATA + DDRSS_PHY_312_DATA + DDRSS_PHY_313_DATA + DDRSS_PHY_314_DATA + DDRSS_PHY_315_DATA + DDRSS_PHY_316_DATA + DDRSS_PHY_317_DATA + DDRSS_PHY_318_DATA + DDRSS_PHY_319_DATA + DDRSS_PHY_320_DATA + DDRSS_PHY_321_DATA + DDRSS_PHY_322_DATA + DDRSS_PHY_323_DATA + DDRSS_PHY_324_DATA + DDRSS_PHY_325_DATA + DDRSS_PHY_326_DATA + DDRSS_PHY_327_DATA + DDRSS_PHY_328_DATA + DDRSS_PHY_329_DATA + DDRSS_PHY_330_DATA + DDRSS_PHY_331_DATA + DDRSS_PHY_332_DATA + DDRSS_PHY_333_DATA + DDRSS_PHY_334_DATA + DDRSS_PHY_335_DATA + DDRSS_PHY_336_DATA + DDRSS_PHY_337_DATA + DDRSS_PHY_338_DATA + DDRSS_PHY_339_DATA + DDRSS_PHY_340_DATA + DDRSS_PHY_341_DATA + DDRSS_PHY_342_DATA + DDRSS_PHY_343_DATA + DDRSS_PHY_344_DATA + DDRSS_PHY_345_DATA + DDRSS_PHY_346_DATA + DDRSS_PHY_347_DATA + DDRSS_PHY_348_DATA + DDRSS_PHY_349_DATA + DDRSS_PHY_350_DATA + DDRSS_PHY_351_DATA + DDRSS_PHY_352_DATA + DDRSS_PHY_353_DATA + DDRSS_PHY_354_DATA + DDRSS_PHY_355_DATA + DDRSS_PHY_356_DATA + DDRSS_PHY_357_DATA + DDRSS_PHY_358_DATA + DDRSS_PHY_359_DATA + DDRSS_PHY_360_DATA + DDRSS_PHY_361_DATA + DDRSS_PHY_362_DATA + DDRSS_PHY_363_DATA + DDRSS_PHY_364_DATA + DDRSS_PHY_365_DATA + DDRSS_PHY_366_DATA + DDRSS_PHY_367_DATA + DDRSS_PHY_368_DATA + DDRSS_PHY_369_DATA + DDRSS_PHY_370_DATA + DDRSS_PHY_371_DATA + DDRSS_PHY_372_DATA + DDRSS_PHY_373_DATA + DDRSS_PHY_374_DATA + DDRSS_PHY_375_DATA + DDRSS_PHY_376_DATA + DDRSS_PHY_377_DATA + DDRSS_PHY_378_DATA + DDRSS_PHY_379_DATA + DDRSS_PHY_380_DATA + DDRSS_PHY_381_DATA + DDRSS_PHY_382_DATA + DDRSS_PHY_383_DATA + DDRSS_PHY_384_DATA + DDRSS_PHY_385_DATA + DDRSS_PHY_386_DATA + DDRSS_PHY_387_DATA + DDRSS_PHY_388_DATA + DDRSS_PHY_389_DATA + DDRSS_PHY_390_DATA + DDRSS_PHY_391_DATA + DDRSS_PHY_392_DATA + DDRSS_PHY_393_DATA + DDRSS_PHY_394_DATA + DDRSS_PHY_395_DATA + DDRSS_PHY_396_DATA + DDRSS_PHY_397_DATA + DDRSS_PHY_398_DATA + DDRSS_PHY_399_DATA + DDRSS_PHY_400_DATA + DDRSS_PHY_401_DATA + DDRSS_PHY_402_DATA + DDRSS_PHY_403_DATA + DDRSS_PHY_404_DATA + DDRSS_PHY_405_DATA + DDRSS_PHY_406_DATA + DDRSS_PHY_407_DATA + DDRSS_PHY_408_DATA + DDRSS_PHY_409_DATA + DDRSS_PHY_410_DATA + DDRSS_PHY_411_DATA + DDRSS_PHY_412_DATA + DDRSS_PHY_413_DATA + DDRSS_PHY_414_DATA + DDRSS_PHY_415_DATA + DDRSS_PHY_416_DATA + DDRSS_PHY_417_DATA + DDRSS_PHY_418_DATA + DDRSS_PHY_419_DATA + DDRSS_PHY_420_DATA + DDRSS_PHY_421_DATA + DDRSS_PHY_422_DATA + DDRSS_PHY_423_DATA + DDRSS_PHY_424_DATA + DDRSS_PHY_425_DATA + DDRSS_PHY_426_DATA + DDRSS_PHY_427_DATA + DDRSS_PHY_428_DATA + DDRSS_PHY_429_DATA + DDRSS_PHY_430_DATA + DDRSS_PHY_431_DATA + DDRSS_PHY_432_DATA + DDRSS_PHY_433_DATA + DDRSS_PHY_434_DATA + DDRSS_PHY_435_DATA + DDRSS_PHY_436_DATA + DDRSS_PHY_437_DATA + DDRSS_PHY_438_DATA + DDRSS_PHY_439_DATA + DDRSS_PHY_440_DATA + DDRSS_PHY_441_DATA + DDRSS_PHY_442_DATA + DDRSS_PHY_443_DATA + DDRSS_PHY_444_DATA + DDRSS_PHY_445_DATA + DDRSS_PHY_446_DATA + DDRSS_PHY_447_DATA + DDRSS_PHY_448_DATA + DDRSS_PHY_449_DATA + DDRSS_PHY_450_DATA + DDRSS_PHY_451_DATA + DDRSS_PHY_452_DATA + DDRSS_PHY_453_DATA + DDRSS_PHY_454_DATA + DDRSS_PHY_455_DATA + DDRSS_PHY_456_DATA + DDRSS_PHY_457_DATA + DDRSS_PHY_458_DATA + DDRSS_PHY_459_DATA + DDRSS_PHY_460_DATA + DDRSS_PHY_461_DATA + DDRSS_PHY_462_DATA + DDRSS_PHY_463_DATA + DDRSS_PHY_464_DATA + DDRSS_PHY_465_DATA + DDRSS_PHY_466_DATA + DDRSS_PHY_467_DATA + DDRSS_PHY_468_DATA + DDRSS_PHY_469_DATA + DDRSS_PHY_470_DATA + DDRSS_PHY_471_DATA + DDRSS_PHY_472_DATA + DDRSS_PHY_473_DATA + DDRSS_PHY_474_DATA + DDRSS_PHY_475_DATA + DDRSS_PHY_476_DATA + DDRSS_PHY_477_DATA + DDRSS_PHY_478_DATA + DDRSS_PHY_479_DATA + DDRSS_PHY_480_DATA + DDRSS_PHY_481_DATA + DDRSS_PHY_482_DATA + DDRSS_PHY_483_DATA + DDRSS_PHY_484_DATA + DDRSS_PHY_485_DATA + DDRSS_PHY_486_DATA + DDRSS_PHY_487_DATA + DDRSS_PHY_488_DATA + DDRSS_PHY_489_DATA + DDRSS_PHY_490_DATA + DDRSS_PHY_491_DATA + DDRSS_PHY_492_DATA + DDRSS_PHY_493_DATA + DDRSS_PHY_494_DATA + DDRSS_PHY_495_DATA + DDRSS_PHY_496_DATA + DDRSS_PHY_497_DATA + DDRSS_PHY_498_DATA + DDRSS_PHY_499_DATA + DDRSS_PHY_500_DATA + DDRSS_PHY_501_DATA + DDRSS_PHY_502_DATA + DDRSS_PHY_503_DATA + DDRSS_PHY_504_DATA + DDRSS_PHY_505_DATA + DDRSS_PHY_506_DATA + DDRSS_PHY_507_DATA + DDRSS_PHY_508_DATA + DDRSS_PHY_509_DATA + DDRSS_PHY_510_DATA + DDRSS_PHY_511_DATA + DDRSS_PHY_512_DATA + DDRSS_PHY_513_DATA + DDRSS_PHY_514_DATA + DDRSS_PHY_515_DATA + DDRSS_PHY_516_DATA + DDRSS_PHY_517_DATA + DDRSS_PHY_518_DATA + DDRSS_PHY_519_DATA + DDRSS_PHY_520_DATA + DDRSS_PHY_521_DATA + DDRSS_PHY_522_DATA + DDRSS_PHY_523_DATA + DDRSS_PHY_524_DATA + DDRSS_PHY_525_DATA + DDRSS_PHY_526_DATA + DDRSS_PHY_527_DATA + DDRSS_PHY_528_DATA + DDRSS_PHY_529_DATA + DDRSS_PHY_530_DATA + DDRSS_PHY_531_DATA + DDRSS_PHY_532_DATA + DDRSS_PHY_533_DATA + DDRSS_PHY_534_DATA + DDRSS_PHY_535_DATA + DDRSS_PHY_536_DATA + DDRSS_PHY_537_DATA + DDRSS_PHY_538_DATA + DDRSS_PHY_539_DATA + DDRSS_PHY_540_DATA + DDRSS_PHY_541_DATA + DDRSS_PHY_542_DATA + DDRSS_PHY_543_DATA + DDRSS_PHY_544_DATA + DDRSS_PHY_545_DATA + DDRSS_PHY_546_DATA + DDRSS_PHY_547_DATA + DDRSS_PHY_548_DATA + DDRSS_PHY_549_DATA + DDRSS_PHY_550_DATA + DDRSS_PHY_551_DATA + DDRSS_PHY_552_DATA + DDRSS_PHY_553_DATA + DDRSS_PHY_554_DATA + DDRSS_PHY_555_DATA + DDRSS_PHY_556_DATA + DDRSS_PHY_557_DATA + DDRSS_PHY_558_DATA + DDRSS_PHY_559_DATA + DDRSS_PHY_560_DATA + DDRSS_PHY_561_DATA + DDRSS_PHY_562_DATA + DDRSS_PHY_563_DATA + DDRSS_PHY_564_DATA + DDRSS_PHY_565_DATA + DDRSS_PHY_566_DATA + DDRSS_PHY_567_DATA + DDRSS_PHY_568_DATA + DDRSS_PHY_569_DATA + DDRSS_PHY_570_DATA + DDRSS_PHY_571_DATA + DDRSS_PHY_572_DATA + DDRSS_PHY_573_DATA + DDRSS_PHY_574_DATA + DDRSS_PHY_575_DATA + DDRSS_PHY_576_DATA + DDRSS_PHY_577_DATA + DDRSS_PHY_578_DATA + DDRSS_PHY_579_DATA + DDRSS_PHY_580_DATA + DDRSS_PHY_581_DATA + DDRSS_PHY_582_DATA + DDRSS_PHY_583_DATA + DDRSS_PHY_584_DATA + DDRSS_PHY_585_DATA + DDRSS_PHY_586_DATA + DDRSS_PHY_587_DATA + DDRSS_PHY_588_DATA + DDRSS_PHY_589_DATA + DDRSS_PHY_590_DATA + DDRSS_PHY_591_DATA + DDRSS_PHY_592_DATA + DDRSS_PHY_593_DATA + DDRSS_PHY_594_DATA + DDRSS_PHY_595_DATA + DDRSS_PHY_596_DATA + DDRSS_PHY_597_DATA + DDRSS_PHY_598_DATA + DDRSS_PHY_599_DATA + DDRSS_PHY_600_DATA + DDRSS_PHY_601_DATA + DDRSS_PHY_602_DATA + DDRSS_PHY_603_DATA + DDRSS_PHY_604_DATA + DDRSS_PHY_605_DATA + DDRSS_PHY_606_DATA + DDRSS_PHY_607_DATA + DDRSS_PHY_608_DATA + DDRSS_PHY_609_DATA + DDRSS_PHY_610_DATA + DDRSS_PHY_611_DATA + DDRSS_PHY_612_DATA + DDRSS_PHY_613_DATA + DDRSS_PHY_614_DATA + DDRSS_PHY_615_DATA + DDRSS_PHY_616_DATA + DDRSS_PHY_617_DATA + DDRSS_PHY_618_DATA + DDRSS_PHY_619_DATA + DDRSS_PHY_620_DATA + DDRSS_PHY_621_DATA + DDRSS_PHY_622_DATA + DDRSS_PHY_623_DATA + DDRSS_PHY_624_DATA + DDRSS_PHY_625_DATA + DDRSS_PHY_626_DATA + DDRSS_PHY_627_DATA + DDRSS_PHY_628_DATA + DDRSS_PHY_629_DATA + DDRSS_PHY_630_DATA + DDRSS_PHY_631_DATA + DDRSS_PHY_632_DATA + DDRSS_PHY_633_DATA + DDRSS_PHY_634_DATA + DDRSS_PHY_635_DATA + DDRSS_PHY_636_DATA + DDRSS_PHY_637_DATA + DDRSS_PHY_638_DATA + DDRSS_PHY_639_DATA + DDRSS_PHY_640_DATA + DDRSS_PHY_641_DATA + DDRSS_PHY_642_DATA + DDRSS_PHY_643_DATA + DDRSS_PHY_644_DATA + DDRSS_PHY_645_DATA + DDRSS_PHY_646_DATA + DDRSS_PHY_647_DATA + DDRSS_PHY_648_DATA + DDRSS_PHY_649_DATA + DDRSS_PHY_650_DATA + DDRSS_PHY_651_DATA + DDRSS_PHY_652_DATA + DDRSS_PHY_653_DATA + DDRSS_PHY_654_DATA + DDRSS_PHY_655_DATA + DDRSS_PHY_656_DATA + DDRSS_PHY_657_DATA + DDRSS_PHY_658_DATA + DDRSS_PHY_659_DATA + DDRSS_PHY_660_DATA + DDRSS_PHY_661_DATA + DDRSS_PHY_662_DATA + DDRSS_PHY_663_DATA + DDRSS_PHY_664_DATA + DDRSS_PHY_665_DATA + DDRSS_PHY_666_DATA + DDRSS_PHY_667_DATA + DDRSS_PHY_668_DATA + DDRSS_PHY_669_DATA + DDRSS_PHY_670_DATA + DDRSS_PHY_671_DATA + DDRSS_PHY_672_DATA + DDRSS_PHY_673_DATA + DDRSS_PHY_674_DATA + DDRSS_PHY_675_DATA + DDRSS_PHY_676_DATA + DDRSS_PHY_677_DATA + DDRSS_PHY_678_DATA + DDRSS_PHY_679_DATA + DDRSS_PHY_680_DATA + DDRSS_PHY_681_DATA + DDRSS_PHY_682_DATA + DDRSS_PHY_683_DATA + DDRSS_PHY_684_DATA + DDRSS_PHY_685_DATA + DDRSS_PHY_686_DATA + DDRSS_PHY_687_DATA + DDRSS_PHY_688_DATA + DDRSS_PHY_689_DATA + DDRSS_PHY_690_DATA + DDRSS_PHY_691_DATA + DDRSS_PHY_692_DATA + DDRSS_PHY_693_DATA + DDRSS_PHY_694_DATA + DDRSS_PHY_695_DATA + DDRSS_PHY_696_DATA + DDRSS_PHY_697_DATA + DDRSS_PHY_698_DATA + DDRSS_PHY_699_DATA + DDRSS_PHY_700_DATA + DDRSS_PHY_701_DATA + DDRSS_PHY_702_DATA + DDRSS_PHY_703_DATA + DDRSS_PHY_704_DATA + DDRSS_PHY_705_DATA + DDRSS_PHY_706_DATA + DDRSS_PHY_707_DATA + DDRSS_PHY_708_DATA + DDRSS_PHY_709_DATA + DDRSS_PHY_710_DATA + DDRSS_PHY_711_DATA + DDRSS_PHY_712_DATA + DDRSS_PHY_713_DATA + DDRSS_PHY_714_DATA + DDRSS_PHY_715_DATA + DDRSS_PHY_716_DATA + DDRSS_PHY_717_DATA + DDRSS_PHY_718_DATA + DDRSS_PHY_719_DATA + DDRSS_PHY_720_DATA + DDRSS_PHY_721_DATA + DDRSS_PHY_722_DATA + DDRSS_PHY_723_DATA + DDRSS_PHY_724_DATA + DDRSS_PHY_725_DATA + DDRSS_PHY_726_DATA + DDRSS_PHY_727_DATA + DDRSS_PHY_728_DATA + DDRSS_PHY_729_DATA + DDRSS_PHY_730_DATA + DDRSS_PHY_731_DATA + DDRSS_PHY_732_DATA + DDRSS_PHY_733_DATA + DDRSS_PHY_734_DATA + DDRSS_PHY_735_DATA + DDRSS_PHY_736_DATA + DDRSS_PHY_737_DATA + DDRSS_PHY_738_DATA + DDRSS_PHY_739_DATA + DDRSS_PHY_740_DATA + DDRSS_PHY_741_DATA + DDRSS_PHY_742_DATA + DDRSS_PHY_743_DATA + DDRSS_PHY_744_DATA + DDRSS_PHY_745_DATA + DDRSS_PHY_746_DATA + DDRSS_PHY_747_DATA + DDRSS_PHY_748_DATA + DDRSS_PHY_749_DATA + DDRSS_PHY_750_DATA + DDRSS_PHY_751_DATA + DDRSS_PHY_752_DATA + DDRSS_PHY_753_DATA + DDRSS_PHY_754_DATA + DDRSS_PHY_755_DATA + DDRSS_PHY_756_DATA + DDRSS_PHY_757_DATA + DDRSS_PHY_758_DATA + DDRSS_PHY_759_DATA + DDRSS_PHY_760_DATA + DDRSS_PHY_761_DATA + DDRSS_PHY_762_DATA + DDRSS_PHY_763_DATA + DDRSS_PHY_764_DATA + DDRSS_PHY_765_DATA + DDRSS_PHY_766_DATA + DDRSS_PHY_767_DATA + DDRSS_PHY_768_DATA + DDRSS_PHY_769_DATA + DDRSS_PHY_770_DATA + DDRSS_PHY_771_DATA + DDRSS_PHY_772_DATA + DDRSS_PHY_773_DATA + DDRSS_PHY_774_DATA + DDRSS_PHY_775_DATA + DDRSS_PHY_776_DATA + DDRSS_PHY_777_DATA + DDRSS_PHY_778_DATA + DDRSS_PHY_779_DATA + DDRSS_PHY_780_DATA + DDRSS_PHY_781_DATA + DDRSS_PHY_782_DATA + DDRSS_PHY_783_DATA + DDRSS_PHY_784_DATA + DDRSS_PHY_785_DATA + DDRSS_PHY_786_DATA + DDRSS_PHY_787_DATA + DDRSS_PHY_788_DATA + DDRSS_PHY_789_DATA + DDRSS_PHY_790_DATA + DDRSS_PHY_791_DATA + DDRSS_PHY_792_DATA + DDRSS_PHY_793_DATA + DDRSS_PHY_794_DATA + DDRSS_PHY_795_DATA + DDRSS_PHY_796_DATA + DDRSS_PHY_797_DATA + DDRSS_PHY_798_DATA + DDRSS_PHY_799_DATA + DDRSS_PHY_800_DATA + DDRSS_PHY_801_DATA + DDRSS_PHY_802_DATA + DDRSS_PHY_803_DATA + DDRSS_PHY_804_DATA + DDRSS_PHY_805_DATA + DDRSS_PHY_806_DATA + DDRSS_PHY_807_DATA + DDRSS_PHY_808_DATA + DDRSS_PHY_809_DATA + DDRSS_PHY_810_DATA + DDRSS_PHY_811_DATA + DDRSS_PHY_812_DATA + DDRSS_PHY_813_DATA + DDRSS_PHY_814_DATA + DDRSS_PHY_815_DATA + DDRSS_PHY_816_DATA + DDRSS_PHY_817_DATA + DDRSS_PHY_818_DATA + DDRSS_PHY_819_DATA + DDRSS_PHY_820_DATA + DDRSS_PHY_821_DATA + DDRSS_PHY_822_DATA + DDRSS_PHY_823_DATA + DDRSS_PHY_824_DATA + DDRSS_PHY_825_DATA + DDRSS_PHY_826_DATA + DDRSS_PHY_827_DATA + DDRSS_PHY_828_DATA + DDRSS_PHY_829_DATA + DDRSS_PHY_830_DATA + DDRSS_PHY_831_DATA + DDRSS_PHY_832_DATA + DDRSS_PHY_833_DATA + DDRSS_PHY_834_DATA + DDRSS_PHY_835_DATA + DDRSS_PHY_836_DATA + DDRSS_PHY_837_DATA + DDRSS_PHY_838_DATA + DDRSS_PHY_839_DATA + DDRSS_PHY_840_DATA + DDRSS_PHY_841_DATA + DDRSS_PHY_842_DATA + DDRSS_PHY_843_DATA + DDRSS_PHY_844_DATA + DDRSS_PHY_845_DATA + DDRSS_PHY_846_DATA + DDRSS_PHY_847_DATA + DDRSS_PHY_848_DATA + DDRSS_PHY_849_DATA + DDRSS_PHY_850_DATA + DDRSS_PHY_851_DATA + DDRSS_PHY_852_DATA + DDRSS_PHY_853_DATA + DDRSS_PHY_854_DATA + DDRSS_PHY_855_DATA + DDRSS_PHY_856_DATA + DDRSS_PHY_857_DATA + DDRSS_PHY_858_DATA + DDRSS_PHY_859_DATA + DDRSS_PHY_860_DATA + DDRSS_PHY_861_DATA + DDRSS_PHY_862_DATA + DDRSS_PHY_863_DATA + DDRSS_PHY_864_DATA + DDRSS_PHY_865_DATA + DDRSS_PHY_866_DATA + DDRSS_PHY_867_DATA + DDRSS_PHY_868_DATA + DDRSS_PHY_869_DATA + DDRSS_PHY_870_DATA + DDRSS_PHY_871_DATA + DDRSS_PHY_872_DATA + DDRSS_PHY_873_DATA + DDRSS_PHY_874_DATA + DDRSS_PHY_875_DATA + DDRSS_PHY_876_DATA + DDRSS_PHY_877_DATA + DDRSS_PHY_878_DATA + DDRSS_PHY_879_DATA + DDRSS_PHY_880_DATA + DDRSS_PHY_881_DATA + DDRSS_PHY_882_DATA + DDRSS_PHY_883_DATA + DDRSS_PHY_884_DATA + DDRSS_PHY_885_DATA + DDRSS_PHY_886_DATA + DDRSS_PHY_887_DATA + DDRSS_PHY_888_DATA + DDRSS_PHY_889_DATA + DDRSS_PHY_890_DATA + DDRSS_PHY_891_DATA + DDRSS_PHY_892_DATA + DDRSS_PHY_893_DATA + DDRSS_PHY_894_DATA + DDRSS_PHY_895_DATA + DDRSS_PHY_896_DATA + DDRSS_PHY_897_DATA + DDRSS_PHY_898_DATA + DDRSS_PHY_899_DATA + DDRSS_PHY_900_DATA + DDRSS_PHY_901_DATA + DDRSS_PHY_902_DATA + DDRSS_PHY_903_DATA + DDRSS_PHY_904_DATA + DDRSS_PHY_905_DATA + DDRSS_PHY_906_DATA + DDRSS_PHY_907_DATA + DDRSS_PHY_908_DATA + DDRSS_PHY_909_DATA + DDRSS_PHY_910_DATA + DDRSS_PHY_911_DATA + DDRSS_PHY_912_DATA + DDRSS_PHY_913_DATA + DDRSS_PHY_914_DATA + DDRSS_PHY_915_DATA + DDRSS_PHY_916_DATA + DDRSS_PHY_917_DATA + DDRSS_PHY_918_DATA + DDRSS_PHY_919_DATA + DDRSS_PHY_920_DATA + DDRSS_PHY_921_DATA + DDRSS_PHY_922_DATA + DDRSS_PHY_923_DATA + DDRSS_PHY_924_DATA + DDRSS_PHY_925_DATA + DDRSS_PHY_926_DATA + DDRSS_PHY_927_DATA + DDRSS_PHY_928_DATA + DDRSS_PHY_929_DATA + DDRSS_PHY_930_DATA + DDRSS_PHY_931_DATA + DDRSS_PHY_932_DATA + DDRSS_PHY_933_DATA + DDRSS_PHY_934_DATA + DDRSS_PHY_935_DATA + DDRSS_PHY_936_DATA + DDRSS_PHY_937_DATA + DDRSS_PHY_938_DATA + DDRSS_PHY_939_DATA + DDRSS_PHY_940_DATA + DDRSS_PHY_941_DATA + DDRSS_PHY_942_DATA + DDRSS_PHY_943_DATA + DDRSS_PHY_944_DATA + DDRSS_PHY_945_DATA + DDRSS_PHY_946_DATA + DDRSS_PHY_947_DATA + DDRSS_PHY_948_DATA + DDRSS_PHY_949_DATA + DDRSS_PHY_950_DATA + DDRSS_PHY_951_DATA + DDRSS_PHY_952_DATA + DDRSS_PHY_953_DATA + DDRSS_PHY_954_DATA + DDRSS_PHY_955_DATA + DDRSS_PHY_956_DATA + DDRSS_PHY_957_DATA + DDRSS_PHY_958_DATA + DDRSS_PHY_959_DATA + DDRSS_PHY_960_DATA + DDRSS_PHY_961_DATA + DDRSS_PHY_962_DATA + DDRSS_PHY_963_DATA + DDRSS_PHY_964_DATA + DDRSS_PHY_965_DATA + DDRSS_PHY_966_DATA + DDRSS_PHY_967_DATA + DDRSS_PHY_968_DATA + DDRSS_PHY_969_DATA + DDRSS_PHY_970_DATA + DDRSS_PHY_971_DATA + DDRSS_PHY_972_DATA + DDRSS_PHY_973_DATA + DDRSS_PHY_974_DATA + DDRSS_PHY_975_DATA + DDRSS_PHY_976_DATA + DDRSS_PHY_977_DATA + DDRSS_PHY_978_DATA + DDRSS_PHY_979_DATA + DDRSS_PHY_980_DATA + DDRSS_PHY_981_DATA + DDRSS_PHY_982_DATA + DDRSS_PHY_983_DATA + DDRSS_PHY_984_DATA + DDRSS_PHY_985_DATA + DDRSS_PHY_986_DATA + DDRSS_PHY_987_DATA + DDRSS_PHY_988_DATA + DDRSS_PHY_989_DATA + DDRSS_PHY_990_DATA + DDRSS_PHY_991_DATA + DDRSS_PHY_992_DATA + DDRSS_PHY_993_DATA + DDRSS_PHY_994_DATA + DDRSS_PHY_995_DATA + DDRSS_PHY_996_DATA + DDRSS_PHY_997_DATA + DDRSS_PHY_998_DATA + DDRSS_PHY_999_DATA + DDRSS_PHY_1000_DATA + DDRSS_PHY_1001_DATA + DDRSS_PHY_1002_DATA + DDRSS_PHY_1003_DATA + DDRSS_PHY_1004_DATA + DDRSS_PHY_1005_DATA + DDRSS_PHY_1006_DATA + DDRSS_PHY_1007_DATA + DDRSS_PHY_1008_DATA + DDRSS_PHY_1009_DATA + DDRSS_PHY_1010_DATA + DDRSS_PHY_1011_DATA + DDRSS_PHY_1012_DATA + DDRSS_PHY_1013_DATA + DDRSS_PHY_1014_DATA + DDRSS_PHY_1015_DATA + DDRSS_PHY_1016_DATA + DDRSS_PHY_1017_DATA + DDRSS_PHY_1018_DATA + DDRSS_PHY_1019_DATA + DDRSS_PHY_1020_DATA + DDRSS_PHY_1021_DATA + DDRSS_PHY_1022_DATA + DDRSS_PHY_1023_DATA + DDRSS_PHY_1024_DATA + DDRSS_PHY_1025_DATA + DDRSS_PHY_1026_DATA + DDRSS_PHY_1027_DATA + DDRSS_PHY_1028_DATA + DDRSS_PHY_1029_DATA + DDRSS_PHY_1030_DATA + DDRSS_PHY_1031_DATA + DDRSS_PHY_1032_DATA + DDRSS_PHY_1033_DATA + DDRSS_PHY_1034_DATA + DDRSS_PHY_1035_DATA + DDRSS_PHY_1036_DATA + DDRSS_PHY_1037_DATA + DDRSS_PHY_1038_DATA + DDRSS_PHY_1039_DATA + DDRSS_PHY_1040_DATA + DDRSS_PHY_1041_DATA + DDRSS_PHY_1042_DATA + DDRSS_PHY_1043_DATA + DDRSS_PHY_1044_DATA + DDRSS_PHY_1045_DATA + DDRSS_PHY_1046_DATA + DDRSS_PHY_1047_DATA + DDRSS_PHY_1048_DATA + DDRSS_PHY_1049_DATA + DDRSS_PHY_1050_DATA + DDRSS_PHY_1051_DATA + DDRSS_PHY_1052_DATA + DDRSS_PHY_1053_DATA + DDRSS_PHY_1054_DATA + DDRSS_PHY_1055_DATA + DDRSS_PHY_1056_DATA + DDRSS_PHY_1057_DATA + DDRSS_PHY_1058_DATA + DDRSS_PHY_1059_DATA + DDRSS_PHY_1060_DATA + DDRSS_PHY_1061_DATA + DDRSS_PHY_1062_DATA + DDRSS_PHY_1063_DATA + DDRSS_PHY_1064_DATA + DDRSS_PHY_1065_DATA + DDRSS_PHY_1066_DATA + DDRSS_PHY_1067_DATA + DDRSS_PHY_1068_DATA + DDRSS_PHY_1069_DATA + DDRSS_PHY_1070_DATA + DDRSS_PHY_1071_DATA + DDRSS_PHY_1072_DATA + DDRSS_PHY_1073_DATA + DDRSS_PHY_1074_DATA + DDRSS_PHY_1075_DATA + DDRSS_PHY_1076_DATA + DDRSS_PHY_1077_DATA + DDRSS_PHY_1078_DATA + DDRSS_PHY_1079_DATA + DDRSS_PHY_1080_DATA + DDRSS_PHY_1081_DATA + DDRSS_PHY_1082_DATA + DDRSS_PHY_1083_DATA + DDRSS_PHY_1084_DATA + DDRSS_PHY_1085_DATA + DDRSS_PHY_1086_DATA + DDRSS_PHY_1087_DATA + DDRSS_PHY_1088_DATA + DDRSS_PHY_1089_DATA + DDRSS_PHY_1090_DATA + DDRSS_PHY_1091_DATA + DDRSS_PHY_1092_DATA + DDRSS_PHY_1093_DATA + DDRSS_PHY_1094_DATA + DDRSS_PHY_1095_DATA + DDRSS_PHY_1096_DATA + DDRSS_PHY_1097_DATA + DDRSS_PHY_1098_DATA + DDRSS_PHY_1099_DATA + DDRSS_PHY_1100_DATA + DDRSS_PHY_1101_DATA + DDRSS_PHY_1102_DATA + DDRSS_PHY_1103_DATA + DDRSS_PHY_1104_DATA + DDRSS_PHY_1105_DATA + DDRSS_PHY_1106_DATA + DDRSS_PHY_1107_DATA + DDRSS_PHY_1108_DATA + DDRSS_PHY_1109_DATA + DDRSS_PHY_1110_DATA + DDRSS_PHY_1111_DATA + DDRSS_PHY_1112_DATA + DDRSS_PHY_1113_DATA + DDRSS_PHY_1114_DATA + DDRSS_PHY_1115_DATA + DDRSS_PHY_1116_DATA + DDRSS_PHY_1117_DATA + DDRSS_PHY_1118_DATA + DDRSS_PHY_1119_DATA + DDRSS_PHY_1120_DATA + DDRSS_PHY_1121_DATA + DDRSS_PHY_1122_DATA + DDRSS_PHY_1123_DATA + DDRSS_PHY_1124_DATA + DDRSS_PHY_1125_DATA + DDRSS_PHY_1126_DATA + DDRSS_PHY_1127_DATA + DDRSS_PHY_1128_DATA + DDRSS_PHY_1129_DATA + DDRSS_PHY_1130_DATA + DDRSS_PHY_1131_DATA + DDRSS_PHY_1132_DATA + DDRSS_PHY_1133_DATA + DDRSS_PHY_1134_DATA + DDRSS_PHY_1135_DATA + DDRSS_PHY_1136_DATA + DDRSS_PHY_1137_DATA + DDRSS_PHY_1138_DATA + DDRSS_PHY_1139_DATA + DDRSS_PHY_1140_DATA + DDRSS_PHY_1141_DATA + DDRSS_PHY_1142_DATA + DDRSS_PHY_1143_DATA + DDRSS_PHY_1144_DATA + DDRSS_PHY_1145_DATA + DDRSS_PHY_1146_DATA + DDRSS_PHY_1147_DATA + DDRSS_PHY_1148_DATA + DDRSS_PHY_1149_DATA + DDRSS_PHY_1150_DATA + DDRSS_PHY_1151_DATA + DDRSS_PHY_1152_DATA + DDRSS_PHY_1153_DATA + DDRSS_PHY_1154_DATA + DDRSS_PHY_1155_DATA + DDRSS_PHY_1156_DATA + DDRSS_PHY_1157_DATA + DDRSS_PHY_1158_DATA + DDRSS_PHY_1159_DATA + DDRSS_PHY_1160_DATA + DDRSS_PHY_1161_DATA + DDRSS_PHY_1162_DATA + DDRSS_PHY_1163_DATA + DDRSS_PHY_1164_DATA + DDRSS_PHY_1165_DATA + DDRSS_PHY_1166_DATA + DDRSS_PHY_1167_DATA + DDRSS_PHY_1168_DATA + DDRSS_PHY_1169_DATA + DDRSS_PHY_1170_DATA + DDRSS_PHY_1171_DATA + DDRSS_PHY_1172_DATA + DDRSS_PHY_1173_DATA + DDRSS_PHY_1174_DATA + DDRSS_PHY_1175_DATA + DDRSS_PHY_1176_DATA + DDRSS_PHY_1177_DATA + DDRSS_PHY_1178_DATA + DDRSS_PHY_1179_DATA + DDRSS_PHY_1180_DATA + DDRSS_PHY_1181_DATA + DDRSS_PHY_1182_DATA + DDRSS_PHY_1183_DATA + DDRSS_PHY_1184_DATA + DDRSS_PHY_1185_DATA + DDRSS_PHY_1186_DATA + DDRSS_PHY_1187_DATA + DDRSS_PHY_1188_DATA + DDRSS_PHY_1189_DATA + DDRSS_PHY_1190_DATA + DDRSS_PHY_1191_DATA + DDRSS_PHY_1192_DATA + DDRSS_PHY_1193_DATA + DDRSS_PHY_1194_DATA + DDRSS_PHY_1195_DATA + DDRSS_PHY_1196_DATA + DDRSS_PHY_1197_DATA + DDRSS_PHY_1198_DATA + DDRSS_PHY_1199_DATA + DDRSS_PHY_1200_DATA + DDRSS_PHY_1201_DATA + DDRSS_PHY_1202_DATA + DDRSS_PHY_1203_DATA + DDRSS_PHY_1204_DATA + DDRSS_PHY_1205_DATA + DDRSS_PHY_1206_DATA + DDRSS_PHY_1207_DATA + DDRSS_PHY_1208_DATA + DDRSS_PHY_1209_DATA + DDRSS_PHY_1210_DATA + DDRSS_PHY_1211_DATA + DDRSS_PHY_1212_DATA + DDRSS_PHY_1213_DATA + DDRSS_PHY_1214_DATA + DDRSS_PHY_1215_DATA + DDRSS_PHY_1216_DATA + DDRSS_PHY_1217_DATA + DDRSS_PHY_1218_DATA + DDRSS_PHY_1219_DATA + DDRSS_PHY_1220_DATA + DDRSS_PHY_1221_DATA + DDRSS_PHY_1222_DATA + DDRSS_PHY_1223_DATA + DDRSS_PHY_1224_DATA + DDRSS_PHY_1225_DATA + DDRSS_PHY_1226_DATA + DDRSS_PHY_1227_DATA + DDRSS_PHY_1228_DATA + DDRSS_PHY_1229_DATA + DDRSS_PHY_1230_DATA + DDRSS_PHY_1231_DATA + DDRSS_PHY_1232_DATA + DDRSS_PHY_1233_DATA + DDRSS_PHY_1234_DATA + DDRSS_PHY_1235_DATA + DDRSS_PHY_1236_DATA + DDRSS_PHY_1237_DATA + DDRSS_PHY_1238_DATA + DDRSS_PHY_1239_DATA + DDRSS_PHY_1240_DATA + DDRSS_PHY_1241_DATA + DDRSS_PHY_1242_DATA + DDRSS_PHY_1243_DATA + DDRSS_PHY_1244_DATA + DDRSS_PHY_1245_DATA + DDRSS_PHY_1246_DATA + DDRSS_PHY_1247_DATA + DDRSS_PHY_1248_DATA + DDRSS_PHY_1249_DATA + DDRSS_PHY_1250_DATA + DDRSS_PHY_1251_DATA + DDRSS_PHY_1252_DATA + DDRSS_PHY_1253_DATA + DDRSS_PHY_1254_DATA + DDRSS_PHY_1255_DATA + DDRSS_PHY_1256_DATA + DDRSS_PHY_1257_DATA + DDRSS_PHY_1258_DATA + DDRSS_PHY_1259_DATA + DDRSS_PHY_1260_DATA + DDRSS_PHY_1261_DATA + DDRSS_PHY_1262_DATA + DDRSS_PHY_1263_DATA + DDRSS_PHY_1264_DATA + DDRSS_PHY_1265_DATA + DDRSS_PHY_1266_DATA + DDRSS_PHY_1267_DATA + DDRSS_PHY_1268_DATA + DDRSS_PHY_1269_DATA + DDRSS_PHY_1270_DATA + DDRSS_PHY_1271_DATA + DDRSS_PHY_1272_DATA + DDRSS_PHY_1273_DATA + DDRSS_PHY_1274_DATA + DDRSS_PHY_1275_DATA + DDRSS_PHY_1276_DATA + DDRSS_PHY_1277_DATA + DDRSS_PHY_1278_DATA + DDRSS_PHY_1279_DATA + DDRSS_PHY_1280_DATA + DDRSS_PHY_1281_DATA + DDRSS_PHY_1282_DATA + DDRSS_PHY_1283_DATA + DDRSS_PHY_1284_DATA + DDRSS_PHY_1285_DATA + DDRSS_PHY_1286_DATA + DDRSS_PHY_1287_DATA + DDRSS_PHY_1288_DATA + DDRSS_PHY_1289_DATA + DDRSS_PHY_1290_DATA + DDRSS_PHY_1291_DATA + DDRSS_PHY_1292_DATA + DDRSS_PHY_1293_DATA + DDRSS_PHY_1294_DATA + DDRSS_PHY_1295_DATA + DDRSS_PHY_1296_DATA + DDRSS_PHY_1297_DATA + DDRSS_PHY_1298_DATA + DDRSS_PHY_1299_DATA + DDRSS_PHY_1300_DATA + DDRSS_PHY_1301_DATA + DDRSS_PHY_1302_DATA + DDRSS_PHY_1303_DATA + DDRSS_PHY_1304_DATA + DDRSS_PHY_1305_DATA + DDRSS_PHY_1306_DATA + DDRSS_PHY_1307_DATA + DDRSS_PHY_1308_DATA + DDRSS_PHY_1309_DATA + DDRSS_PHY_1310_DATA + DDRSS_PHY_1311_DATA + DDRSS_PHY_1312_DATA + DDRSS_PHY_1313_DATA + DDRSS_PHY_1314_DATA + DDRSS_PHY_1315_DATA + DDRSS_PHY_1316_DATA + DDRSS_PHY_1317_DATA + DDRSS_PHY_1318_DATA + DDRSS_PHY_1319_DATA + DDRSS_PHY_1320_DATA + DDRSS_PHY_1321_DATA + DDRSS_PHY_1322_DATA + DDRSS_PHY_1323_DATA + DDRSS_PHY_1324_DATA + DDRSS_PHY_1325_DATA + DDRSS_PHY_1326_DATA + DDRSS_PHY_1327_DATA + DDRSS_PHY_1328_DATA + DDRSS_PHY_1329_DATA + DDRSS_PHY_1330_DATA + DDRSS_PHY_1331_DATA + DDRSS_PHY_1332_DATA + DDRSS_PHY_1333_DATA + DDRSS_PHY_1334_DATA + DDRSS_PHY_1335_DATA + DDRSS_PHY_1336_DATA + DDRSS_PHY_1337_DATA + DDRSS_PHY_1338_DATA + DDRSS_PHY_1339_DATA + DDRSS_PHY_1340_DATA + DDRSS_PHY_1341_DATA + DDRSS_PHY_1342_DATA + DDRSS_PHY_1343_DATA + DDRSS_PHY_1344_DATA + DDRSS_PHY_1345_DATA + DDRSS_PHY_1346_DATA + DDRSS_PHY_1347_DATA + DDRSS_PHY_1348_DATA + DDRSS_PHY_1349_DATA + DDRSS_PHY_1350_DATA + DDRSS_PHY_1351_DATA + DDRSS_PHY_1352_DATA + DDRSS_PHY_1353_DATA + DDRSS_PHY_1354_DATA + DDRSS_PHY_1355_DATA + DDRSS_PHY_1356_DATA + DDRSS_PHY_1357_DATA + DDRSS_PHY_1358_DATA + DDRSS_PHY_1359_DATA + DDRSS_PHY_1360_DATA + DDRSS_PHY_1361_DATA + DDRSS_PHY_1362_DATA + DDRSS_PHY_1363_DATA + DDRSS_PHY_1364_DATA + DDRSS_PHY_1365_DATA + DDRSS_PHY_1366_DATA + DDRSS_PHY_1367_DATA + DDRSS_PHY_1368_DATA + DDRSS_PHY_1369_DATA + DDRSS_PHY_1370_DATA + DDRSS_PHY_1371_DATA + DDRSS_PHY_1372_DATA + DDRSS_PHY_1373_DATA + DDRSS_PHY_1374_DATA + DDRSS_PHY_1375_DATA + DDRSS_PHY_1376_DATA + DDRSS_PHY_1377_DATA + DDRSS_PHY_1378_DATA + DDRSS_PHY_1379_DATA + DDRSS_PHY_1380_DATA + DDRSS_PHY_1381_DATA + DDRSS_PHY_1382_DATA + DDRSS_PHY_1383_DATA + DDRSS_PHY_1384_DATA + DDRSS_PHY_1385_DATA + DDRSS_PHY_1386_DATA + DDRSS_PHY_1387_DATA + DDRSS_PHY_1388_DATA + DDRSS_PHY_1389_DATA + DDRSS_PHY_1390_DATA + DDRSS_PHY_1391_DATA + DDRSS_PHY_1392_DATA + DDRSS_PHY_1393_DATA + DDRSS_PHY_1394_DATA + DDRSS_PHY_1395_DATA + DDRSS_PHY_1396_DATA + DDRSS_PHY_1397_DATA + DDRSS_PHY_1398_DATA + DDRSS_PHY_1399_DATA + DDRSS_PHY_1400_DATA + DDRSS_PHY_1401_DATA + DDRSS_PHY_1402_DATA + DDRSS_PHY_1403_DATA + DDRSS_PHY_1404_DATA + DDRSS_PHY_1405_DATA + DDRSS_PHY_1406_DATA + DDRSS_PHY_1407_DATA + DDRSS_PHY_1408_DATA + DDRSS_PHY_1409_DATA + DDRSS_PHY_1410_DATA + DDRSS_PHY_1411_DATA + DDRSS_PHY_1412_DATA + DDRSS_PHY_1413_DATA + DDRSS_PHY_1414_DATA + DDRSS_PHY_1415_DATA + DDRSS_PHY_1416_DATA + DDRSS_PHY_1417_DATA + DDRSS_PHY_1418_DATA + DDRSS_PHY_1419_DATA + DDRSS_PHY_1420_DATA + DDRSS_PHY_1421_DATA + DDRSS_PHY_1422_DATA + >; + }; +}; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 815e334b2c..54d7998d27 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -6,6 +6,8 @@ /dts-v1/; #include "k3-j721e-som-p0.dtsi" +#include "k3-j721e-ddr-evm-lp4-3733.dtsi" +#include "k3-j721e-ddr.dtsi" / { aliases { |