diff options
| author | Otavio Salvador <otavio@ossystems.com.br> | 2015-02-17 10:42:44 -0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-02-23 09:11:42 +0100 |
| commit | ee0c538951018759eff4038db75e61b1cd040307 (patch) | |
| tree | 612e1d55c9acee5252d0166b79fc99c32234ccd5 | |
| parent | f022d36e8a4517b2a9d25ff2d75bd2459d0c68b1 (diff) | |
mmc: fsl_esdhc: Add support to force VSELECT set
Some boards cannot do voltage negotiation but need to set the VSELECT
bit forcely to ensure it to work at 1.8V.
This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| -rw-r--r-- | doc/README.fsl-esdhc | 1 | ||||
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc index b70f271d1a..619c6b2d07 100644 --- a/doc/README.fsl-esdhc +++ b/doc/README.fsl-esdhc @@ -1,5 +1,6 @@ CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode. CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode. +CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V. Accessing ESDHC registers can be determined by ESDHC IP's endian mode or processor's endian mode. diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 6a3e147ed2..67ee179f86 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -523,6 +523,10 @@ static int esdhc_init(struct mmc *mmc) /* Set timout to the maximum value */ esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); +#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT + esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); +#endif + return 0; } |