diff options
| author | Marek Vasut <marek.vasut@gmail.com> | 2017-09-12 19:07:22 +0200 |
|---|---|---|
| committer | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2017-09-12 19:07:22 +0200 |
| commit | ef60323326b6736c1adf30362344af78d3f7d62c (patch) | |
| tree | de396d137b4d767f57a7ade507860d1fbaae82d7 | |
| parent | afb19d65d9a69635bed197f1d3be492e6bfe85d4 (diff) | |
ARM: rmobile: Move HSUSB configuration to board on ULCB
In order to use ehci-generic driver, move the configuration of HSUSB
block into the board file. This configuration should not have been in
the Gen3 EHCI USB driver in the first place, so move it to the board
file until there is a proper infrastructure and driver for the HSUSB
block.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| -rw-r--r-- | board/renesas/ulcb/ulcb.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index dc23228f4f..578b14be7b 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -53,6 +53,7 @@ void s_init(void) #define SD0_MSTP314 BIT(14) #define SD1_MSTP313 BIT(13) #define SD2_MSTP312 BIT(12) /* either MMC0 */ +#define HSUSB_MSTP704 BIT(4) /* HSUSB */ #define SD0CKCR 0xE6150074 #define SD1CKCR 0xE6150078 @@ -90,6 +91,13 @@ int board_early_init_f(void) /* -/W 32 Power resume control register 2 (3DG) */ #define SYSC_PWRONCR2 0xE618010C +/* HSUSB block registers */ +#define HSUSB_REG_LPSTS 0xE6590102 +#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) +#define HSUSB_REG_UGCTRL2 0xE6590184 +#define HSUSB_REG_UGCTRL2_USB0SEL 0x30 +#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10 + int board_init(void) { /* adress of boot parameters */ @@ -105,6 +113,14 @@ int board_init(void) /* USB1 pull-up */ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); + /* Configure the HSUSB block */ + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704); + /* Choice USB0SEL */ + clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, + HSUSB_REG_UGCTRL2_USB0SEL_EHCI); + /* low power status */ + setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); + #ifdef CONFIG_RENESAS_RAVB /* EtherAVB Enable */ /* GPSR2 */ |