diff options
| author | Sandeep Gopalpet <sandeep.kumar@freescale.com> | 2010-03-12 10:45:02 +0530 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-04-07 00:21:27 -0500 |
| commit | ff8473e90a018c2bb19a196176c1f2e9602d6354 (patch) | |
| tree | 52f1171686c26eacb52bbf3837f90abc3d86ea32 | |
| parent | 216082754f6da5359ea0db9b0cc03ad531ac6e45 (diff) | |
85xx: Set HID1[mbdd] on e500v2 rev5.0 or greater
The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize
the performance of mbar/eieio instructions.
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
| -rw-r--r-- | cpu/mpc85xx/release.S | 7 | ||||
| -rw-r--r-- | cpu/mpc85xx/start.S | 7 | ||||
| -rw-r--r-- | include/asm-ppc/processor.h | 1 |
3 files changed, 15 insertions, 0 deletions
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 69fce927a6..0b5b9da032 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -57,6 +57,13 @@ __secondary_start_page: #ifndef CONFIG_E500MC li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ + mfspr r0,PVR + andi. r0,r0,0xff + cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */ + blt 1f + /* Set MBDD bit also */ + ori r3, r3, HID1_MBDD@l +1: mtspr SPRN_HID1,r3 #endif diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 52ea9b3416..b3cb56a5b0 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -208,6 +208,13 @@ _start_e500: #ifndef CONFIG_E500MC li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ + mfspr r3,PVR + andi. r3,r3, 0xff + cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ + blt 1f + /* Set MBDD bit also */ + ori r0, r0, HID1_MBDD@l +1: mtspr HID1,r0 #endif diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 2b02774715..9ec319ae17 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -265,6 +265,7 @@ #define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ #define HID1_ASTME (1<<13) /* Address bus streaming mode */ #define HID1_ABE (1<<12) /* Address broadcast enable */ +#define HID1_MBDD (1<<6) /* optimized sync instruction */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #ifndef CONFIG_BOOKE #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ |