Merge branch 'next'

136 files changed, 3338 insertions, 2309 deletions

diff --git a/CREDITS b/CREDITS
index 2471029fc5..043ba6e13b 100644
--- a/CREDITS
+++ b/CREDITS
@@ -511,6 +511,11 @@ N: Martin Winistoerfer
 E: martinwinistoerfer@gmx.ch
 D: Port to MPC555/556 microcontrollers and support for cmi board
 
+N: David Wu
+E: support@arcturusnetworks.com
+D: Mercury Security EP2500
+W: http://www.arcturusnetworks.com
+
 N: Ming-Len Wu
 E: minglen_wu@techware.com.tw
 D: Motorola MX1ADS board support
diff --git a/MAINTAINERS b/MAINTAINERS
index 80057ce1eb..bb03f17784 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -80,7 +80,6 @@ Torsten Demke <torsten.demke@fci.com>
 
 Wolfgang Denk <wd@denx.de>
 
-	IceCube_5100	MGT5100
 	IceCube_5200	MPC5200
 
 	ARIA		MPC5121e
@@ -890,6 +889,10 @@ TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 	M5475EVB	mcf547x_8x
 	M5485EVB	mcf547x_8x
 
+Wolfgang Wegner <w.wegner@astro-kom.de>
+
+	astro_mcf5373l	MCF5373L
+
 #########################################################################
 # AVR32 Systems:							#
 #									#
diff --git a/MAKEALL b/MAKEALL
index 5c303f9a42..a88c31eff4 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -61,7 +61,6 @@ LIST_5xxx="		\
 	EVAL5200	\
 	fo300		\
 	galaxy5200	\
-	icecube_5100	\
 	icecube_5200	\
 	inka4x0		\
 	ipek01		\
@@ -76,7 +75,6 @@ LIST_5xxx="		\
 	pf5200		\
 	PM520		\
 	TB5200		\
-	Total5100	\
 	Total5200	\
 	Total5200_Rev2	\
 	TQM5200		\
@@ -840,6 +838,7 @@ LIST_microblaze="			\
 #########################################################################
 
 LIST_coldfire="			\
+	astro_mcf5373l		\
 	cobra5272		\
 	EB+MCF-EV123		\
 	EB+MCF-EV123_internal	\
diff --git a/Makefile b/Makefile
index e141cb2af3..45325504f9 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2009
+# (C) Copyright 2000-2010
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -548,8 +548,7 @@ icecube_5200_LOWBOOT_config		\
 icecube_5200_LOWBOOT08_config		\
 icecube_5200_DDR_config			\
 icecube_5200_DDR_LOWBOOT_config		\
-icecube_5200_DDR_LOWBOOT08_config	\
-icecube_5100_config:			unconfig
+icecube_5200_DDR_LOWBOOT08_config:	unconfig
 	@mkdir -p $(obj)include
 	@mkdir -p $(obj)board/icecube
 	@[ -z "$(findstring LOWBOOT_,$@)" ] || \
@@ -568,14 +567,6 @@ icecube_5100_config:			unconfig
 		{ echo "#define CONFIG_MPC5200_DDR"	>>$(obj)include/config.h ; \
 		  $(XECHO) "... DDR memory revision" ; \
 		}
-	@[ -z "$(findstring 5200,$@)" ] || \
-		{ echo "#define CONFIG_MPC5200"		>>$(obj)include/config.h ; \
-		  $(XECHO) "... with MPC5200 processor" ; \
-		}
-	@[ -z "$(findstring 5100,$@)" ] || \
-		{ echo "#define CONFIG_MGT5100"		>>$(obj)include/config.h ; \
-		  $(XECHO) "... with MGT5100 processor" ; \
-		}
 	@$(MKCONFIG) -a IceCube ppc mpc5xxx icecube
 
 jupiter_config:	unconfig
@@ -594,7 +585,6 @@ lite5200b_LOWBOOT_config:	unconfig
 	@mkdir -p $(obj)board/icecube
 	@ echo "#define CONFIG_MPC5200_DDR"	>>$(obj)include/config.h
 	@ $(XECHO) "... DDR memory revision"
-	@ echo "#define CONFIG_MPC5200"		>>$(obj)include/config.h
 	@ echo "#define CONFIG_LITE5200B"	>>$(obj)include/config.h
 	@[ -z "$(findstring _PM_,$@)" ] || \
 		{ echo "#define CONFIG_LITE5200B_PM"	>>$(obj)include/config.h ; \
@@ -604,7 +594,6 @@ lite5200b_LOWBOOT_config:	unconfig
 		{ echo "TEXT_BASE = 0xFF000000" >$(obj)board/icecube/config.tmp ; \
 		  $(XECHO) "... with LOWBOOT configuration" ; \
 		}
-	@ $(XECHO) "... with MPC5200B processor"
 	@$(MKCONFIG) -a IceCube  ppc mpc5xxx icecube
 
 mcc200_config	\
@@ -728,21 +717,12 @@ TOP5200_config:	unconfig
 	@ echo "#define CONFIG_$(@:_config=) 1"	>$(obj)include/config.h
 	@$(MKCONFIG) -n $@ -a TOP5200 ppc mpc5xxx top5200 emk
 
-Total5100_config		\
 Total5200_config		\
 Total5200_lowboot_config	\
 Total5200_Rev2_config		\
 Total5200_Rev2_lowboot_config:	unconfig
 	@mkdir -p $(obj)include
 	@mkdir -p $(obj)board/total5200
-	@[ -z "$(findstring 5100,$@)" ] || \
-		{ echo "#define CONFIG_MGT5100"		>>$(obj)include/config.h ; \
-		  $(XECHO) "... with MGT5100 processor" ; \
-		}
-	@[ -z "$(findstring 5200,$@)" ] || \
-		{ echo "#define CONFIG_MPC5200"		>>$(obj)include/config.h ; \
-		  $(XECHO) "... with MPC5200 processor" ; \
-		}
 	@[ -n "$(findstring Rev,$@)" ] || \
 		{ echo "#define CONFIG_TOTAL5200_REV 1"	>>$(obj)include/config.h ; \
 		  $(XECHO) "... revision 1 board" ; \
@@ -1993,6 +1973,10 @@ ZPC1900_config: unconfig
 ## Coldfire
 #########################################################################
 
+astro_mcf5373l_config \
+astro_mcf5373l_RAM_config :	unconfig
+	@$(MKCONFIG) -t $(@:_config=) astro_mcf5373l m68k mcf532x mcf5373l astro
+
 M5208EVBE_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5208evbe freescale
 
@@ -2061,6 +2045,9 @@ EB+MCF-EV123_internal_config :	unconfig
 	@echo "TEXT_BASE = 0xF0000000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk
 	@$(MKCONFIG) EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
 
+EP2500_config:			unconfig
+	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 ep2500 Mercury
+
 idmr_config :			unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 idmr
 
diff --git a/board/astro/mcf5373l/Makefile b/board/astro/mcf5373l/Makefile
new file mode 100644
index 0000000000..c7a1d05518
--- /dev/null
+++ b/board/astro/mcf5373l/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o fpga.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/astro/mcf5373l/astro.h b/board/astro/mcf5373l/astro.h
new file mode 100644
index 0000000000..b55a6f785c
--- /dev/null
+++ b/board/astro/mcf5373l/astro.h
@@ -0,0 +1,44 @@
+#ifndef __ASTRO_H__
+#define __ASTRO_H__
+
+/* in mcf5373l.c */
+int rs_serial_init(int port, int baud);
+void astro_put_char(char ch);
+int astro_is_char(void);
+int astro_get_char(void);
+
+/* in fpga.c */
+int astro5373l_altera_load(void);
+int astro5373l_xilinx_load(void);
+
+/* data structures used for communication (update.c) */
+typedef struct card_id {
+	char card_type;
+	char hardware_version;
+	char software_version;
+	char software_subversion;	/* " ","a".."z" */
+	char fpga_version_altera;
+	char fpga_version_xilinx;
+} card_id_t;
+
+typedef struct {
+	unsigned char mode;
+	unsigned char deviation;
+	unsigned short freq;
+} __attribute__ ((packed)) output_params_t;
+
+typedef struct {
+	unsigned short satfreq;
+	unsigned char satdatallg;
+	unsigned short symbolrate;
+	unsigned char viterbirate;
+	unsigned char symbolrate_l;
+	output_params_t output_params;
+	unsigned char reserve;
+	unsigned char card_error;
+	unsigned short dummy_ts_id;
+	unsigned char dummy_pat_ver;
+	unsigned char dummy_sdt_ver;
+} __attribute__ ((packed)) parameters_t;
+
+#endif /* __ASTRO_H__ */
diff --git a/board/astro/mcf5373l/config.mk b/board/astro/mcf5373l/config.mk
new file mode 100644
index 0000000000..6316a3029a
--- /dev/null
+++ b/board/astro/mcf5373l/config.mk
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = $(CONFIG_TEXT_BASE)
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c
new file mode 100644
index 0000000000..467461b8e8
--- /dev/null
+++ b/board/astro/mcf5373l/fpga.c
@@ -0,0 +1,425 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH,
+ * w.wegner@astro-kom.de
+ *
+ * based on the files by
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de
+ * and
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */
+
+#include <common.h>
+#include <watchdog.h>
+#include <altera.h>
+#include <ACEX1K.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/immap_5329.h>
+#include <asm/io.h>
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int altera_pre_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	unsigned char tmp_char;
+	unsigned short tmp_short;
+
+	/* first, set the required pins to GPIO function */
+	/* PAR_T0IN -> GPIO */
+	tmp_char = readb(&gpiop->par_timer);
+	tmp_char &= 0xfc;
+	writeb(tmp_char, &gpiop->par_timer);
+	/* all QSPI pins -> GPIO */
+	writew(0x0000, &gpiop->par_qspi);
+	/* U0RTS, U0CTS -> GPIO */
+	tmp_short = __raw_readw(&gpiop->par_uart);
+	tmp_short &= 0xfff3;
+	__raw_writew(tmp_short, &gpiop->par_uart);
+	/* all PWM pins -> GPIO */
+	writeb(0x00, &gpiop->par_pwm);
+	/* next, set data direction registers */
+	writeb(0x01, &gpiop->pddr_timer);
+	writeb(0x25, &gpiop->pddr_qspi);
+	writeb(0x0c, &gpiop->pddr_uart);
+	writeb(0x04, &gpiop->pddr_pwm);
+
+	/* ensure other SPI peripherals are deselected */
+	writeb(0x08, &gpiop->ppd_uart);
+	writeb(0x38, &gpiop->ppd_qspi);
+
+	/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
+	writeb(0xFB, &gpiop->pclrr_uart);
+	/* enable Altera configuration by clearing QSPI_CS2 and DT0IN */
+	writeb(0xFE, &gpiop->pclrr_timer);
+	writeb(0xDF, &gpiop->pclrr_qspi);
+	return FPGA_SUCCESS;
+}
+
+/* Set the state of CONFIG Pin */
+int altera_config_fn(int assert_config, int flush, int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (assert_config)
+		writeb(0x04, &gpiop->ppd_uart);
+	else
+		writeb(0xFB, &gpiop->pclrr_uart);
+	return FPGA_SUCCESS;
+}
+
+/* Returns the state of STATUS Pin */
+int altera_status_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (readb(&gpiop->ppd_pwm) & 0x08)
+		return FPGA_FAIL;
+	return FPGA_SUCCESS;
+}
+
+/* Returns the state of CONF_DONE Pin */
+int altera_done_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (readb(&gpiop->ppd_pwm) & 0x20)
+		return FPGA_FAIL;
+	return FPGA_SUCCESS;
+}
+
+/*
+ * writes the complete buffer to the FPGA
+ * writing the complete buffer in one function is much faster,
+ * then calling it for every bit
+ */
+int altera_write_fn(void *buf, size_t len, int flush, int cookie)
+{
+	size_t bytecount = 0;
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	unsigned char *data = (unsigned char *)buf;
+	unsigned char val = 0;
+	int i;
+	int len_40 = len / 40;
+
+	while (bytecount < len) {
+		val = data[bytecount++];
+		i = 8;
+		do {
+			writeb(0xFB, &gpiop->pclrr_qspi);
+			if (val & 0x01)
+				writeb(0x01, &gpiop->ppd_qspi);
+			else
+				writeb(0xFE, &gpiop->pclrr_qspi);
+			writeb(0x04, &gpiop->ppd_qspi);
+			val >>= 1;
+			i--;
+		} while (i > 0);
+
+		if (bytecount % len_40 == 0) {
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+			WATCHDOG_RESET();
+#endif
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+			putc('.');	/* let them know we are alive */
+#endif
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+			if (ctrlc())
+				return FPGA_FAIL;
+#endif
+		}
+	}
+	return FPGA_SUCCESS;
+}
+
+/* called, when programming is aborted */
+int altera_abort_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	writeb(0x20, &gpiop->ppd_qspi);
+	writeb(0x08, &gpiop->ppd_uart);
+	return FPGA_SUCCESS;
+}
+
+/* called, when programming was succesful */
+int altera_post_fn(int cookie)
+{
+	return altera_abort_fn(cookie);
+}
+
+/*
+ * Note that these are pointers to code that is in Flash. They will be
+ * relocated at runtime.
+ * FIXME: relocation not yet working for coldfire, see below!
+ */
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+	altera_pre_fn,
+	altera_config_fn,
+	altera_status_fn,
+	altera_done_fn,
+	altera_write_fn,
+	altera_abort_fn,
+	altera_post_fn
+};
+
+Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = {
+	{Altera_CYC2,
+	 passive_serial,
+	 85903,
+	 (void *)&altera_fns,
+	 NULL,
+	 0}
+};
+
+/* Initialize the fpga.  Return 1 on success, 0 on failure. */
+int astro5373l_altera_load(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		/*
+		 * I did not yet manage to get relocation work properly,
+		 * so set stuff here instead of static initialisation:
+		 */
+		altera_fns.pre = altera_pre_fn;
+		altera_fns.config = altera_config_fn;
+		altera_fns.status = altera_status_fn;
+		altera_fns.done = altera_done_fn;
+		altera_fns.write = altera_write_fn;
+		altera_fns.abort = altera_abort_fn;
+		altera_fns.post = altera_post_fn;
+		altera_fpga[i].iface_fns = (void *)&altera_fns;
+		fpga_add(fpga_altera, &altera_fpga[i]);
+	}
+	return 1;
+}
+
+/* Set the FPGA's PROG_B line to the specified level */
+int xilinx_pgm_fn(int assert, int flush, int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (assert)
+		writeb(0xFB, &gpiop->pclrr_uart);
+	else
+		writeb(0x04, &gpiop->ppd_uart);
+	return assert;
+}
+
+/*
+ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
+ * asserted (low).
+ */
+int xilinx_init_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	return (readb(&gpiop->ppd_pwm) & 0x08) == 0;
+}
+
+/* Test the state of the active-high FPGA DONE pin */
+int xilinx_done_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	return (readb(&gpiop->ppd_pwm) & 0x20) >> 5;
+}
+
+/* Abort an FPGA operation */
+int xilinx_abort_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	/* ensure all SPI peripherals and FPGAs are deselected */
+	writeb(0x08, &gpiop->ppd_uart);
+	writeb(0x01, &gpiop->ppd_timer);
+	writeb(0x38, &gpiop->ppd_qspi);
+	return FPGA_FAIL;
+}
+
+/*
+ * FPGA pre-configuration function. Just make sure that
+ * FPGA reset is asserted to keep the FPGA from starting up after
+ * configuration.
+ */
+int xilinx_pre_config_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	unsigned char tmp_char;
+	unsigned short tmp_short;
+
+	/* first, set the required pins to GPIO function */
+	/* PAR_T0IN -> GPIO */
+	tmp_char = readb(&gpiop->par_timer);
+	tmp_char &= 0xfc;
+	writeb(tmp_char, &gpiop->par_timer);
+	/* all QSPI pins -> GPIO */
+	writew(0x0000, &gpiop->par_qspi);
+	/* U0RTS, U0CTS -> GPIO */
+	tmp_short = __raw_readw(&gpiop->par_uart);
+	tmp_short &= 0xfff3;
+	__raw_writew(tmp_short, &gpiop->par_uart);
+	/* all PWM pins -> GPIO */
+	writeb(0x00, &gpiop->par_pwm);
+	/* next, set data direction registers */
+	writeb(0x01, &gpiop->pddr_timer);
+	writeb(0x25, &gpiop->pddr_qspi);
+	writeb(0x0c, &gpiop->pddr_uart);
+	writeb(0x04, &gpiop->pddr_pwm);
+
+	/* ensure other SPI peripherals are deselected */
+	writeb(0x08, &gpiop->ppd_uart);
+	writeb(0x38, &gpiop->ppd_qspi);
+	writeb(0x01, &gpiop->ppd_timer);
+
+	/* CONFIG = 0, STATUS = 0 -> FPGA in reset state */
+	writeb(0xFB, &gpiop->pclrr_uart);
+	/* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */
+	writeb(0xF7, &gpiop->pclrr_uart);
+	writeb(0xDF, &gpiop->pclrr_qspi);
+	return 0;
+}
+
+/*
+ * FPGA post configuration function. Should perform a test if FPGA is running.
+ */
+int xilinx_post_config_fn(int cookie)
+{
+	int rc = 0;
+
+	/*
+	 * no test yet
+	 */
+	return rc;
+}
+
+int xilinx_clk_fn(int assert_clk, int flush, int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (assert_clk)
+		writeb(0x04, &gpiop->ppd_qspi);
+	else
+		writeb(0xFB, &gpiop->pclrr_qspi);
+	return assert_clk;
+}
+
+int xilinx_wr_fn(int assert_write, int flush, int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (assert_write)
+		writeb(0x01, &gpiop->ppd_qspi);
+	else
+		writeb(0xFE, &gpiop->pclrr_qspi);
+	return assert_write;
+}
+
+int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie)
+{
+	size_t bytecount = 0;
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	unsigned char *data = (unsigned char *)buf;
+	unsigned char val = 0;
+	int i;
+	int len_40 = len / 40;
+
+	for (bytecount = 0; bytecount < len; bytecount++) {
+		val = *(data++);
+		for (i = 8; i > 0; i--) {
+			writeb(0xFB, &gpiop->pclrr_qspi);
+			if (val & 0x80)
+				writeb(0x01, &gpiop->ppd_qspi);
+			else
+				writeb(0xFE, &gpiop->pclrr_qspi);
+			writeb(0x04, &gpiop->ppd_qspi);
+			val <<= 1;
+		}
+		if (bytecount % len_40 == 0) {
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+			WATCHDOG_RESET();
+#endif
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+			putc('.');	/* let them know we are alive */
+#endif
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+			if (ctrlc())
+				return FPGA_FAIL;
+#endif
+		}
+	}
+	return FPGA_SUCCESS;
+}
+
+/*
+ * Note that these are pointers to code that is in Flash.  They will be
+ * relocated at runtime.
+ * FIXME: relocation not yet working for coldfire, see below!
+ */
+Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = {
+	xilinx_pre_config_fn,
+	xilinx_pgm_fn,
+	xilinx_clk_fn,
+	xilinx_init_fn,
+	xilinx_done_fn,
+	xilinx_wr_fn,
+	0,
+	xilinx_fastwr_fn
+};
+
+Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
+	{Xilinx_Spartan3,
+	 slave_serial,
+	 XILINX_XC3S4000_SIZE,
+	 (void *)&xilinx_fns,
+	 0}
+};
+
+/* Initialize the fpga.  Return 1 on success, 0 on failure. */
+int astro5373l_xilinx_load(void)
+{
+	int i;
+
+	fpga_init();
+
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		/*
+		 * I did not yet manage to get relocation work properly,
+		 * so set stuff here instead of static initialisation:
+		 */
+		xilinx_fns.pre = xilinx_pre_config_fn;
+		xilinx_fns.pgm = xilinx_pgm_fn;
+		xilinx_fns.clk = xilinx_clk_fn;
+		xilinx_fns.init = xilinx_init_fn;
+		xilinx_fns.done = xilinx_done_fn;
+		xilinx_fns.wr = xilinx_wr_fn;
+		xilinx_fns.bwr = xilinx_fastwr_fn;
+		xilinx_fpga[i].iface_fns = (void *)&xilinx_fns;
+		fpga_add(fpga_xilinx, &xilinx_fpga[i]);
+	}
+	return 1;
+}
diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c
new file mode 100644
index 0000000000..3c09a21eed
--- /dev/null
+++ b/board/astro/mcf5373l/mcf5373l.c
@@ -0,0 +1,211 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/m5329.h>
+#include <asm/immap_5329.h>
+#include <asm/io.h>
+
+/* needed for astro bus: */
+#include <asm/uart.h>
+#include "astro.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+extern void uart_port_conf(void);
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("ASTRO MCF5373L (Urmel) Board\n");
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+	sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
+
+	/*
+	 * GPIO configuration for bus should be set correctly from reset,
+	 * so we do not care! First, set up address space: at this point,
+	 * we should be running from internal SRAM;
+	 * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM,
+	 * and do not care where it is
+	 */
+	__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
+			&sdp->cs0);
+	__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
+			&sdp->cs1);
+	/*
+	 * I am not sure from the data sheet, but it seems burst length
+	 * has to be 8 for the 16 bit data bus we use;
+	 * so these values are for BL = 8
+	 */
+	__raw_writel(0x33211530, &sdp->cfg1);
+	__raw_writel(0x56570000, &sdp->cfg2);
+	/* send PrechargeALL, REF and IREF remain cleared! */
+	__raw_writel(0xE1462C02, &sdp->ctrl);
+	udelay(1);
+	/* refresh SDRAM twice */
+	__raw_writel(0xE1462C04, &sdp->ctrl);
+	udelay(1);
+	__raw_writel(0xE1462C04, &sdp->ctrl);
+	/* init MR  */
+	__raw_writel(0x008D0000, &sdp->mode);
+	/* initialize EMR */
+	__raw_writel(0x80010000, &sdp->mode);
+	/* wait until DLL is locked */
+	udelay(1);
+	/*
+	 * enable automatic refresh, lock mode register,
+	 * clear iref and ipall
+	 */
+	__raw_writel(0x71462C00, &sdp->ctrl);
+	/* Dummy write to start SDRAM */
+	writel(0, CONFIG_SYS_SDRAM_BASE);
+#endif
+
+	/*
+	 * for get_ram_size() to work, both CS areas have to be
+	 * configured, i.e. CS1 has to be explicitely disabled, else
+	 * probing for memory will cause the SDRAM bus to hang!
+	 * (Do not rely on the SDCS register(s) being set to 0x00000000
+	 * during reset as stated in the data sheet.)
+	 */
+	return get_ram_size((unsigned long *)CONFIG_SYS_SDRAM_BASE,
+				0x80000000 - CONFIG_SYS_SDRAM_BASE);
+}
+
+#define UART_BASE MMAP_UART0
+int rs_serial_init(int port, int baud)
+{
+	uart_t *uart;
+	u32 counter;
+
+	switch (port) {
+	case 0:
+		uart = (uart_t *)(MMAP_UART0);
+		break;
+	case 1:
+		uart = (uart_t *)(MMAP_UART1);
+		break;
+	case 2:
+		uart = (uart_t *)(MMAP_UART2);
+		break;
+	default:
+		uart = (uart_t *)(MMAP_UART0);
+	}
+
+	uart_port_conf();
+
+	/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
+	writeb(UART_UCR_RESET_RX, &uart->ucr);
+	writeb(UART_UCR_RESET_TX, &uart->ucr);
+	writeb(UART_UCR_RESET_ERROR, &uart->ucr);
+	writeb(UART_UCR_RESET_MR, &uart->ucr);
+	__asm__ ("nop");
+
+	writeb(0, &uart->uimr);
+
+	/* write to CSR: RX/TX baud rate from timers */
+	writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
+
+	writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
+	writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
+
+	/* Setting up BaudRate */
+	counter = (u32) (gd->bus_clk / (baud));
+	counter >>= 5;
+
+	/* write to CTUR: divide counter upper byte */
+	writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1);
+	/* write to CTLR: divide counter lower byte */
+	writeb((u8) (counter & 0x00ff), &uart->ubg2);
+
+	writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
+
+	return 0;
+}
+
+void astro_put_char(char ch)
+{
+	uart_t *uart;
+	unsigned long timer;
+
+	uart = (uart_t *)(MMAP_UART0);
+	/*
+	 * Wait for last character to go. Timeout of 6ms should
+	 * be enough for our lowest baud rate of 2400.
+	 */
+	timer = get_timer(0);
+	while (get_timer(timer) < 6) {
+		if (readb(&uart->usr) & UART_USR_TXRDY)
+			break;
+	}
+	writeb(ch, &uart->utb);
+
+	return;
+}
+
+int astro_is_char(void)
+{
+	uart_t *uart;
+
+	uart = (uart_t *)(MMAP_UART0);
+	return readb(&uart->usr) & UART_USR_RXRDY;
+}
+
+int astro_get_char(void)
+{
+	uart_t *uart;
+
+	uart = (uart_t *)(MMAP_UART0);
+	while (!(readb(&uart->usr) & UART_USR_RXRDY)) ;
+	return readb(&uart->urb);
+}
+
+int misc_init_r(void)
+{
+	int retval = 0;
+
+	puts("Configure Xilinx FPGA...");
+	retval = astro5373l_xilinx_load();
+	if (!retval) {
+		puts("failed!\n");
+		return retval;
+	}
+	puts("done\n");
+
+	puts("Configure Altera FPGA...");
+	retval = astro5373l_altera_load();
+	if (!retval) {
+		puts("failed!\n");
+		return retval;
+	}
+	puts("done\n");
+
+	return retval;
+}
diff --git a/board/astro/mcf5373l/u-boot.lds b/board/astro/mcf5373l/u-boot.lds
new file mode 100644
index 0000000000..a9a4e0a233
--- /dev/null
+++ b/board/astro/mcf5373l/u-boot.lds
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf532x/start.o		(.text)
+    lib_m68k/traps.o		(.text)
+    lib_m68k/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+/*    *(.fixup)*/
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c
index 6fb0096bed..3117b5fbff 100644
--- a/board/bc3450/bc3450.c
+++ b/board/bc3450/bc3450.c
@@ -104,7 +104,6 @@ static void sdram_start (int hi_addr)
  *	      is something else than 0x00000000.
  */
 
-#if defined(CONFIG_MPC5200)
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
@@ -204,57 +203,6 @@ phys_size_t initdram (int board_type)
 	return dramsize;
 }
 
-#elif defined(CONFIG_MGT5100)
-
-phys_size_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup and enable SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
-	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;	/* 2G		*/
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22);	/* Enable SDRAM */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
-	/* address select register */
-	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
-	__asm__ volatile ("sync");
-
-	/* find RAM size */
-	sdram_start(0);
-	test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* set SDRAM end address according to size */
-	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* Retrieve amount of SDRAM available */
-	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	return dramsize;
-}
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
-
 int checkboard (void)
 {
 #if defined (CONFIG_TQM5200)
@@ -276,10 +224,6 @@ void flash_preinit(void)
 	 * Note that CS_BOOT cannot be cleared when
 	 * executing in flash.
 	 */
-#if defined(CONFIG_MGT5100)
-	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25);	/* disable CS_BOOT */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16);	/* enable CS0	   */
-#endif
 	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1;		/* clear RO	   */
 }
 
diff --git a/board/bc3450/mt48lc16m16a2-75.h b/board/bc3450/mt48lc16m16a2-75.h
index 3f1e1691bb..48b43213dc 100644
--- a/board/bc3450/mt48lc16m16a2-75.h
+++ b/board/bc3450/mt48lc16m16a2-75.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 /* #define SDRAM_MODE	0x008D0000 */ /* CAS latency 2 */
@@ -33,15 +32,3 @@
 /*#define SDRAM_CONFIG1	0xD7322800 */ /* SDRAM controller bug workaround */
 #define SDRAM_CONFIG2	0x8AD70000
 /*#define SDRAM_CONFIG2	0xDDD70000 */ /* SDRAM controller bug workaround */
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c
index dce07bf785..6ddc858ea4 100644
--- a/board/canmb/canmb.c
+++ b/board/canmb/canmb.c
@@ -81,7 +81,6 @@ static void sdram_start (int hi_addr)
  *            is something else than 0x00000000.
  */
 
-#if defined(CONFIG_MPC5200)
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
@@ -183,57 +182,6 @@ phys_size_t initdram (int board_type)
 	return dramsize + dramsize2;
 }
 
-#elif defined(CONFIG_MGT5100)
-
-phys_size_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup and enable SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
-	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
-	/* address select register */
-	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
-	__asm__ volatile ("sync");
-
-	/* find RAM size */
-	sdram_start(0);
-	test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* set SDRAM end address according to size */
-	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* Retrieve amount of SDRAM available */
-	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	return dramsize;
-}
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
-
 int checkboard (void)
 {
 	puts ("Board: CANMB\n");
diff --git a/board/canmb/mt48lc16m32s2-75.h b/board/canmb/mt48lc16m32s2-75.h
index ffdf0396a5..15477259ca 100644
--- a/board/canmb/mt48lc16m32s2-75.h
+++ b/board/canmb/mt48lc16m32s2-75.h
@@ -23,21 +23,8 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 #define SDRAM_CONTROL	0x504F0000
 #define SDRAM_CONFIG1	0xD2322800
 #define SDRAM_CONFIG2	0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/davinci/da830evm/da830evm.c b/board/davinci/da830evm/da830evm.c
index ed668afccc..6385443666 100644
--- a/board/davinci/da830evm/da830evm.c
+++ b/board/davinci/da830evm/da830evm.c
@@ -150,7 +150,7 @@ int board_init(void)
 		DAVINCI_ABCR_RHOLD(0) |
 		DAVINCI_ABCR_TA(2) |
 		DAVINCI_ABCR_ASIZE_8BIT),
-	       &davinci_emif_regs->AB2CR);
+	       &davinci_emif_regs->ab2cr);
 #endif
 
 	/* arch number of the board */
diff --git a/board/esd/cpci5200/mt46v16m16-75.h b/board/esd/cpci5200/mt46v16m16-75.h
index 22d0a55444..cf63806a58 100644
--- a/board/esd/cpci5200/mt46v16m16-75.h
+++ b/board/esd/cpci5200/mt46v16m16-75.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	1	/* is DDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x018D0000
 #define SDRAM_EMODE	0x40090000
@@ -31,7 +30,3 @@
 #define SDRAM_CONFIG1	0x73722930
 #define SDRAM_CONFIG2	0x47770000
 #define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/esd/mecp5200/mt46v16m16-75.h b/board/esd/mecp5200/mt46v16m16-75.h
index 22d0a55444..cf63806a58 100644
--- a/board/esd/mecp5200/mt46v16m16-75.h
+++ b/board/esd/mecp5200/mt46v16m16-75.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	1	/* is DDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x018D0000
 #define SDRAM_EMODE	0x40090000
@@ -31,7 +30,3 @@
 #define SDRAM_CONFIG1	0x73722930
 #define SDRAM_CONFIG2	0x47770000
 #define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/esd/pf5200/mt46v16m16-75.h b/board/esd/pf5200/mt46v16m16-75.h
index 22d0a55444..cf63806a58 100644
--- a/board/esd/pf5200/mt46v16m16-75.h
+++ b/board/esd/pf5200/mt46v16m16-75.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	1	/* is DDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x018D0000
 #define SDRAM_EMODE	0x40090000
@@ -31,7 +30,3 @@
 #define SDRAM_CONFIG1	0x73722930
 #define SDRAM_CONFIG2	0x47770000
 #define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/freescale/m5271evb/m5271evb.c b/board/freescale/m5271evb/m5271evb.c
index 5505cc42c6..446f102e58 100644
--- a/board/freescale/m5271evb/m5271evb.c
+++ b/board/freescale/m5271evb/m5271evb.c
@@ -47,6 +47,7 @@ phys_size_t initdram (int board_type) {
 			MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
 			MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
 			MCF_GPIO_SDRAM_SDCS_11);
+	asm(" nop");
 
 	/*
 	 * Check to see if the SDRAM has already been initialized
@@ -55,8 +56,9 @@ phys_size_t initdram (int board_type) {
 	if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
 		/* Initialize DRAM Control Register: DCR */
 		mbar_writeShort(MCF_SDRAMC_DCR,
-				MCF_SDRAMC_DCR_RTIM(0x01)
-				| MCF_SDRAMC_DCR_RC(0x30));
+				MCF_SDRAMC_DCR_RTIM(2)
+				| MCF_SDRAMC_DCR_RC(0x2E));
+		asm(" nop");
 
 		/*
 		 * Initialize DACR0
@@ -70,15 +72,18 @@ phys_size_t initdram (int board_type) {
 				| MCF_SDRAMC_DACRn_CASL(1)
 				| MCF_SDRAMC_DACRn_CBM(3)
 				| MCF_SDRAMC_DACRn_PS(0));
+		asm(" nop");
 
 		/* Initialize DMR0 */
 		mbar_writeLong(MCF_SDRAMC_DMR0,
 				MCF_SDRAMC_DMRn_BAM_16M
 				| MCF_SDRAMC_DMRn_V);
+		asm(" nop");
 
 		/* Set IP bit in DACR */
 		mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
 				| MCF_SDRAMC_DACRn_IP);
+		asm(" nop");
 
 		/* Wait at least 20ns to allow banks to precharge */
 		for (i = 0; i < 5; i++)
@@ -86,6 +91,7 @@ phys_size_t initdram (int board_type) {
 
 		/* Write to this block to initiate precharge */
 		*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
+		asm(" nop");
 
 		/* Set RE bit in DACR */
 		mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
@@ -98,6 +104,7 @@ phys_size_t initdram (int board_type) {
 		/* Finish the configuration by issuing the MRS */
 		mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
 				| MCF_SDRAMC_DACRn_MRS);
+		asm(" nop");
 
 		/*
 		 * Write to the SDRAM Mode Register A0-A11 = 0x400
@@ -109,6 +116,7 @@ phys_size_t initdram (int board_type) {
 		 * Burst Length = 1
 		 */
 		*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
+		asm(" nop");
 	}
 
 	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c
index 293b5b0e41..2a84514a3d 100644
--- a/board/freescale/m54455evb/m54455evb.c
+++ b/board/freescale/m54455evb/m54455evb.c
@@ -107,7 +107,7 @@ int ide_preinit(void)
 {
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-	gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_MASK) | 0x10;
+	gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
 	gpio->par_feci2c |=
 	    (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
 					   GPIO_PAR_FECI2C_MDIO1_ATA_DIOW);
@@ -185,7 +185,7 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
 	info->flash_id          = 0x01000000;
 	info->portwidth         = 1;
 	info->chipwidth         = 1;
-	info->buffer_size       = 32;
+	info->buffer_size       = 1;
 	info->erase_blk_tout    = 16384;
 	info->write_tout        = 2;
 	info->buffer_write_tout = 5;
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index 75244610cf..47b2195557 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -134,7 +134,6 @@ static void sdram_start (int hi_addr)
  *            is something else than 0x00000000.
  */
 
-#if defined(CONFIG_MPC5200)
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
@@ -258,65 +257,12 @@ phys_size_t initdram (int board_type)
 	return dramsize + dramsize2;
 }
 
-#elif defined(CONFIG_MGT5100)
-
-phys_size_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup and enable SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
-	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
-	/* address select register */
-	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
-	__asm__ volatile ("sync");
-
-	/* find RAM size */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* set SDRAM end address according to size */
-	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* Retrieve amount of SDRAM available */
-	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	return dramsize;
-}
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
-
 int checkboard (void)
 {
 #if defined (CONFIG_LITE5200B)
 	puts ("Board: Freescale Lite5200B\n");
-#elif defined(CONFIG_MPC5200)
+#else
 	puts ("Board: Motorola MPC5200 (IceCube)\n");
-#elif defined(CONFIG_MGT5100)
-	puts ("Board: Motorola MGT5100 (IceCube)\n");
 #endif
 	return 0;
 }
@@ -329,10 +275,6 @@ void flash_preinit(void)
 	 * Note that CS_BOOT cannot be cleared when
 	 * executing in flash.
 	 */
-#if defined(CONFIG_MGT5100)
-	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-#endif
 	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 }
 
diff --git a/board/icecube/mt46v16m16-75.h b/board/icecube/mt46v16m16-75.h
index 4c0f9a7406..eb857404f1 100644
--- a/board/icecube/mt46v16m16-75.h
+++ b/board/icecube/mt46v16m16-75.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	1		/* is DDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x018D0000
 #define SDRAM_EMODE	0x40090000
@@ -31,7 +30,3 @@
 #define SDRAM_CONFIG1	0x73722930
 #define SDRAM_CONFIG2	0x47770000
 #define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/icecube/mt46v32m16.h b/board/icecube/mt46v32m16.h
index de2b48bc60..519bf6d0f0 100644
--- a/board/icecube/mt46v32m16.h
+++ b/board/icecube/mt46v32m16.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	1		/* is DDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x018D0000
 #define SDRAM_EMODE	0x40090000
@@ -31,7 +30,3 @@
 #define SDRAM_CONFIG1	0x73722930
 #define SDRAM_CONFIG2	0x47770000
 #define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/icecube/mt48lc16m16a2-75.h b/board/icecube/mt48lc16m16a2-75.h
index ffdf0396a5..15477259ca 100644
--- a/board/icecube/mt48lc16m16a2-75.h
+++ b/board/icecube/mt48lc16m16a2-75.h
@@ -23,21 +23,8 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 #define SDRAM_CONTROL	0x504F0000
 #define SDRAM_CONFIG1	0xD2322800
 #define SDRAM_CONFIG2	0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c
index 6e752c6554..967aabdcfa 100644
--- a/board/jupiter/jupiter.c
+++ b/board/jupiter/jupiter.c
@@ -227,10 +227,6 @@ void flash_preinit(void)
 	 * Note that CS_BOOT cannot be cleared when
 	 * executing in flash.
 	 */
-#if defined(CONFIG_MGT5100)
-	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-#endif
 	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 }
 
@@ -248,10 +244,8 @@ void flash_afterinit(ulong size)
 		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 			STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
 	}
-#if defined(CONFIG_MPC5200)
 	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
 	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-#endif
 }
 
 int update_flash_size (int flash_size)
diff --git a/board/mcc200/mt46v16m16-75.h b/board/mcc200/mt46v16m16-75.h
index f650faaa10..423febe20a 100644
--- a/board/mcc200/mt46v16m16-75.h
+++ b/board/mcc200/mt46v16m16-75.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	1		/* is DDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x018D0000
 #define SDRAM_EMODE	0x40090000
@@ -31,7 +30,3 @@
 #define SDRAM_CONFIG1	0x73722930
 #define SDRAM_CONFIG2	0x47770000
 #define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/mcc200/mt48lc16m16a2-75.h b/board/mcc200/mt48lc16m16a2-75.h
index ffdf0396a5..15477259ca 100644
--- a/board/mcc200/mt48lc16m16a2-75.h
+++ b/board/mcc200/mt48lc16m16a2-75.h
@@ -23,21 +23,8 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 #define SDRAM_CONTROL	0x504F0000
 #define SDRAM_CONFIG1	0xD2322800
 #define SDRAM_CONFIG2	0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/mcc200/mt48lc16m32s2-75.h b/board/mcc200/mt48lc16m32s2-75.h
index ffdf0396a5..15477259ca 100644
--- a/board/mcc200/mt48lc16m32s2-75.h
+++ b/board/mcc200/mt48lc16m32s2-75.h
@@ -23,21 +23,8 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 #define SDRAM_CONTROL	0x504F0000
 #define SDRAM_CONFIG1	0xD2322800
 #define SDRAM_CONFIG2	0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/munices/mt48lc16m16a2-75.h b/board/munices/mt48lc16m16a2-75.h
index ffdf0396a5..15477259ca 100644
--- a/board/munices/mt48lc16m16a2-75.h
+++ b/board/munices/mt48lc16m16a2-75.h
@@ -23,21 +23,8 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 #define SDRAM_CONTROL	0x504F0000
 #define SDRAM_CONFIG1	0xD2322800
 #define SDRAM_CONFIG2	0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/pm520/mt46v16m16-75.h b/board/pm520/mt46v16m16-75.h
index f650faaa10..423febe20a 100644
--- a/board/pm520/mt46v16m16-75.h
+++ b/board/pm520/mt46v16m16-75.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	1		/* is DDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x018D0000
 #define SDRAM_EMODE	0x40090000
@@ -31,7 +30,3 @@
 #define SDRAM_CONFIG1	0x73722930
 #define SDRAM_CONFIG2	0x47770000
 #define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/pm520/mt48lc16m16a2-75.h b/board/pm520/mt48lc16m16a2-75.h
index ffdf0396a5..15477259ca 100644
--- a/board/pm520/mt48lc16m16a2-75.h
+++ b/board/pm520/mt48lc16m16a2-75.h
@@ -23,21 +23,8 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 #define SDRAM_CONTROL	0x504F0000
 #define SDRAM_CONFIG1	0xD2322800
 #define SDRAM_CONFIG2	0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c
index 9da1041733..d6914343fa 100644
--- a/board/pm520/pm520.c
+++ b/board/pm520/pm520.c
@@ -84,7 +84,6 @@ static void sdram_start (int hi_addr)
  *            is something else than 0x00000000.
  */
 
-#if defined(CONFIG_MPC5200)
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
@@ -186,64 +185,9 @@ phys_size_t initdram (int board_type)
 	return dramsize + dramsize2;
 }
 
-#elif defined(CONFIG_MGT5100)
-
-phys_size_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup and enable SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
-	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
-	/* address select register */
-	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
-	__asm__ volatile ("sync");
-
-	/* find RAM size */
-	sdram_start(0);
-	test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* set SDRAM end address according to size */
-	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* Retrieve amount of SDRAM available */
-	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	return dramsize;
-}
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
-
 int checkboard (void)
 {
-#if defined(CONFIG_MPC5200)
 	puts ("Board: MicroSys PM520 \n");
-#elif defined(CONFIG_MGT5100)
-	puts ("Board: MicroSys PM510 \n");
-#endif
 	return 0;
 }
 
@@ -255,10 +199,6 @@ void flash_preinit(void)
 	 * Note that CS_BOOT cannot be cleared when
 	 * executing in flash.
 	 */
-#if defined(CONFIG_MGT5100)
-	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-#endif
 	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 }
 
diff --git a/board/total5200/mt48lc16m16a2-75.h b/board/total5200/mt48lc16m16a2-75.h
index 5b0923e3e8..ae237c6cab 100644
--- a/board/total5200/mt48lc16m16a2-75.h
+++ b/board/total5200/mt48lc16m16a2-75.h
@@ -23,21 +23,8 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 #define SDRAM_CONTROL	0x504F0000
 #define SDRAM_CONFIG1	0xD2322800
 #define SDRAM_CONFIG2	0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/total5200/mt48lc32m16a2-75.h b/board/total5200/mt48lc32m16a2-75.h
index 4b5ac80b35..cb4b43d63e 100644
--- a/board/total5200/mt48lc32m16a2-75.h
+++ b/board/total5200/mt48lc32m16a2-75.h
@@ -28,13 +28,8 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 #define SDRAM_CONTROL	0x514F0000
 #define SDRAM_CONFIG1	0xD2322800
 #define SDRAM_CONFIG2	0x8AD70000
-
-#else
-#error CONFIG_MPC5200 is not defined
-#endif
diff --git a/board/total5200/sdram.c b/board/total5200/sdram.c
index dc4c6f18c2..d883eb656d 100644
--- a/board/total5200/sdram.c
+++ b/board/total5200/sdram.c
@@ -76,7 +76,6 @@ static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr)
  *            is something else than 0x00000000.
  */
 
-#if defined(CONFIG_MPC5200)
 long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
 {
 	ulong dramsize = 0;
@@ -174,54 +173,3 @@ long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
 
 	return dramsize + dramsize2;
 }
-
-#elif defined(CONFIG_MGT5100)
-
-long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
-{
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup and enable SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
-	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2;
-
-	/* address select register */
-	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = sdram_conf->addrsel;
-	__asm__ volatile ("sync");
-
-	/* find RAM size */
-	mpc5xxx_sdram_start(sdram_conf, 0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	mpc5xxx_sdram_start(sdram_conf, 1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		mpc5xxx_sdram_start(sdram_conf, 0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* set SDRAM end address according to size */
-	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* Retrieve amount of SDRAM available */
-	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	return dramsize;
-}
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/total5200/sdram.h b/board/total5200/sdram.h
index bc21e1d300..396a190145 100644
--- a/board/total5200/sdram.h
+++ b/board/total5200/sdram.h
@@ -28,12 +28,7 @@ typedef struct {
 	ulong control;
 	ulong config1;
 	ulong config2;
-#if defined(CONFIG_MPC5200)
 	ulong tapdelay;
-#endif
-#if defined(CONFIG_MGT5100)
-	ulong addrsel;
-#endif
 } sdram_conf_t;
 
 long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf);
diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c
index c524d63f93..61b5b807af 100644
--- a/board/total5200/total5200.c
+++ b/board/total5200/total5200.c
@@ -47,26 +47,17 @@ phys_size_t initdram (int board_type)
 	sdram_conf.control = SDRAM_CONTROL;
 	sdram_conf.config1 = SDRAM_CONFIG1;
 	sdram_conf.config2 = SDRAM_CONFIG2;
-#if defined(CONFIG_MPC5200)
 	sdram_conf.tapdelay = 0;
-#endif
-#if defined(CONFIG_MGT5100)
-	sdram_conf.addrsel = SDRAM_ADDRSEL;
-#endif
 	return mpc5xxx_sdram_init (&sdram_conf);
 }
 
 int checkboard (void)
 {
-#if defined(CONFIG_MPC5200)
 #if CONFIG_TOTAL5200_REV==2
 	puts ("Board: Total5200 Rev.2 ");
 #else
 	puts ("Board: Total5200 ");
 #endif
-#elif defined(CONFIG_MGT5100)
-	puts ("Board: Total5100 ");
-#endif
 
 	/*
 	 * Retrieve FPGA Revision.
@@ -85,20 +76,6 @@ int checkboard (void)
 	return 0;
 }
 
-#if defined(CONFIG_MGT5100)
-int board_early_init_r(void)
-{
-	/*
-	 * Now, when we are in RAM, enable CS0
-	 * because CS_BOOT cannot be written.
-	 */
-	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-
-	return 0;
-}
-#endif
-
 #ifdef	CONFIG_PCI
 static struct pci_controller hose;
 
@@ -266,9 +243,7 @@ static const S1D_REGS init_regs [] =
 void video_get_info_str (int line_number, char *info)
 {
 	if (line_number == 1) {
-#ifdef CONFIG_MGT5100
-		strcpy (info, " Total5100");
-#elif CONFIG_TOTAL5200_REV==1
+#if CONFIG_TOTAL5200_REV==1
 		strcpy (info, " Total5200");
 #elif CONFIG_TOTAL5200_REV==2
 		strcpy (info, " Total5200 Rev.2");
diff --git a/board/tqc/tqm5200/mt48lc16m16a2-75.h b/board/tqc/tqm5200/mt48lc16m16a2-75.h
index 3f1e1691bb..48b43213dc 100644
--- a/board/tqc/tqm5200/mt48lc16m16a2-75.h
+++ b/board/tqc/tqm5200/mt48lc16m16a2-75.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 /* #define SDRAM_MODE	0x008D0000 */ /* CAS latency 2 */
@@ -33,15 +32,3 @@
 /*#define SDRAM_CONFIG1	0xD7322800 */ /* SDRAM controller bug workaround */
 #define SDRAM_CONFIG2	0x8AD70000
 /*#define SDRAM_CONFIG2	0xDDD70000 */ /* SDRAM controller bug workaround */
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index f8400bcc04..d22eb6634a 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static void print_num(const char *, ulong);
 
-#if !defined(CONFIG_ARM) || defined(CONFIG_CMD_NET)
+#if !(defined(CONFIG_ARM) || defined(CONFIG_M68K)) || defined(CONFIG_CMD_NET)
 static void print_eth(int idx);
 #endif
 
@@ -350,7 +350,7 @@ static void print_num(const char *name, ulong value)
 	printf ("%-12s= 0x%08lX\n", name, value);
 }
 
-#if !defined(CONFIG_ARM) || defined(CONFIG_CMD_NET)
+#if !(defined(CONFIG_ARM) || defined(CONFIG_M68K)) || defined(CONFIG_CMD_NET)
 static void print_eth(int idx)
 {
 	char name[10], *val;
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 995e378359..452686dd3d 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -463,7 +463,7 @@ static int bootm_start_standalone(ulong iflag, int argc, char *argv[])
 
 /* we overload the cmd field with our state machine info instead of a
  * function pointer */
-cmd_tbl_t cmd_bootm_sub[] = {
+static cmd_tbl_t cmd_bootm_sub[] = {
 	U_BOOT_CMD_MKENT(start, 0, 1, (void *)BOOTM_STATE_START, "", ""),
 	U_BOOT_CMD_MKENT(loados, 0, 1, (void *)BOOTM_STATE_LOADOS, "", ""),
 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC)
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index 62cbd335e5..8b9c2c9490 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -130,6 +130,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #endif
 
+#define DISP_LINE_LEN	16
+
 /* TODO: Implement architecture-specific get/set functions */
 unsigned int __def_i2c_get_bus_speed(void)
 {
@@ -149,12 +151,82 @@ int i2c_set_bus_speed(unsigned int)
 	__attribute__((weak, alias("__def_i2c_set_bus_speed")));
 
 /*
+ * get_alen: small parser helper function to get address length
+ * returns the address length,or 0 on error
+ */
+static uint get_alen(char *arg)
+{
+	int	j;
+	int	alen;
+
+	alen = 1;
+	for (j = 0; j < 8; j++) {
+		if (arg[j] == '.') {
+			alen = arg[j+1] - '0';
+			if (alen > 3) {
+				return 0;
+			}
+			break;
+		} else if (arg[j] == '\0')
+			break;
+	}
+	return alen;
+}
+
+/*
  * Syntax:
- *	i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
+ *	i2c read {i2c_chip} {devaddr}{.0, .1, .2} {len} {memaddr}
  */
-#define DISP_LINE_LEN	16
 
-int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u_char	chip;
+	uint	devaddr, alen, length;
+	u_char  *memaddr;
+
+	if (argc != 5) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	/*
+	 * I2C chip address
+	 */
+	chip = simple_strtoul(argv[1], NULL, 16);
+
+	/*
+	 * I2C data address within the chip.  This can be 1 or
+	 * 2 bytes long.  Some day it might be 3 bytes long :-).
+	 */
+	devaddr = simple_strtoul(argv[2], NULL, 16);
+	alen = get_alen(argv[2]);
+	if (alen == 0) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	/*
+	 * Length is the number of objects, not number of bytes.
+	 */
+	length = simple_strtoul(argv[3], NULL, 16);
+
+	/*
+	 * memaddr is the address where to store things in memory
+	 */
+	memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
+
+	if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) {
+		puts ("Error reading the chip.\n");
+		return 1;
+	}
+	return 0;
+}
+
+/*
+ * Syntax:
+ *	i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
+ */
+static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	u_char	chip;
 	uint	addr, alen, length;
@@ -177,7 +249,6 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		/*
 		 * New command specified.
 		 */
-		alen = 1;
 
 		/*
 		 * I2C chip address
@@ -189,17 +260,10 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		 * 2 bytes long.  Some day it might be 3 bytes long :-).
 		 */
 		addr = simple_strtoul(argv[2], NULL, 16);
-		alen = 1;
-		for (j = 0; j < 8; j++) {
-			if (argv[2][j] == '.') {
-				alen = argv[2][j+1] - '0';
-				if (alen > 4) {
-					cmd_usage(cmdtp);
-					return 1;
-				}
-				break;
-			} else if (argv[2][j] == '\0')
-				break;
+		alen = get_alen(argv[2]);
+		if (alen == 0) {
+			cmd_usage(cmdtp);
+			return 1;
 		}
 
 		/*
@@ -260,14 +324,13 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  * Syntax:
  *	i2c mw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
  */
-int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	uchar	chip;
 	ulong	addr;
 	uint	alen;
 	uchar	byte;
 	int	count;
-	int	j;
 
 	if ((argc < 4) || (argc > 5)) {
 		cmd_usage(cmdtp);
@@ -283,17 +346,10 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	 * Address is always specified.
 	 */
 	addr = simple_strtoul(argv[2], NULL, 16);
-	alen = 1;
-	for (j = 0; j < 8; j++) {
-		if (argv[2][j] == '.') {
-			alen = argv[2][j+1] - '0';
-			if (alen > 4) {
-				cmd_usage(cmdtp);
-				return 1;
-			}
-			break;
-		} else if (argv[2][j] == '\0')
-			break;
+	alen = get_alen(argv[2]);
+	if (alen == 0) {
+		cmd_usage(cmdtp);
+		return 1;
 	}
 
 	/*
@@ -332,7 +388,7 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  * Syntax:
  *	i2c crc32 {i2c_chip} {addr}{.0, .1, .2} {count}
  */
-int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	uchar	chip;
 	ulong	addr;
@@ -341,7 +397,6 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	uchar	byte;
 	ulong	crc;
 	ulong	err;
-	int	j;
 
 	if (argc < 4) {
 		cmd_usage(cmdtp);
@@ -357,17 +412,10 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	 * Address is always specified.
 	 */
 	addr = simple_strtoul(argv[2], NULL, 16);
-	alen = 1;
-	for (j = 0; j < 8; j++) {
-		if (argv[2][j] == '.') {
-			alen = argv[2][j+1] - '0';
-			if (alen > 4) {
-				cmd_usage(cmdtp);
-				return 1;
-			}
-			break;
-		} else if (argv[2][j] == '\0')
-			break;
+	alen = get_alen(argv[2]);
+	if (alen == 0) {
+		cmd_usage(cmdtp);
+		return 1;
 	}
 
 	/*
@@ -412,7 +460,6 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 	ulong	data;
 	int	size = 1;
 	int	nbytes;
-	int	j;
 	extern char console_buffer[];
 
 	if (argc != 3) {
@@ -447,17 +494,10 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 		 * Address is always specified.
 		 */
 		addr = simple_strtoul(argv[2], NULL, 16);
-		alen = 1;
-		for (j = 0; j < 8; j++) {
-			if (argv[2][j] == '.') {
-				alen = argv[2][j+1] - '0';
-				if (alen > 4) {
-					cmd_usage(cmdtp);
-					return 1;
-				}
-				break;
-			} else if (argv[2][j] == '\0')
-				break;
+		alen = get_alen(argv[2]);
+		if (alen == 0) {
+			cmd_usage(cmdtp);
+			return 1;
 		}
 	}
 
@@ -535,7 +575,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
  * Syntax:
  *	i2c probe {addr}{.0, .1, .2}
  */
-int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	int j;
 #if defined(CONFIG_SYS_I2C_NOPROBES)
@@ -579,7 +619,7 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  *	{length} - Number of bytes to read
  *	{delay}  - A DECIMAL number and defaults to 1000 uSec
  */
-int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	u_char	chip;
 	ulong	alen;
@@ -587,7 +627,6 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	uint	length;
 	u_char	bytes[16];
 	int	delay;
-	int	j;
 
 	if (argc < 3) {
 		cmd_usage(cmdtp);
@@ -603,17 +642,10 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	 * Address is always specified.
 	 */
 	addr = simple_strtoul(argv[2], NULL, 16);
-	alen = 1;
-	for (j = 0; j < 8; j++) {
-		if (argv[2][j] == '.') {
-			alen = argv[2][j+1] - '0';
-			if (alen > 4) {
-				cmd_usage(cmdtp);
-				return 1;
-			}
-			break;
-		} else if (argv[2][j] == '\0')
-			break;
+	alen = get_alen(argv[2]);
+	if (alen == 0) {
+		cmd_usage(cmdtp);
+		return 1;
 	}
 
 	/*
@@ -699,7 +731,7 @@ static void decode_bits (u_char const b, char const *str[], int const do_once)
  * Syntax:
  *	i2c sdram {i2c_chip}
  */
-int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	enum { unknown, EDO, SDRAM, DDR2 } type;
 
@@ -1176,7 +1208,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 #endif
 
 #if defined(CONFIG_I2C_MUX)
-int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	int ret=0;
 
@@ -1207,7 +1239,7 @@ int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 #endif  /* CONFIG_I2C_MUX */
 
 #if defined(CONFIG_I2C_MULTI_BUS)
-int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	int bus_idx, ret=0;
 
@@ -1225,7 +1257,7 @@ int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 }
 #endif  /* CONFIG_I2C_MULTI_BUS */
 
-int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	int speed, ret=0;
 
@@ -1242,46 +1274,60 @@ int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	return ret;
 }
 
-int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+static int do_i2c_mm(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-	/* Strip off leading 'i2c' command argument */
-	argc--;
-	argv++;
+	return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
+}
 
+static int do_i2c_nm(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
+}
+
+static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	return 0;
+}
+
+static cmd_tbl_t cmd_i2c_sub[] = {
 #if defined(CONFIG_I2C_MUX)
-	if (!strncmp(argv[0], "bu", 2))
-		return do_i2c_add_bus(cmdtp, flag, argc, argv);
+	U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_add_bus, "", ""),
 #endif  /* CONFIG_I2C_MUX */
-	if (!strncmp(argv[0], "sp", 2))
-		return do_i2c_bus_speed(cmdtp, flag, argc, argv);
+	U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
 #if defined(CONFIG_I2C_MULTI_BUS)
-	if (!strncmp(argv[0], "de", 2))
-		return do_i2c_bus_num(cmdtp, flag, argc, argv);
+	U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
 #endif  /* CONFIG_I2C_MULTI_BUS */
-	if (!strncmp(argv[0], "md", 2))
-		return do_i2c_md(cmdtp, flag, argc, argv);
-	if (!strncmp(argv[0], "mm", 2))
-		return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
-	if (!strncmp(argv[0], "mw", 2))
-		return do_i2c_mw(cmdtp, flag, argc, argv);
-	if (!strncmp(argv[0], "nm", 2))
-		return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
-	if (!strncmp(argv[0], "cr", 2))
-		return do_i2c_crc(cmdtp, flag, argc, argv);
-	if (!strncmp(argv[0], "pr", 2))
-		return do_i2c_probe(cmdtp, flag, argc, argv);
-	if (!strncmp(argv[0], "re", 2)) {
-		i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-		return 0;
-	}
-	if (!strncmp(argv[0], "lo", 2))
-		return do_i2c_loop(cmdtp, flag, argc, argv);
+	U_BOOT_CMD_MKENT(loop, 3, 1, do_i2c_loop, "", ""),
+	U_BOOT_CMD_MKENT(md, 3, 1, do_i2c_md, "", ""),
+	U_BOOT_CMD_MKENT(mm, 2, 1, do_i2c_mm, "", ""),
+	U_BOOT_CMD_MKENT(mw, 3, 1, do_i2c_mw, "", ""),
+	U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""),
+	U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
+	U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
+	U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
 #if defined(CONFIG_CMD_SDRAM)
-	if (!strncmp(argv[0], "sd", 2))
-		return do_sdram(cmdtp, flag, argc, argv);
+	U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
 #endif
-	cmd_usage(cmdtp);
-	return 0;
+	U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
+};
+
+static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	cmd_tbl_t *c;
+
+	/* Strip off leading 'i2c' command argument */
+	argc--;
+	argv++;
+
+	c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub));
+
+	if (c) {
+		return  c->cmd(cmdtp, flag, argc, argv);
+	} else {
+		cmd_usage(cmdtp);
+		return 1;
+	}
 }
 
 /***************************************************/
@@ -1289,30 +1335,29 @@ int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 U_BOOT_CMD(
 	i2c, 6, 1, do_i2c,
 	"I2C sub-system",
-	"speed [speed] - show or set I2C bus speed\n"
 #if defined(CONFIG_I2C_MUX)
-	"i2c bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes\n"
+	"bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes\ni2c "
 #endif  /* CONFIG_I2C_MUX */
+	"crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
 #if defined(CONFIG_I2C_MULTI_BUS)
 	"i2c dev [dev] - show or set current I2C bus\n"
 #endif  /* CONFIG_I2C_MULTI_BUS */
+	"i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
 	"i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
 	"i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
 	"i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
 	"i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
-	"i2c crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
 	"i2c probe - show devices on the I2C bus\n"
+	"i2c read chip address[.0, .1, .2] length memaddress - read to memory \n"
 	"i2c reset - re-init the I2C Controller\n"
-	"i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device"
 #if defined(CONFIG_CMD_SDRAM)
-	"\n"
-	"i2c sdram chip - print SDRAM configuration information"
+	"i2c sdram chip - print SDRAM configuration information\n"
 #endif
+	"i2c speed [speed] - show or set I2C bus speed"
 );
 
 #if defined(CONFIG_I2C_MUX)
-
-int i2c_mux_add_device(I2C_MUX_DEVICE *dev)
+static int i2c_mux_add_device(I2C_MUX_DEVICE *dev)
 {
 	I2C_MUX_DEVICE	*devtmp = i2c_mux_devices;
 
diff --git a/common/cmd_mtdparts.c b/common/cmd_mtdparts.c
index 20fed2aadc..0b5f747141 100644
--- a/common/cmd_mtdparts.c
+++ b/common/cmd_mtdparts.c
@@ -776,7 +776,7 @@ static int device_del(struct mtd_device *dev)
  * @param num device number
  * @return NULL if requested device does not exist
  */
-static struct mtd_device* device_find(u8 type, u8 num)
+struct mtd_device *device_find(u8 type, u8 num)
 {
 	struct list_head *entry;
 	struct mtd_device *dev_tmp;
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index 075a8afb60..9b0c930530 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -327,8 +327,14 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 			     "are sure of what you are doing!\n"
 			     "\nReally scrub this NAND flash? <y/N>\n");
 
-			if (getc() == 'y' && getc() == '\r') {
-				opts.scrub = 1;
+			if (getc() == 'y') {
+				puts("y");
+				if (getc() == '\r')
+					opts.scrub = 1;
+				else {
+					puts("scrub aborted\n");
+					return -1;
+				}
 			} else {
 				puts("scrub aborted\n");
 				return -1;
diff --git a/common/cmd_setexpr.c b/common/cmd_setexpr.c
index f8b5d4dcfe..2d3719755e 100644
--- a/common/cmd_setexpr.c
+++ b/common/cmd_setexpr.c
@@ -28,10 +28,33 @@
 #include <config.h>
 #include <command.h>
 
+static ulong get_arg(char *s, int w)
+{
+	ulong *p;
+
+        /*
+	 * if the parameter starts with a '*' then assume
+	 * it is a pointer to the value we want
+	 */
+
+	if (s[0] == '*') {
+		p = (ulong *)simple_strtoul(&s[1], NULL, 16);
+		switch (w) {
+		case 1: return((ulong)(*(uchar *)p));
+		case 2: return((ulong)(*(ushort *)p));
+		case 4:
+		default: return(*p);
+		}
+	} else {
+		return simple_strtoul(s, NULL, 16);
+	}
+}
+
 int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	ulong a, b;
 	char buf[16];
+	int w;
 
 	/* Validate arguments */
 	if ((argc != 5) || (strlen(argv[3]) != 1)) {
@@ -39,8 +62,10 @@ int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		return 1;
 	}
 
-	a = simple_strtoul(argv[2], NULL, 16);
-	b = simple_strtoul(argv[4], NULL, 16);
+	w = cmd_get_data_size(argv[0], 4);
+
+	a = get_arg(argv[2], w);
+	b = get_arg(argv[4], w);
 
 	switch (argv[3][0]) {
 	case '|': sprintf(buf, "%lx", (a | b)); break;
@@ -64,7 +89,8 @@ int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 U_BOOT_CMD(
 	setexpr, 5, 0, do_setexpr,
 	"set environment variable as the result of eval expression",
-	"name value1 <op> value2\n"
+	"[.b, .w, .l] name value1 <op> value2\n"
 	"    - set environment variable 'name' to the result of the evaluated\n"
-	"      express specified by <op>.  <op> can be &, |, ^, +, -, *, /, %"
+	"      express specified by <op>.  <op> can be &, |, ^, +, -, *, /, %\n"
+	"      size argument is only meaningful if value1 and/or value2 are memory addresses"
 );
diff --git a/common/fdt_support.c b/common/fdt_support.c
index f89a3eef66..b7d4fe5063 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -757,3 +757,222 @@ int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size)
 	return -1;
 }
 #endif
+
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+
+struct reg_cell {
+	unsigned int r0;
+	unsigned int r1;
+};
+
+int fdt_del_subnodes(const void *blob, int parent_offset)
+{
+	int off, ndepth;
+	int ret;
+
+	for (ndepth = 0, off = fdt_next_node(blob, parent_offset, &ndepth);
+	     (off >= 0) && (ndepth > 0);
+	     off = fdt_next_node(blob, off, &ndepth)) {
+		if (ndepth == 1) {
+			debug("delete %s: offset: %x\n",
+				fdt_get_name(blob, off, 0), off);
+			ret = fdt_del_node((void *)blob, off);
+			if (ret < 0) {
+				printf("Can't delete node: %s\n",
+					fdt_strerror(ret));
+				return ret;
+			} else {
+				ndepth = 0;
+				off = parent_offset;
+			}
+		}
+	}
+	return 0;
+}
+
+int fdt_increase_size(void *fdt, int add_len)
+{
+	int newlen;
+
+	newlen = fdt_totalsize(fdt) + add_len;
+
+	/* Open in place with a new len */
+	return fdt_open_into(fdt, fdt, newlen);
+}
+
+int fdt_del_partitions(void *blob, int parent_offset)
+{
+	const void *prop;
+	int ndepth = 0;
+	int off;
+	int ret;
+
+	off = fdt_next_node(blob, parent_offset, &ndepth);
+	if (off > 0 && ndepth == 1) {
+		prop = fdt_getprop(blob, off, "label", NULL);
+		if (prop == NULL) {
+			/*
+			 * Could not find label property, nand {}; node?
+			 * Check subnode, delete partitions there if any.
+			 */
+			return fdt_del_partitions(blob, off);
+		} else {
+			ret = fdt_del_subnodes(blob, parent_offset);
+			if (ret < 0) {
+				printf("Can't remove subnodes: %s\n",
+					fdt_strerror(ret));
+				return ret;
+			}
+		}
+	}
+	return 0;
+}
+
+int fdt_node_set_part_info(void *blob, int parent_offset,
+			   struct mtd_device *dev)
+{
+	struct list_head *pentry;
+	struct part_info *part;
+	struct reg_cell cell;
+	int off, ndepth = 0;
+	int part_num, ret;
+	char buf[64];
+
+	ret = fdt_del_partitions(blob, parent_offset);
+	if (ret < 0)
+		return ret;
+
+	/*
+	 * Check if it is nand {}; subnode, adjust
+	 * the offset in this case
+	 */
+	off = fdt_next_node(blob, parent_offset, &ndepth);
+	if (off > 0 && ndepth == 1)
+		parent_offset = off;
+
+	part_num = 0;
+	list_for_each_prev(pentry, &dev->parts) {
+		int newoff;
+
+		part = list_entry(pentry, struct part_info, link);
+
+		debug("%2d: %-20s0x%08x\t0x%08x\t%d\n",
+			part_num, part->name, part->size,
+			part->offset, part->mask_flags);
+
+		sprintf(buf, "partition@%x", part->offset);
+add_sub:
+		ret = fdt_add_subnode(blob, parent_offset, buf);
+		if (ret == -FDT_ERR_NOSPACE) {
+			ret = fdt_increase_size(blob, 512);
+			if (!ret)
+				goto add_sub;
+			else
+				goto err_size;
+		} else if (ret < 0) {
+			printf("Can't add partition node: %s\n",
+				fdt_strerror(ret));
+			return ret;
+		}
+		newoff = ret;
+
+		/* Check MTD_WRITEABLE_CMD flag */
+		if (part->mask_flags & 1) {
+add_ro:
+			ret = fdt_setprop(blob, newoff, "read_only", NULL, 0);
+			if (ret == -FDT_ERR_NOSPACE) {
+				ret = fdt_increase_size(blob, 512);
+				if (!ret)
+					goto add_ro;
+				else
+					goto err_size;
+			} else if (ret < 0)
+				goto err_prop;
+		}
+
+		cell.r0 = cpu_to_fdt32(part->offset);
+		cell.r1 = cpu_to_fdt32(part->size);
+add_reg:
+		ret = fdt_setprop(blob, newoff, "reg", &cell, sizeof(cell));
+		if (ret == -FDT_ERR_NOSPACE) {
+			ret = fdt_increase_size(blob, 512);
+			if (!ret)
+				goto add_reg;
+			else
+				goto err_size;
+		} else if (ret < 0)
+			goto err_prop;
+
+add_label:
+		ret = fdt_setprop_string(blob, newoff, "label", part->name);
+		if (ret == -FDT_ERR_NOSPACE) {
+			ret = fdt_increase_size(blob, 512);
+			if (!ret)
+				goto add_label;
+			else
+				goto err_size;
+		} else if (ret < 0)
+			goto err_prop;
+
+		part_num++;
+	}
+	return 0;
+err_size:
+	printf("Can't increase blob size: %s\n", fdt_strerror(ret));
+	return ret;
+err_prop:
+	printf("Can't add property: %s\n", fdt_strerror(ret));
+	return ret;
+}
+
+/*
+ * Update partitions in nor/nand nodes using info from
+ * mtdparts environment variable. The nodes to update are
+ * specified by node_info structure which contains mtd device
+ * type and compatible string: E. g. the board code in
+ * ft_board_setup() could use:
+ *
+ *	struct node_info nodes[] = {
+ *		{ "fsl,mpc5121-nfc",    MTD_DEV_TYPE_NAND, },
+ *		{ "cfi-flash",          MTD_DEV_TYPE_NOR,  },
+ *	};
+ *
+ *	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ */
+void fdt_fixup_mtdparts(void *blob, void *node_info, int node_info_size)
+{
+	struct node_info *ni = node_info;
+	struct mtd_device *dev;
+	char *parts;
+	int i, idx;
+	int noff;
+
+	parts = getenv("mtdparts");
+	if (!parts)
+		return;
+
+	if (mtdparts_init() != 0)
+		return;
+
+	for (i = 0; i < node_info_size; i++) {
+		idx = 0;
+		noff = fdt_node_offset_by_compatible(blob, -1, ni[i].compat);
+		while (noff != -FDT_ERR_NOTFOUND) {
+			debug("%s: %s, mtd dev type %d\n",
+				fdt_get_name(blob, noff, 0),
+				ni[i].compat, ni[i].type);
+			dev = device_find(ni[i].type, idx++);
+			if (dev) {
+				if (fdt_node_set_part_info(blob, noff, dev))
+					return; /* return on error */
+			}
+
+			/* Jump to next flash node */
+			noff = fdt_node_offset_by_compatible(blob, noff,
+							     ni[i].compat);
+		}
+	}
+}
+#endif
diff --git a/common/main.c b/common/main.c
index c860b0b0e5..3949a5bb22 100644
--- a/common/main.c
+++ b/common/main.c
@@ -68,7 +68,7 @@ static int abortboot(int);
 
 #undef DEBUG_PARSER
 
-char        console_buffer[CONFIG_SYS_CBSIZE];		/* console I/O buffer	*/
+char        console_buffer[CONFIG_SYS_CBSIZE + 1];	/* console I/O buffer	*/
 
 static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen);
 static char erase_seq[] = "\b \b";		/* erase sequence	*/
@@ -526,7 +526,7 @@ void reset_cmd_timeout(void)
 
 #define CTL_CH(c)		((c) - 'a' + 1)
 
-#define MAX_CMDBUF_SIZE		256
+#define MAX_CMDBUF_SIZE		CONFIG_SYS_CBSIZE
 
 #define CTL_BACKSPACE		('\b')
 #define DEL			((char)255)
@@ -546,7 +546,7 @@ static int hist_cur = -1;
 unsigned hist_num = 0;
 
 char* hist_list[HIST_MAX];
-char hist_lines[HIST_MAX][HIST_SIZE];
+char hist_lines[HIST_MAX][HIST_SIZE + 1];	 /* Save room for NULL */
 
 #define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1)
 
diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c
index e160ee1aff..beb78f5839 100644
--- a/cpu/mcf5227x/cpu_init.c
+++ b/cpu/mcf5227x/cpu_init.c
@@ -125,27 +125,27 @@ int cpu_init_r(void)
 	return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
-	switch (CONFIG_SYS_UART_PORT) {
+	switch (port) {
 	case 0:
 		gpio->par_uart &=
-		    (GPIO_PAR_UART_U0TXD_MASK & GPIO_PAR_UART_U0RXD_MASK);
+		    (GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK);
 		gpio->par_uart |=
 		    (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
 		break;
 	case 1:
 		gpio->par_uart &=
-		    (GPIO_PAR_UART_U1TXD_MASK & GPIO_PAR_UART_U1RXD_MASK);
+		    (GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK);
 		gpio->par_uart |=
 		    (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
 		break;
 	case 2:
 		gpio->par_dspi &=
-		    (GPIO_PAR_DSPI_SIN_MASK & GPIO_PAR_DSPI_SOUT_MASK);
+		    (GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK);
 		gpio->par_dspi =
 		    (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
 		break;
@@ -175,11 +175,11 @@ int cfspi_claim_bus(uint bus, uint cs)
 
 	switch (cs) {
 	case 0:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_MASK;
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_UNMASK;
 		gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
 		break;
 	case 2:
-		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK;
 		gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
 		break;
 	}
@@ -199,7 +199,7 @@ void cfspi_release_bus(uint bus, uint cs)
 		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
 		break;
 	case 2:
-		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK;
 		break;
 	}
 }
diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S
index 0c9c89c402..30428f15d8 100644
--- a/cpu/mcf5227x/start.S
+++ b/cpu/mcf5227x/start.S
@@ -24,16 +24,12 @@
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
+#include <asm/cache.h>
 
 #ifndef	 CONFIG_IDENT_STRING
 #define	 CONFIG_IDENT_STRING ""
 #endif
 
-/* last three long word reserved for cache status */
-#define ICACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
-#define DCACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
-#define CACR_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
-
 #define _START	_start
 #define _FAULT	_fault
 
@@ -378,21 +374,19 @@ _start:
 	movec	%d0, %RAMBAR1
 #endif
 
+	/* invalidate and disable cache */
+	move.l	#CF_CACR_CINV, %d0	/* Invalidate cache cmd */
+	movec	%d0, %CACR		/* Invalidate cache */
+	move.l	#0, %d0
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+
 	/* initialize general use internal ram */
 	move.l #0, %d0
 	move.l #(ICACHE_STATUS), %a1	/* icache */
 	move.l #(DCACHE_STATUS), %a2	/* icache */
-	move.l #(CACR_STATUS), %a3	/* CACR */
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
-	move.l %d0, (%a3)
-
-	/* invalidate and disable cache */
-	move.l	#0x01000000, %d0	/* Invalidate cache cmd */
-	movec	%d0, %CACR		/* Invalidate cache */
-	move.l	#0, %d0
-	movec	%d0, %ACR0
-	movec	%d0, %ACR1
 
 	/* set stackpointer to end of internal ram to get some stackspace for
 	   the first c-code */
@@ -510,84 +504,6 @@ _int_handler:
 	RESTORE_ALL
 
 /*------------------------------------------------------------------------------*/
-/* cache functions */
-	.globl	icache_enable
-icache_enable:
-	move.l	#0x01200000, %d0	/* Invalid cache */
-	movec	%d0, %CACR
-
-	move.l	#(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0
-	movec	%d0, %ACR0
-
-	move.l	#0x81600610, %d0	/* Enable cache */
-	movec	%d0, %CACR
-
-	move.l	#(ICACHE_STATUS), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_disable
-icache_disable:
-	move.l	#0x01F00000, %d0	/* Setup cache mask */
-	movec	%d0, %CACR		/* Invalidate icache */
-	clr.l	%d0
-	movec	%d0, %ACR0
-	movec	%d0, %ACR1
-
-	move.l	#(ICACHE_STATUS), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_status
-icache_status:
-	move.l	#(ICACHE_STATUS), %a1
-	move.l	(%a1), %d0
-	rts
-
-	.globl	icache_invalid
-icache_invalid:
-	move.l	#0x80600610, %d0	/* Invalidate icache */
-	movec	%d0, %CACR		/* Enable and invalidate cache */
-	rts
-
-	.globl	dcache_enable
-dcache_enable:
-	move.l	#0x01200000, %d0	/* Invalid cache */
-	movec	%d0, %CACR
-
-	move.l	#0x81300610, %d0
-	movec	%d0, %CACR
-
-	move.l	#(DCACHE_STATUS), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	dcache_disable
-dcache_disable:
-	move.l	#0x81600610, %d0	/* Setup cache mask */
-	movec	%d0, %CACR		/* Invalidate icache */
-
-	move.l	#(DCACHE_STATUS), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	dcache_invalid
-dcache_invalid:
-	move.l	#0x81100610, %d0	/* Setup cache mask */
-	movec	%d0, %CACR		/* Enable and invalidate cache */
-	rts
-
-	.globl	dcache_status
-dcache_status:
-	move.l	#(DCACHE_STATUS), %a1
-	move.l	(%a1), %d0
-	rts
-
-/*------------------------------------------------------------------------------*/
 
 	.globl	version_string
 version_string:
diff --git a/cpu/mcf523x/cpu_init.c b/cpu/mcf523x/cpu_init.c
index 3c04fd4134..0f299f0c3c 100644
--- a/cpu/mcf523x/cpu_init.c
+++ b/cpu/mcf523x/cpu_init.c
@@ -130,21 +130,32 @@ int cpu_init_r(void)
 	return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
-	switch (CONFIG_SYS_UART_PORT) {
+	switch (port) {
 	case 0:
-		gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
+		gpio->par_uart &= ~(GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
+		gpio->par_uart |= (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
 		break;
 	case 1:
-		gpio->par_uart =
-			(GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
+		gpio->par_uart &=
+		    ~(GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
+		gpio->par_uart |=
+		    (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
 		break;
 	case 2:
-		gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+#ifdef CONFIG_SYS_UART2_PRI_GPIO
+		gpio->par_uart &= ~(GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+		gpio->par_uart |= (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
+		gpio->feci2c &=
+		    ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
+		gpio->feci2c |=
+		    (GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
+#endif
 		break;
 	}
 }
@@ -156,7 +167,8 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 
 	if (setclear) {
 		gpio->par_feci2c |=
-		    (GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
+		    (GPIO_PAR_FECI2C_EMDC_FECEMDC |
+		     GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
 	} else {
 		gpio->par_feci2c &=
 		    ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
diff --git a/cpu/mcf523x/start.S b/cpu/mcf523x/start.S
index d44da37ec7..20b50e7579 100644
--- a/cpu/mcf523x/start.S
+++ b/cpu/mcf523x/start.S
@@ -24,6 +24,7 @@
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
+#include <asm/cache.h>
 
 #ifndef	 CONFIG_IDENT_STRING
 #define	 CONFIG_IDENT_STRING ""
@@ -135,7 +136,7 @@ _start:
 	movec	%d0, %RAMBAR1
 
 	/* invalidate and disable cache */
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
+	move.l	#CF_CACR_CINV, %d0		/* Invalidate cache cmd */
 	movec	%d0, %CACR			/* Invalidate cache */
 	nop
 	move.l	#0, %d0
@@ -144,8 +145,8 @@ _start:
 
 	/* initialize general use internal ram */
 	move.l #0, %d0
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2
+	move.l #(ICACHE_STATUS), %a1	/* icache */
+	move.l #(DCACHE_STATUS), %a2	/* icache */
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
 
@@ -265,74 +266,6 @@ _int_handler:
 	RESTORE_ALL
 
 /*------------------------------------------------------------------------------*/
-/* cache functions */
-	.globl	icache_enable
-icache_enable:
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-	nop
-	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0	/* Setup cache mask */
-	movec	%d0, %ACR0			/* Enable cache */
-	move.l	#(CONFIG_SYS_FLASH_BASE + 0xc000), %d0	/* Setup cache mask */
-	movec	%d0, %ACR1			/* Enable cache */
-
-	move.l	#0x80400100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	nop
-
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_disable
-icache_disable:
-	move.l	#0x00000100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Disable cache */
-	clr.l	%d0				/* Setup cache mask */
-	movec	%d0, %ACR0
-	movec	%d0, %ACR1
-
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_status
-icache_status:
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	move.l	(%a1), %d0
-	rts
-
-	.globl	icache_invalid
-icache_invalid:
-	move.l	#0x80600100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	nop
-	rts
-
-	.globl	dcache_enable
-dcache_enable:
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-    /* No dcache, just a dummy function */
-	.globl	dcache_disable
-dcache_disable:
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	dcache_status
-dcache_status:
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
-	move.l	(%a1), %d0
-	rts
-
-/*------------------------------------------------------------------------------*/
 
 	.globl	version_string
 version_string:
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 7cea6558fd..170bbfc356 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -5,6 +5,8 @@
  * MCF5282 additionals
  * (C) Copyright 2005
  * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
+ * (c) Copyright 2010
+ * Arcturus Networks Inc. <www.arcturusnetworks.com>
  *
  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
@@ -133,36 +135,36 @@ int cpu_init_r(void)
 	return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
-	switch (CONFIG_SYS_UART_PORT) {
+	switch (port) {
 	case 0:
-		gpio->par_uart &= GPIO_PAR_UART0_MASK;
+		gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
 		gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
 		break;
 	case 1:
-		gpio->par_uart &= GPIO_PAR_UART0_MASK;
+		gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
 		gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
 		break;
 	case 2:
 #ifdef CONFIG_SYS_UART2_PRI_GPIO
 		gpio->par_timer &=
-		    (GPIO_PAR_TMR_TIN0_MASK | GPIO_PAR_TMR_TIN1_MASK);
+		    (GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK);
 		gpio->par_timer |=
 		    (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
 #endif
 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
 		gpio->par_feci2c &=
-		    (GPIO_PAR_FECI2C_MDC_MASK | GPIO_PAR_FECI2C_MDIO_MASK);
+		    (GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK);
 		gpio->par_feci2c |=
 		    (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
 #endif
 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
 		gpio->par_feci2c &=
-		    (GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
+		    (GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
 		gpio->par_feci2c |=
 		    (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
 #endif
@@ -182,8 +184,8 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 		    GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
 	} else {
 		gpio->par_fec &=
-		    (GPIO_PAR_FEC_7W_MASK & GPIO_PAR_FEC_MII_MASK);
-		gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_MASK;
+		    (GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK);
+		gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_UNMASK;
 	}
 	return 0;
 }
@@ -245,15 +247,19 @@ int cpu_init_r(void)
 	return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
+	volatile u32 *par = (u32 *) MMAP_PAR;
+
 	/* Setup Ports: */
-	switch (CONFIG_SYS_UART_PORT) {
-	case 0:
-		break;
+	switch (port) {
 	case 1:
+		*par &= 0xFFE7FFFF;
+		*par |= 0x00180000;
 		break;
 	case 2:
+		*par &= 0xFFFFFFFC;
+		*par &= 0x00000003;
 		break;
 	}
 }
@@ -289,21 +295,26 @@ int cpu_init_r(void)
 	return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
+	u16 temp;
+
 	/* Setup Ports: */
-	switch (CONFIG_SYS_UART_PORT) {
+	switch (port) {
 	case 0:
-		mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
-				MCF_GPIO_PAR_UART_U0RXD);
+		temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3;
+		temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD);
+		mbar_writeShort(MCF_GPIO_PAR_UART, temp);
 		break;
 	case 1:
-		mbar_writeShort(MCF_GPIO_PAR_UART,
-				MCF_GPIO_PAR_UART_U1RXD_UART1 |
-				MCF_GPIO_PAR_UART_U1TXD_UART1);
+		temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF;
+		temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1);
+		mbar_writeShort(MCF_GPIO_PAR_UART, temp);
 		break;
 	case 2:
-		mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
+		temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF;
+		temp |= (0x3000);
+		mbar_writeShort(MCF_GPIO_PAR_UART, temp);
 		break;
 	}
 }
@@ -407,12 +418,12 @@ int cpu_init_r(void)
 	return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
-	switch (CONFIG_SYS_UART_PORT) {
+	switch (port) {
 	case 0:
 		gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
 		gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
@@ -485,19 +496,22 @@ int cpu_init_r(void)
 	return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
-	switch (CONFIG_SYS_UART_PORT) {
+	switch (port) {
 	case 0:
+		gpio->par_uart &= ~UART0_ENABLE_MASK;
 		gpio->par_uart |= UART0_ENABLE_MASK;
 		break;
 	case 1:
+		gpio->par_uart &= ~UART1_ENABLE_MASK;
 		gpio->par_uart |= UART1_ENABLE_MASK;
 		break;
 	case 2:
+		gpio->par_uart &= ~UART2_ENABLE_MASK;
 		gpio->par_uart |= UART2_ENABLE_MASK;
 		break;
 	}
@@ -582,6 +596,12 @@ void cpu_init_f(void)
 #ifdef CONFIG_SYS_PTCPAR
 	MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
 #endif
+#if defined(CONFIG_SYS_PORTTC)
+	MCFGPIO_PORTTC = CONFIG_SYS_PORTTC;
+#endif
+#if defined(CONFIG_SYS_DDRTC)
+	MCFGPIO_DDRTC  = CONFIG_SYS_DDRTC;
+#endif
 #ifdef CONFIG_SYS_PTDPAR
 	MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
 #endif
@@ -589,6 +609,9 @@ void cpu_init_f(void)
 	MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
 #endif
 
+#if defined(CONFIG_SYS_DDRD)
+	MCFGPIO_DDRD = CONFIG_SYS_DDRD;
+#endif
 #ifdef CONFIG_SYS_DDRUA
 	MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
 #endif
@@ -610,10 +633,10 @@ int cpu_init_r(void)
 	return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
 	/* Setup Ports: */
-	switch (CONFIG_SYS_UART_PORT) {
+	switch (port) {
 	case 0:
 		MCFGPIO_PUAPAR &= 0xFc;
 		MCFGPIO_PUAPAR |= 0x03;
@@ -718,14 +741,7 @@ int cpu_init_r(void)
 	return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
-	/* Setup Ports: */
-	switch (CONFIG_SYS_UART_PORT) {
-	case 0:
-		break;
-	case 1:
-		break;
-	}
 }
 #endif				/* #if defined(CONFIG_M5249) */
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index 0dd4de5160..9ef206aa0f 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -24,12 +24,12 @@
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
+#include <asm/cache.h>
 
 #ifndef	 CONFIG_IDENT_STRING
 #define	 CONFIG_IDENT_STRING ""
 #endif
 
-
 #define _START	_start
 #define _FAULT	_fault
 
@@ -201,6 +201,13 @@ _after_flashbar_copy:
 	movec	%d0, %RAMBAR1
 #endif
 
+	/* initialize general use internal ram */
+	move.l #0, %d0
+	move.l #(ICACHE_STATUS), %a1	/* icache */
+	move.l #(DCACHE_STATUS), %a2	/* icache */
+	move.l %d0, (%a1)
+	move.l %d0, (%a2)
+
 	/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
 	clr.l %sp@-
@@ -283,23 +290,6 @@ clear_bss:
 	cmp.l	%a2, %a1
 	bne	7b
 
-#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
-	/* patch the 3 accesspoints to 3 ichache_state */
-	/* quick and dirty */
-
-	move.l	%a0,%d1
-	add.l	#(icache_state - CONFIG_SYS_MONITOR_BASE),%d1
-	move.l	%a0,%a1
-	add.l	#(icache_state_access_1+2 - CONFIG_SYS_MONITOR_BASE),%a1
-	move.l  %d1,(%a1)
-	move.l	%a0,%a1
-	add.l	#(icache_state_access_2+2 - CONFIG_SYS_MONITOR_BASE),%a1
-	move.l  %d1,(%a1)
-	move.l	%a0,%a1
-	add.l	#(icache_state_access_3+2 - CONFIG_SYS_MONITOR_BASE),%a1
-	move.l  %d1,(%a1)
-#endif
-
 	/* calculate relative jump to board_init_r in ram */
 	move.l %a0, %a1
 	add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
@@ -336,156 +326,6 @@ _int_handler:
 	RESTORE_ALL
 
 /*------------------------------------------------------------------------------*/
-/* cache functions */
-#ifdef	CONFIG_M5208
-	.globl	icache_enable
-icache_enable:
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0	/* Setup cache mask */
-	movec	%d0, %ACR0			/* Enable cache */
-
-	move.l	#0x80000200, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	nop
-
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-#endif
-
-#ifdef	CONFIG_M5271
-	.globl	icache_enable
-icache_enable:
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0	/* Setup cache mask */
-	movec	%d0, %ACR0			/* Enable cache */
-
-	move.l	#0x80000200, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	nop
-
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-#endif
-
-#ifdef	CONFIG_M5272
-	.globl	icache_enable
-icache_enable:
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-	move.l	#0x0000c000, %d0		/* Setup cache mask */
-	movec	%d0, %ACR0			/* Enable cache */
-	move.l	#0xff00c000, %d0		/* Setup cache mask */
-	movec	%d0, %ACR1			/* Enable cache */
-	move.l	#0x80000100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	moveq	#1, %d0
-	move.l	%d0, icache_state
-	rts
-#endif
-
-#if  defined(CONFIG_M5275)
-/*
- * Instruction cache only
- */
-	.globl	icache_enable
-icache_enable:
-	move.l	#0x01400000, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-	move.l	#0x0000c000, %d0		/* Setup SDRAM caching */
-	movec	%d0, %ACR0			/* Enable cache */
-	move.l	#0x00000000, %d0		/* No other caching */
-	movec	%d0, %ACR1			/* Enable cache */
-	move.l	#0x80400100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	moveq	#1, %d0
-	move.l	%d0, icache_state
-	rts
-#endif
-
-#ifdef CONFIG_M5282
-	.globl	icache_enable
-icache_enable:
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-	move.l	#0x0000c000, %d0		/* Setup cache mask */
-	movec	%d0, %ACR0			/* Enable cache */
-	move.l	#0xff00c000, %d0		/* Setup cache mask */
-	movec	%d0, %ACR1			/* Enable cache */
-	move.l	#0x80400100, %d0		/* Setup cache mask, data cache disabel*/
-	movec	%d0, %CACR			/* Enable cache */
-	moveq	#1, %d0
-icache_state_access_1:
-	move.l	%d0, icache_state
-	rts
-#endif
-
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
-	.globl	icache_enable
-icache_enable:
-	/*
-	 *  Note: The 5249 Documentation doesn't give a bit position for CINV!
-	 *  From the 5272 and the 5307 documentation, I have deduced that it is
-	 *  probably CACR[24]. Should someone say something to Motorola?
-	 *	~Jeremy
-	 */
-	move.l	#0x01000000, %d0		/* Invalidate whole cache */
-	move.c	%d0,%CACR
-	move.l	#0xff00c000, %d0		/* Set FLASH cachable: always match (SM=0b10) */
-	move.c	%d0, %ACR0
-	move.l	#0x0000c000, %d0		/* Set SDRAM cachable: always match (SM=0b10) */
-	move.c	%d0, %ACR1
-	move.l	#0x90000200, %d0		/* Set cache enable cmd */
-	move.c	%d0,%CACR
-	moveq	#1, %d0
-	move.l	%d0, icache_state
-	rts
-#endif
-
-	.globl	icache_disable
-icache_disable:
-	move.l	#0x00000100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	clr.l	%d0				/* Setup cache mask */
-	movec	%d0, %ACR0			/* Enable cache */
-	movec	%d0, %ACR1			/* Enable cache */
-	moveq	#0, %d0
-icache_state_access_2:
-	move.l	%d0, icache_state
-	rts
-
-	.globl	icache_status
-icache_status:
-icache_state_access_3:
-	move.l	#(icache_state), %a0
-	move.l	(%a0), %d0
-	rts
-
-	.data
-icache_state:
-	.long	0	/* cache is diabled on inirialization */
-
-	.globl	dcache_enable
-dcache_enable:
-	/* dummy function */
-	rts
-
-	.globl	dcache_disable
-dcache_disable:
-	/* dummy function */
-	rts
-
-	.globl	dcache_status
-dcache_status:
-	/* dummy function */
-	rts
-
-/*------------------------------------------------------------------------------*/
 
 	.globl	version_string
 version_string:
diff --git a/cpu/mcf532x/config.mk b/cpu/mcf532x/config.mk
index 0cb90ac4e2..b783444ae8 100644
--- a/cpu/mcf532x/config.mk
+++ b/cpu/mcf532x/config.mk
@@ -24,8 +24,20 @@
 #
 
 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+
+cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5301x:=$(shell grep CONFIG_MCF5301x $(TOPDIR)/include/$(cfg))
+is532x:=$(shell grep CONFIG_MCF532x $(TOPDIR)/include/$(cfg))
+
 ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
+
+ifneq (,$(findstring CONFIG_MCF5301x,$(is5301x)))
+PLATFORM_CPPFLAGS += -mcpu=53015 -fPIC
+endif
+ifneq (,$(findstring CONFIG_MCF532x,$(is532x)))
 PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC
+endif
+
 else
 PLATFORM_CPPFLAGS += -m5307 -fPIC
 endif
diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c
index 4f1695cef8..6f551b60c9 100644
--- a/cpu/mcf532x/cpu_init.c
+++ b/cpu/mcf532x/cpu_init.c
@@ -133,24 +133,26 @@ int cpu_init_r(void)
 	return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
-	switch (CONFIG_SYS_UART_PORT) {
+	switch (port) {
 	case 0:
-		gpio->par_uart = (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+		gpio->par_uart &= ~(GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+		gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
 		break;
 	case 1:
 #ifdef CONFIG_SYS_UART1_ALT1_GPIO
 		gpio->par_simp1h &=
-		    ~(GPIO_PAR_SIMP1H_DATA1_MASK | GPIO_PAR_SIMP1H_VEN1_MASK);
+		    ~(GPIO_PAR_SIMP1H_DATA1_UNMASK |
+		      GPIO_PAR_SIMP1H_VEN1_UNMASK);
 		gpio->par_simp1h |=
 		    (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD);
 #elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
 		gpio->par_ssih &=
-		    ~(GPIO_PAR_SSIH_RXD_MASK | GPIO_PAR_SSIH_TXD_MASK);
+		    ~(GPIO_PAR_SSIH_RXD_UNMASK | GPIO_PAR_SSIH_TXD_UNMASK);
 		gpio->par_ssih |=
 		    (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD);
 #endif
@@ -160,12 +162,12 @@ void uart_port_conf(void)
 		gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD);
 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
 		gpio->par_dspih &=
-		    ~(GPIO_PAR_DSPIH_SIN_MASK | GPIO_PAR_DSPIH_SOUT_MASK);
+		    ~(GPIO_PAR_DSPIH_SIN_UNMASK | GPIO_PAR_DSPIH_SOUT_UNMASK);
 		gpio->par_dspih |=
 		    (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD);
 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
 		gpio->par_feci2c &=
-		    ~(GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
+		    ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
 		gpio->par_feci2c |=
 		    (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
 #endif
@@ -195,11 +197,11 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
 			gpio->par_fec &=
 			    ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
-			gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_MASK;
+			gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_UNMASK;
 		} else {
 			gpio->par_fec &=
 			    ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
-			gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_MASK;
+			gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_UNMASK;
 		}
 	}
 	return 0;
@@ -297,22 +299,33 @@ int cpu_init_r(void)
 	return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
-	switch (CONFIG_SYS_UART_PORT) {
+	switch (port) {
 	case 0:
-		gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
+		gpio->par_uart &= ~(GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
+		gpio->par_uart |= (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
 		break;
 	case 1:
-		gpio->par_uart =
+		gpio->par_uart &=
+		    ~(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
+		gpio->par_uart |=
 		    (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
 		break;
 	case 2:
+#ifdef CONFIG_SYS_UART2_ALT1_GPIO
 		gpio->par_timer &= 0x0F;
 		gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
+#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
+		gpio->par_feci2c &= 0xFF00;
+		gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
+#elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
+		gpio->par_ssi &= 0xF0FF;
+		gpio->par_ssi |= (GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
+#endif
 		break;
 	}
 }
diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c
index 67f08c7602..5a29e2567a 100644
--- a/cpu/mcf532x/speed.c
+++ b/cpu/mcf532x/speed.c
@@ -229,7 +229,7 @@ int clock_pll(int fsys, int flags)
 	    PLL_PDR_OUTDIV3((BUSDIV / 2) - 1)	|
 	    PLL_PDR_OUTDIV4(USBDIV - 1);
 
-	pll->pcr &= PLL_PCR_FBDIV_MASK;
+	pll->pcr &= PLL_PCR_FBDIV_UNMASK;
 	pll->pcr |= PLL_PCR_FBDIV(mfd - 1);
 #endif
 #ifdef CONFIG_MCF532x
diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S
index 5b134aa47c..a80b0a9946 100644
--- a/cpu/mcf532x/start.S
+++ b/cpu/mcf532x/start.S
@@ -27,6 +27,7 @@
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
+#include <asm/cache.h>
 
 #ifndef	 CONFIG_IDENT_STRING
 #define	 CONFIG_IDENT_STRING ""
@@ -142,7 +143,7 @@ _start:
 	movec	%d0, %RAMBAR1
 
 	/* invalidate and disable cache */
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
+	move.l	#CF_CACR_CINVA, %d0		/* Invalidate cache cmd */
 	movec	%d0, %CACR			/* Invalidate cache */
 	move.l	#0, %d0
 	movec	%d0, %ACR0
@@ -158,8 +159,8 @@ _start:
 
 	/* initialize general use internal ram */
 	move.l #0, %d0
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2
+	move.l #(ICACHE_STATUS), %a1	/* icache */
+	move.l #(DCACHE_STATUS), %a2	/* icache */
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
 
@@ -279,71 +280,6 @@ _int_handler:
 	RESTORE_ALL
 
 /*------------------------------------------------------------------------------*/
-/* cache functions */
-	.globl	icache_enable
-icache_enable:
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-	move.l  #(CONFIG_SYS_SDRAM_BASE + 0xc000 + ((CONFIG_SYS_SDRAM_SIZE & 0x1fe0) << 11)), %d0
-	movec	%d0, %ACR0			/* Enable cache */
-
-	move.l	#0x80000200, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	nop
-
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_disable
-icache_disable:
-	move.l	#0x01000000, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Disable cache */
-	clr.l	%d0				/* Setup cache mask */
-	movec	%d0, %ACR0
-	movec	%d0, %ACR1
-
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_status
-icache_status:
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	move.l	(%a1), %d0
-	rts
-
-	.globl	icache_invalid
-icache_invalid:
-	move.l	#0x81000200, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	rts
-
-	.globl	dcache_enable
-dcache_enable:
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-    /* No dcache, just a dummy function */
-	.globl	dcache_disable
-dcache_disable:
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	dcache_status
-dcache_status:
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
-	move.l	(%a1), %d0
-	rts
-
-/*------------------------------------------------------------------------------*/
-
 	.globl	version_string
 version_string:
 	.ascii U_BOOT_VERSION
diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c
index 48b37dfe7d..8d51d35d68 100644
--- a/cpu/mcf5445x/cpu_init.c
+++ b/cpu/mcf5445x/cpu_init.c
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <watchdog.h>
 #include <asm/immap.h>
+#include <asm/processor.h>
 #include <asm/rtc.h>
 
 #if defined(CONFIG_CMD_NET)
@@ -105,6 +106,14 @@ void cpu_init_f(void)
 	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
 #endif
 
+	/*
+	 * now the flash base address is no longer at 0 (Newer ColdFire family
+	 * boot at address 0 instead of 0xFFnn_nnnn). The vector table must
+	 * also move to the new location.
+	 */
+	if (CONFIG_SYS_CS0_BASE != 0)
+		setvbr(CONFIG_SYS_CS0_BASE);
+
 #ifdef CONFIG_FSL_I2C
 	gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
 #endif
@@ -128,19 +137,43 @@ int cpu_init_r(void)
 	return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
-	switch (CONFIG_SYS_UART_PORT) {
+	switch (port) {
 	case 0:
-		gpio->par_uart =
+		gpio->par_uart &=
+		    ~(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+		gpio->par_uart |=
 		    (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
 		break;
 	case 1:
-		gpio->par_uart =
+#ifdef CONFIG_SYS_UART1_PRI_GPIO
+		gpio->par_uart &=
+		    ~(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+		gpio->par_uart |=
 		    (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+#elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
+		gpio->par_ssi &=
+		    (GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK);
+		gpio->par_ssi |=
+		    (GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
+#endif
+		break;
+	case 2:
+#if defined(CONFIG_SYS_UART2_ALT1_GPIO)
+		gpio->par_timer &=
+		    (GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK);
+		gpio->par_timer |=
+		    (GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
+#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
+		gpio->par_timer &=
+		    (GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK);
+		gpio->par_timer |=
+		    (GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
+#endif
 		break;
 	}
 }
@@ -164,9 +197,9 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 		    ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
 
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
-			gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
+			gpio->par_fec &= GPIO_PAR_FEC_FEC0_UNMASK;
 		else
-			gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
+			gpio->par_fec &= GPIO_PAR_FEC_FEC1_UNMASK;
 	}
 	return 0;
 }
diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S
index d2d4439151..738e4a7110 100644
--- a/cpu/mcf5445x/start.S
+++ b/cpu/mcf5445x/start.S
@@ -24,16 +24,12 @@
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
+#include <asm/cache.h>
 
 #ifndef	 CONFIG_IDENT_STRING
 #define	 CONFIG_IDENT_STRING ""
 #endif
 
-/* last three long word reserved for cache status */
-#define CACR_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
-#define ICACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
-#define DCACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
-
 #define _START	_start
 #define _FAULT	_fault
 
@@ -160,15 +156,13 @@ asm_dram_init:
 
 	/* initialize general use internal ram */
 	move.l #0, %d0
-	move.l #(CACR_STATUS), %a1	/* CACR */
-	move.l #(ICACHE_STATUS), %a2	/* icache */
-	move.l #(DCACHE_STATUS), %a3	/* dcache */
+	move.l #(ICACHE_STATUS), %a1	/* icache */
+	move.l #(DCACHE_STATUS), %a2	/* dcache */
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
-	move.l %d0, (%a3)
 
 	/* invalidate and disable cache */
-	move.l	#0x01004100, %d0	/* Invalidate cache cmd */
+	move.l	#(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
 	movec	%d0, %CACR		/* Invalidate cache */
 	move.l	#0, %d0
 	movec	%d0, %ACR0
@@ -411,15 +405,13 @@ _start:
 
 	/* initialize general use internal ram */
 	move.l #0, %d0
-	move.l #(CACR_STATUS), %a1	/* CACR */
-	move.l #(ICACHE_STATUS), %a2	/* icache */
-	move.l #(DCACHE_STATUS), %a3	/* dcache */
+	move.l #(ICACHE_STATUS), %a1	/* icache */
+	move.l #(DCACHE_STATUS), %a2	/* dcache */
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
-	move.l %d0, (%a3)
 
 	/* invalidate and disable cache */
-	move.l	#0x01004100, %d0	/* Invalidate cache cmd */
+	move.l	#(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
 	movec	%d0, %CACR		/* Invalidate cache */
 	move.l	#0, %d0
 	movec	%d0, %ACR0
@@ -544,107 +536,6 @@ _int_handler:
 	RESTORE_ALL
 
 /*------------------------------------------------------------------------------*/
-/* cache functions */
-	.globl	icache_enable
-icache_enable:
-	move.l #(CACR_STATUS), %a1	/* read CACR Status */
-	move.l	(%a1), %d1
-
-	move.l	#0x00040100, %d0	/* Invalidate icache */
-	movec	%d0, %CACR
-
-	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0	/* Setup icache */
-	movec	%d0, %ACR2
-
-	move.l	#0x04088020, %d0	/* Enable bcache and icache */
-	movec	%d0, %CACR
-
-	move.l #(ICACHE_STATUS), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_disable
-icache_disable:
-	move.l #(CACR_STATUS), %a1	/* read CACR Status */
-	move.l	(%a1), %d0
-
-	move.l	#0xFFF77BFF, %d0
-	or.l	#0x00040100, %d0	/* Setup cache mask */
-	movec	%d0, %CACR		/* Invalidate icache */
-	clr.l	%d0
-	movec	%d0, %ACR2
-	movec	%d0, %ACR3
-
-	move.l #(ICACHE_STATUS), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_status
-icache_status:
-	move.l #(ICACHE_STATUS), %a1
-	move.l	(%a1), %d0
-	rts
-
-	.globl	icache_invalid
-icache_invalid:
-	move.l #(CACR_STATUS), %a1	/* read CACR Status */
-	move.l	(%a1), %d0
-
-	move.l	#0x00040100, %d0	/* Invalidate icache */
-	movec	%d0, %CACR		/* Enable and invalidate cache */
-	rts
-
-	.globl	dcache_enable
-dcache_enable:
-	move.l #(CACR_STATUS), %a1	/* read CACR Status */
-	move.l	(%a1), %d1
-
-	move.l	#0x01040100, %d0
-	movec	%d0, %CACR		/* Invalidate dcache */
-
-	move.l	#0x80088020, %d0	/* Enable bcache and icache */
-	movec	%d0, %CACR
-
-	move.l #(DCACHE_STATUS), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	dcache_disable
-dcache_disable:
-	move.l #(CACR_STATUS), %a1	/* read CACR Status */
-	move.l	(%a1), %d0
-
-	and.l	#0x7FFFFFFF, %d0
-	or.l	#0x01000000, %d0	/* Setup cache mask */
-	movec	%d0, %CACR		/* Disable dcache */
-	clr.l	%d0
-	movec	%d0, %ACR0
-	movec	%d0, %ACR1
-
-	move.l #(DCACHE_STATUS), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	dcache_invalid
-dcache_invalid:
-	move.l #(CACR_STATUS), %a1	/* read CACR Status */
-	move.l	(%a1), %d0
-
-	move.l	#0x81088020, %d0	/* Setup cache mask */
-	movec	%d0, %CACR		/* Enable and invalidate cache */
-	rts
-
-	.globl	dcache_status
-dcache_status:
-	move.l #(DCACHE_STATUS), %a1
-	move.l	(%a1), %d0
-	rts
-
-/*------------------------------------------------------------------------------*/
 
 	.globl	version_string
 version_string:
diff --git a/cpu/mcf547x_8x/cpu_init.c b/cpu/mcf547x_8x/cpu_init.c
index 96a3132b78..60c91267a7 100644
--- a/cpu/mcf547x_8x/cpu_init.c
+++ b/cpu/mcf547x_8x/cpu_init.c
@@ -113,13 +113,13 @@ int cpu_init_r(void)
 	return (0);
 }
 
-void uart_port_conf(void)
+void uart_port_conf(int port)
 {
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
 
 	/* Setup Ports: */
-	switch (CONFIG_SYS_UART_PORT) {
+	switch (port) {
 	case 0:
 		gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
 		break;
diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S
index 94ef14bf3d..84118629e2 100644
--- a/cpu/mcf547x_8x/start.S
+++ b/cpu/mcf547x_8x/start.S
@@ -24,16 +24,12 @@
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
+#include <asm/cache.h>
 
 #ifndef	 CONFIG_IDENT_STRING
 #define	 CONFIG_IDENT_STRING ""
 #endif
 
-/* last three long word reserved for cache status */
-#define ICACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
-#define DCACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
-#define CACR_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
-
 #define _START	_start
 #define _FAULT	_fault
 
@@ -158,10 +154,8 @@ _start:
 	move.l #0, %d0
 	move.l #(ICACHE_STATUS), %a1	/* icache */
 	move.l #(DCACHE_STATUS), %a2	/* icache */
-	move.l #(CACR_STATUS), %a3	/* CACR */
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
-	move.l %d0, (%a3)
 
 	/* set stackpointer to end of internal ram to get some stackspace for the
 	   first c-code */
@@ -279,81 +273,6 @@ _int_handler:
 	RESTORE_ALL
 
 /*------------------------------------------------------------------------------*/
-/* cache functions */
-	.globl	icache_enable
-icache_enable:
-	move.l	#(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0
-	movec	%d0, %ACR2			/* Enable cache */
-
-	move.l	#0x020C8100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	nop
-
-	move.l #(ICACHE_STATUS), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_disable
-icache_disable:
-	move.l	#0x000C8100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Disable cache */
-	clr.l	%d0				/* Setup cache mask */
-	movec	%d0, %ACR2
-	movec	%d0, %ACR3
-
-	move.l #(ICACHE_STATUS), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_invalid
-icache_invalid:
-	move.l	#0x000C8100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	rts
-
-	.globl	icache_status
-icache_status:
-	move.l #(ICACHE_STATUS), %a1
-	move.l	(%a1), %d0
-	rts
-
-	.globl	dcache_enable
-dcache_enable:
-	bsr	icache_disable
-
-	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0
-	movec	%d0, %ACR0			/* Enable cache */
-
-	move.l	#0xA30C8100, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-
-	move.l #(DCACHE_STATUS), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	dcache_disable
-dcache_disable:
-	move.l	#0xA30C8100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Disable cache */
-	clr.l	%d0				/* Setup cache mask */
-	movec	%d0, %ACR0
-	movec	%d0, %ACR1
-
-	move.l #(DCACHE_STATUS), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	dcache_status
-dcache_status:
-	move.l #(DCACHE_STATUS), %a1
-	move.l	(%a1), %d0
-	rts
-
-/*------------------------------------------------------------------------------*/
 
 	.globl	version_string
 version_string:
diff --git a/cpu/mpc5xxx/Makefile b/cpu/mpc5xxx/Makefile
index 06fdbcfb72..0ee0611550 100644
--- a/cpu/mpc5xxx/Makefile
+++ b/cpu/mpc5xxx/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-SOBJS	= io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
+SOBJS	= io.o firmware_sc_task_bestcomm.impl.o
 COBJS	= i2c.o traps.o cpu.o cpu_init.o ide.o interrupts.o \
 	  loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o
 
diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c
index edfb8282b7..b20234d32e 100644
--- a/cpu/mpc5xxx/cpu.c
+++ b/cpu/mpc5xxx/cpu.c
@@ -50,16 +50,10 @@ int checkcpu (void)
 {
 	ulong clock = gd->cpu_clk;
 	char buf[32];
-#ifndef CONFIG_MGT5100
 	uint svr, pvr;
-#endif
 
 	puts ("CPU:   ");
 
-#ifdef CONFIG_MGT5100
-	puts   (CPU_ID_STR);
-	printf (" (JTAG ID %08lx)", *(vu_long *)MPC5XXX_CDM_JTAGID);
-#else
 	svr = get_svr();
 	pvr = get_pvr();
 
@@ -77,7 +71,6 @@ int checkcpu (void)
 
 	printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr),
 		PVR_MAJ(pvr), PVR_MIN(pvr));
-#endif
 	printf (" at %s MHz\n", strmhz (buf, clock));
 	return 0;
 }
diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c
index 560c9b311c..9daf3755ac 100644
--- a/cpu/mpc5xxx/cpu_init.c
+++ b/cpu/mpc5xxx/cpu_init.c
@@ -53,10 +53,6 @@ void cpu_init_f (void)
 		(struct mpc5xxx_gpt *) MPC5XXX_GPT;
 #endif /* CONFIG_WATCHDOG */
 	unsigned long addecr = (1 << 25); /* Boot_CS */
-
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_MGT5100)
-	addecr |= (1 << 22); /* SDRAM enable */
-#endif
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 
@@ -136,7 +132,6 @@ void cpu_init_f (void)
 	out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG);
 #endif
 
-#if defined(CONFIG_MPC5200)
 	addecr |= 1;
 #if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
 	out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START));
@@ -164,14 +159,9 @@ void cpu_init_f (void)
 #if defined(CONFIG_SYS_CS_DEADCYCLE)
 	out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE);
 #endif
-#endif /* CONFIG_MPC5200 */
 
 	/* Enable chip selects */
-#if defined(CONFIG_MGT5100)
-	out_be32(&mm->addecr, addecr);
-#elif defined(CONFIG_MPC5200)
 	out_be32(&mm->ipbi_ws_ctrl, addecr);
-#endif
 	out_be32(&lpb->cs_ctrl, (1 << 24));
 
 	/* Setup pin multiplexing */
@@ -179,7 +169,6 @@ void cpu_init_f (void)
 	out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
 #endif
 
-#if defined(CONFIG_MPC5200)
 	/* enable timebase */
 	setbits_be32(&xlb->config, (1 << 13));
 
@@ -187,33 +176,29 @@ void cpu_init_f (void)
 	setbits_be32(&xlb->config, (1 << 15));
 	out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d);
 
-# if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
+#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
 	/* Motorola reports IPB should better run at 133 MHz. */
-#  if defined(CONFIG_MGT5100)
-	setbits_be32(&mm->addecr, 1);
-#  elif defined(CONFIG_MPC5200)
 	setbits_be32(&mm->ipbi_ws_ctrl, 1);
-#  endif
 	/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
 	addecr = in_be32(&cdm->cfg);
 	addecr &= ~0x103;
-#  if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
+# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
 	/* pci_clk_sel = 0x01 -> IPB_CLK/2 */
 	addecr |= 0x01;
-#  else
+# else
 	/* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
 	addecr |= 0x02;
-#  endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
+# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
 	out_be32(&cdm->cfg, addecr);
-# endif	/* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
+#endif	/* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
 	/* Configure the XLB Arbiter */
 	out_be32(&xlb->master_pri_enable, 0xff);
 	out_be32(&xlb->master_priority, 0x11111111);
 
-# if defined(CONFIG_SYS_XLB_PIPELINING)
+#if defined(CONFIG_SYS_XLB_PIPELINING)
 	/* Enable piplining */
 	clrbits_be32(&xlb->config, (1 << 31));
-# endif
+#endif
 
 #if defined(CONFIG_WATCHDOG)
 	/* Charge the watchdog timer - prescaler = 64k, count = 64k*/
@@ -222,8 +207,6 @@ void cpu_init_f (void)
 
 	reset_5xxx_watchdog();
 #endif /* CONFIG_WATCHDOG */
-
-#endif	/* CONFIG_MPC5200 */
 }
 
 /*
@@ -235,11 +218,7 @@ int cpu_init_r (void)
 		(struct mpc5xxx_intr *) MPC5XXX_ICTL;
 
 	/* mask all interrupts */
-#if defined(CONFIG_MGT5100)
-	out_be32(&intr->per_mask, 0xfffffc00);
-#elif defined(CONFIG_MPC5200)
 	out_be32(&intr->per_mask, 0xffffff00);
-#endif
 	setbits_be32(&intr->main_mask, 0x0001ffff);
 	clrbits_be32(&intr->ctrl, 0x00000f00);
 	/* route critical ints to normal ints */
diff --git a/cpu/mpc5xxx/firmware_sc_task.impl.S b/cpu/mpc5xxx/firmware_sc_task.impl.S
deleted file mode 100644
index b668ee5cf8..0000000000
--- a/cpu/mpc5xxx/firmware_sc_task.impl.S
+++ /dev/null
@@ -1,364 +0,0 @@
-/*
- * Copyright (C) 2001, Software Center, Motorola China.
- *
- * This file contains microcode for the FEC controller of the MGT5100 CPU.
- */
-
-#include <config.h>
-
-#if defined(CONFIG_MGT5100)
-
-/* sas/sccg, gas target */
-.section	smartdmaInitData,"aw",@progbits	/* Initialized data for task variables */
-.section	smartdmaTaskTable,"aw",@progbits	/* Task tables */
-.globl taskTable
-taskTable:
-.globl scEthernetRecv_Entry
-scEthernetRecv_Entry:		/* Task 0 */
-.long	scEthernetRecv_TDT - taskTable	/* Task 0 Descriptor Table */
-.long	scEthernetRecv_TDT - taskTable + 0x000000a4
-.long	scEthernetRecv_VarTab - taskTable	/* Task 0 Variable Table */
-.long	scEthernetRecv_FDT - taskTable + 0x03	/* Task 0 Function Descriptor Table & Flags */
-.long	0x00000000
-.long	0x00000000
-.long	scEthernetRecv_CSave - taskTable	/* Task 0 context save space */
-.long	0xf0000000
-.globl scEthernetXmit_Entry
-scEthernetXmit_Entry:		/* Task 1 */
-.long	scEthernetXmit_TDT - taskTable	/* Task 1 Descriptor Table */
-.long	scEthernetXmit_TDT - taskTable + 0x000000d0
-.long	scEthernetXmit_VarTab - taskTable	/* Task 1 Variable Table */
-.long	scEthernetXmit_FDT - taskTable + 0x03	/* Task 1 Function Descriptor Table & Flags */
-.long	0x00000000
-.long	0x00000000
-.long	scEthernetXmit_CSave - taskTable	/* Task 1 context save space */
-.long	0xf0000000
-
-
-.globl scEthernetRecv_TDT
-scEthernetRecv_TDT:	/* Task 0 Descriptor Table */
-.long	0xc4c50000	/* 0000:  LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */
-.long	0x84c5e000	/* 0004:  LCD: idx1 = var9 + var11; ; idx1 += inc0 */
-.long	0x10001f08	/* 0008:    DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long	0x10000380	/* 000C:    DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
-.long	0x00000f88	/* 0010:    DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */
-.long	0x81980000	/* 0014:  LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */
-.long	0x10000780	/* 0018:    DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
-.long	0x60000000	/* 001C:    DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long	0x010c504c	/* 0020:    DRD2B1: var4 = EU1(); EU1(var1,var12)  */
-.long	0x82180349	/* 0024:  LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */
-.long	0x81c68004	/* 0028:    LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */
-.long	0x70000000	/* 002C:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long	0x018c504e	/* 0030:      DRD2B1: var6 = EU1(); EU1(var1,var14)  */
-.long	0x70000000	/* 0034:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long	0x020c504f	/* 0038:      DRD2B1: var8 = EU1(); EU1(var1,var15)  */
-.long	0x00000b88	/* 003C:      DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */
-.long	0x8000d184	/* 0040:    LCDEXT: idx1 = 0xf0003184; ; */
-.long	0xc6990452	/* 0044:    LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */
-.long	0x81486010	/* 0048:    LCD: idx3 = var2 + var16; ; idx3 += inc2 */
-.long	0x006acf88	/* 004C:      DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */
-.long	0x8000d184	/* 0050:    LCDEXT: idx1 = 0xf0003184; ; */
-.long	0x86810492	/* 0054:    LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */
-.long	0x006acf88	/* 0058:      DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */
-.long	0x8000d184	/* 005C:    LCDEXT: idx1 = 0xf0003184; ; */
-.long	0x868184d2	/* 0060:    LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */
-.long	0x000acf88	/* 0064:      DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */
-.long	0xc318839b	/* 0068:    LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */
-.long	0x80190000	/* 006C:    LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
-.long	0x04008468	/* 0070:      DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */
-.long	0xc4038358	/* 0074:    LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */
-.long	0x81c50000	/* 0078:    LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */
-.long	0x1000cb18	/* 007C:      DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */
-.long	0x00000f18	/* 0080:      DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */
-.long	0xc4188364	/* 0084:    LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */
-.long	0x83990000	/* 0088:    LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */
-.long	0x10000c00	/* 008C:      DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */
-.long	0x0000c800	/* 0090:      DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */
-.long	0x81988000	/* 0094:    LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
-.long	0x10000788	/* 0098:      DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long	0x60000000	/* 009C:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long	0x080c504c	/* 00A0:      DRD2B1: idx0 = EU1(); EU1(var1,var12)  */
-.long	0x000001f8	/* 00A4(:0):    NOP */
-
-
-.globl scEthernetXmit_TDT
-scEthernetXmit_TDT:	/* Task 1 Descriptor Table */
-.long	0x80014800	/* 0000:  LCDEXT: idx0 = 0xf0004800; ; */
-.long	0x85c60004	/* 0004:  LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */
-.long	0x10002308	/* 0008:    DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long	0x10000f88	/* 000C:    DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long	0x00000380	/* 0010:    DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */
-.long	0x81980000	/* 0014:  LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */
-.long	0x10000780	/* 0018:    DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
-.long	0x60000000	/* 001C:    DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long	0x024c504d	/* 0020:    DRD2B1: var9 = EU1(); EU1(var1,var13)  */
-.long	0x84980309	/* 0024:  LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */
-.long	0xc0004003	/* 0028:    LCDEXT: idx1 = 0x00000003; ; */
-.long	0x81c60004	/* 002C:    LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */
-.long	0x70000000	/* 0030:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long	0x010c504e	/* 0034:      DRD2B1: var4 = EU1(); EU1(var1,var14)  */
-.long	0x70000000	/* 0038:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long	0x014c504f	/* 003C:      DRD2B1: var5 = EU1(); EU1(var1,var15)  */
-.long	0x70000000	/* 0040:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long	0x028c5050	/* 0044:      DRD2B1: var10 = EU1(); EU1(var1,var16)  */
-.long	0x70000000	/* 0048:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
-.long	0x018c5051	/* 004C:      DRD2B1: var6 = EU1(); EU1(var1,var17)  */
-.long	0x10000b90	/* 0050:      DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */
-.long	0x60000000	/* 0054:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long	0x01cc50a1	/* 0058:      DRD2B1: var7 = EU1(); EU1(var2,idx1)  */
-.long	0xc2988312	/* 005C:    LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */
-.long	0x83490000	/* 0060:    LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */
-.long	0x00001b10	/* 0064:      DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */
-.long	0x8000d1a4	/* 0068:    LCDEXT: idx1 = 0xf00031a4; ; */
-.long	0x8301031c	/* 006C:    LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */
-.long	0x008ac798	/* 0070:      DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */
-.long	0x8000d1a4	/* 0074:    LCDEXT: idx1 = 0xf00031a4; ; */
-.long	0xc1430000	/* 0078:    LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */
-.long	0x82998312	/* 007C:    LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */
-.long	0x088ac790	/* 0080:      DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */
-.long	0x81988000	/* 0084:    LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
-.long	0x60000100	/* 0088:      DRD2A: EU0=0 EU1=1 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long	0x0c4c5c4d	/* 008C:      DRD2B1: *idx1 = EU1(); EU1(*idx1,var13)  */
-.long	0xc21883ad	/* 0090:    LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */
-.long	0x80190000	/* 0094:    LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
-.long	0x04008460	/* 0098:      DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */
-.long	0xc4052305	/* 009C:    LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */
-.long	0x81c98000	/* 00A0:    LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */
-.long	0x1000c718	/* 00A4:      DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */
-.long	0x00000f18	/* 00A8:      DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */
-.long	0xc4188000	/* 00AC:    LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */
-.long	0x85190312	/* 00B0:    LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */
-.long	0x10000c00	/* 00B4:      DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */
-.long	0x1000c400	/* 00B8:      DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */
-.long	0x00008860	/* 00BC:      DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */
-.long	0x81988000	/* 00C0:    LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
-.long	0x10000788	/* 00C4:      DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
-.long	0x60000000	/* 00C8:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
-.long	0x080c504d	/* 00CC:      DRD2B1: idx0 = EU1(); EU1(var1,var13)  */
-.long	0x000001f8	/* 00D0(:0):    NOP */
-
-.align	8
-
-.globl scEthernetRecv_VarTab
-scEthernetRecv_VarTab:	/* Task 0 Variable Table */
-.long	0x00000000	/* var[0] */
-.long	0x00000000	/* var[1] */
-.long	0x00000000	/* var[2] */
-.long	0x00000000	/* var[3] */
-.long	0x00000000	/* var[4] */
-.long	0x00000000	/* var[5] */
-.long	0x00000000	/* var[6] */
-.long	0x00000000	/* var[7] */
-.long	0x00000000	/* var[8] */
-.long	0xf0004800	/* var[9] */
-.long	0x00000008	/* var[10] */
-.long	0x0000000c	/* var[11] */
-.long	0x80000000	/* var[12] */
-.long	0x00000000	/* var[13] */
-.long	0x10000000	/* var[14] */
-.long	0x20000000	/* var[15] */
-.long	0x000005e4	/* var[16] */
-.long	0x0000000e	/* var[17] */
-.long	0x000005e0	/* var[18] */
-.long	0x00000004	/* var[19] */
-.long	0x00000000	/* var[20] */
-.long	0x00000000	/* var[21] */
-.long	0x00000000	/* var[22] */
-.long	0x00000000	/* var[23] */
-.long	0x00000000	/* inc[0] */
-.long	0x60000000	/* inc[1] */
-.long	0x20000001	/* inc[2] */
-.long	0x80000000	/* inc[3] */
-.long	0x40000000	/* inc[4] */
-.long	0x00000000	/* inc[5] */
-.long	0x00000000	/* inc[6] */
-.long	0x00000000	/* inc[7] */
-
-.align	8
-
-.globl scEthernetXmit_VarTab
-scEthernetXmit_VarTab:	/* Task 1 Variable Table */
-.long	0x00000000	/* var[0] */
-.long	0x00000000	/* var[1] */
-.long	0x00000000	/* var[2] */
-.long	0x00000000	/* var[3] */
-.long	0x00000000	/* var[4] */
-.long	0x00000000	/* var[5] */
-.long	0x00000000	/* var[6] */
-.long	0x00000000	/* var[7] */
-.long	0x00000000	/* var[8] */
-.long	0x00000000	/* var[9] */
-.long	0x00000000	/* var[10] */
-.long	0xf0004800	/* var[11] */
-.long	0x00000000	/* var[12] */
-.long	0x80000000	/* var[13] */
-.long	0x10000000	/* var[14] */
-.long	0x08000000	/* var[15] */
-.long	0x20000000	/* var[16] */
-.long	0x0000ffff	/* var[17] */
-.long	0xffffffff	/* var[18] */
-.long	0x00000008	/* var[19] */
-.long	0x00000000	/* var[20] */
-.long	0x00000000	/* var[21] */
-.long	0x00000000	/* var[22] */
-.long	0x00000000	/* var[23] */
-.long	0x00000000	/* inc[0] */
-.long	0x60000000	/* inc[1] */
-.long	0x40000000	/* inc[2] */
-.long	0x4000ffff	/* inc[3] */
-.long	0xe0000001	/* inc[4] */
-.long	0x80000000	/* inc[5] */
-.long	0x00000000	/* inc[6] */
-.long	0x00000000	/* inc[7] */
-
-.align	8
-
-.globl scEthernetRecv_FDT
-scEthernetRecv_FDT:	/* Task 0 Function Descriptor Table */
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x05800000	/* and(), EU# 1 */
-.long	0x05400000	/* andn(), EU# 1 */
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-
-.align	8
-
-.globl scEthernetXmit_FDT
-scEthernetXmit_FDT:	/* Task 1 Function Descriptor Table */
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x05800000	/* and(), EU# 1 */
-.long	0x05400000	/* andn(), EU# 1 */
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-.long	0x00000000
-
-
-.align	8
-.globl scEthernetRecv_CSave
-scEthernetRecv_CSave:	/* Task 0 context save space */
-.space	256, 0x0
-
-
-.align	8
-.globl scEthernetXmit_CSave
-scEthernetXmit_CSave:	/* Task 1 context save space */
-.space	256, 0x0
-
-#endif /* CONFIG_MGT5100 */
diff --git a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S
index d140c7e989..00c23121ac 100644
--- a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S
+++ b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S
@@ -6,8 +6,6 @@
 
 #include <config.h>
 
-#if defined(CONFIG_MPC5200)
-
 /* sas/sccg, gas target */
 .section        smartdmaInitData,"aw",@progbits	/* Initialized data for task variables */
 .section        smartdmaTaskTable,"aw",@progbits	/* Task tables */
@@ -359,5 +357,3 @@ scEthernetRecv_CSave:	/* Task 0 context save space */
 .globl scEthernetXmit_CSave
 scEthernetXmit_CSave:	/* Task 1 context save space */
 .space  128, 0x0
-
-#endif /* CONFIG_MPC5200 */
diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c
index 225738a073..8268f8afe1 100644
--- a/cpu/mpc5xxx/pci_mpc5200.c
+++ b/cpu/mpc5xxx/pci_mpc5200.c
@@ -23,7 +23,7 @@
 
 #include <common.h>
 
-#if defined(CONFIG_PCI) && defined(CONFIG_MPC5200)
+#if defined(CONFIG_PCI)
 
 #include <asm/processor.h>
 #include <asm/io.h>
@@ -184,4 +184,4 @@ void pci_mpc5xxx_init (struct pci_controller *hose)
 
 	hose->last_busno = pci_hose_scan(hose);
 }
-#endif /* CONFIG_PCI && CONFIG_MPC5200 */
+#endif /* CONFIG_PCI */
diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c
index a8a384aa58..66759887c6 100644
--- a/cpu/mpc5xxx/serial.c
+++ b/cpu/mpc5xxx/serial.c
@@ -50,8 +50,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define PSC_BASE MPC5XXX_PSC2
 #elif CONFIG_PSC_CONSOLE == 3
 #define PSC_BASE MPC5XXX_PSC3
-#elif defined(CONFIG_MGT5100)
-#error CONFIG_PSC_CONSOLE must be in 1, 2 or 3
 #elif CONFIG_PSC_CONSOLE == 4
 #define PSC_BASE MPC5XXX_PSC4
 #elif CONFIG_PSC_CONSOLE == 5
@@ -73,8 +71,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define PSC_BASE2 MPC5XXX_PSC2
 #elif CONFIG_PSC_CONSOLE2 == 3
 #define PSC_BASE2 MPC5XXX_PSC3
-#elif defined(CONFIG_MGT5100)
-#error CONFIG_PSC_CONSOLE2 must be in 1, 2 or 3
 #elif CONFIG_PSC_CONSOLE2 == 4
 #define PSC_BASE2 MPC5XXX_PSC4
 #elif CONFIG_PSC_CONSOLE2 == 5
@@ -104,23 +100,14 @@ int serial_init (void)
 	psc->command = PSC_SEL_MODE_REG_1;
 
 	/* select clock sources */
-#if defined(CONFIG_MGT5100)
-	psc->psc_clock_select = 0xdd00;
-	baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32;
-#elif defined(CONFIG_MPC5200)
 	psc->psc_clock_select = 0;
 	baseclk = (gd->ipb_clk + 16) / 32;
-#endif
 
 	/* switch to UART mode */
 	psc->sicr = 0;
 
 	/* configure parity, bit length and so on */
-#if defined(CONFIG_MGT5100)
-	psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE;
-#elif defined(CONFIG_MPC5200)
 	psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
-#endif
 	psc->mode = PSC_MODE_ONE_STOP;
 
 	/* set up UART divisor */
@@ -246,11 +233,7 @@ void serial_setbrg(void)
 #endif
 	unsigned long baseclk, div;
 
-#if defined(CONFIG_MGT5100)
-	baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32;
-#elif defined(CONFIG_MPC5200)
 	baseclk = (gd->ipb_clk + 16) / 32;
-#endif
 
 	/* set up UART divisor */
 	div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S
index d499da5036..ba49944210 100644
--- a/cpu/mpc5xxx/start.S
+++ b/cpu/mpc5xxx/start.S
@@ -111,9 +111,6 @@ boot_warm:
 # if defined(CONFIG_SYS_RAMBOOT)
 #  error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT
 # endif /* CONFIG_SYS_RAMBOOT */
-# if defined(CONFIG_MGT5100)
-#  error CONFIG_SYS_LOWBOOT is incompatible with MGT5100
-# endif /* CONFIG_MGT5100 */
 	lis	r4, CONFIG_SYS_DEFAULT_MBAR@h
 	lis	r3,	START_REG(CONFIG_SYS_BOOTCS_START)@h
 	ori	r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
@@ -145,14 +142,9 @@ lowboot_reentry:
 #if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
 	lis	r3, CONFIG_SYS_MBAR@h
 	ori	r3, r3, CONFIG_SYS_MBAR@l
-#if defined(CONFIG_MPC5200)
 	/* MBAR is mirrored into the MBAR SPR */
 	mtspr	MBAR,r3
 	rlwinm	r3, r3, 16, 16, 31
-#endif
-#if defined(CONFIG_MGT5100)
-	rlwinm	r3, r3, 17, 15, 31
-#endif
 	lis	r4, CONFIG_SYS_DEFAULT_MBAR@h
 	stw	r3, 0(r4)
 #endif /* CONFIG_SYS_DEFAULT_MBAR */
diff --git a/cpu/mpc5xxx/usb_ohci.c b/cpu/mpc5xxx/usb_ohci.c
index 66a4af8d8e..7976e4df7d 100644
--- a/cpu/mpc5xxx/usb_ohci.c
+++ b/cpu/mpc5xxx/usb_ohci.c
@@ -76,13 +76,8 @@
 #define m16_swap(x) swap_16(x)
 #define m32_swap(x) swap_32(x)
 
-#ifdef CONFIG_MPC5200
 #define ohci_cpu_to_le16(x) (x)
 #define ohci_cpu_to_le32(x) (x)
-#else
-#define ohci_cpu_to_le16(x) swap_16(x)
-#define ohci_cpu_to_le32(x) swap_32(x)
-#endif
 
 /* global ohci_t */
 static ohci_t gohci;
@@ -803,9 +798,7 @@ static td_t * dl_reverse_done_list (ohci_t *ohci)
 				} else
 					td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);
 			}
-#ifdef CONFIG_MPC5200
 			td_list->hwNextTD = 0;
-#endif
 		}
 
 		td_list->next_dl_td = td_rev;
diff --git a/cpu/mpc5xxx/usb_ohci.h b/cpu/mpc5xxx/usb_ohci.h
index 6eedbdd1d9..629b529a69 100644
--- a/cpu/mpc5xxx/usb_ohci.h
+++ b/cpu/mpc5xxx/usb_ohci.h
@@ -127,13 +127,8 @@ typedef struct td td_t;
 #define NUM_INTS 32	/* part of the OHCI standard */
 struct ohci_hcca {
 	__u32	int_table[NUM_INTS];	/* Interrupt ED table */
-#if defined(CONFIG_MPC5200)
 	__u16	pad1;			/* set to 0 on each frame_no change */
 	__u16	frame_no;		/* current frame number */
-#else
-	__u16	frame_no;		/* current frame number */
-	__u16	pad1;			/* set to 0 on each frame_no change */
-#endif
 	__u32	done_head;		/* info returned for an interrupt */
 	u8		reserved_for_hc[116];
 } __attribute__((aligned(256)));
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index 0fe30410a6..7a89b5692c 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@ -385,34 +385,38 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
 		} while ((*fn->init) (cookie));
 
 		/* Load the data */
-		while (bytecount < bsize) {
-
-			/* Xilinx detects an error if INIT goes low (active)
-			   while DONE is low (inactive) */
-			if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
-				puts ("** CRC error during FPGA load.\n");
-				return (FPGA_FAIL);
-			}
-			val = data [bytecount ++];
-			i = 8;
-			do {
-				/* Deassert the clock */
-				(*fn->clk) (FALSE, TRUE, cookie);
-				CONFIG_FPGA_DELAY ();
-				/* Write data */
-				(*fn->wr) ((val & 0x80), TRUE, cookie);
-				CONFIG_FPGA_DELAY ();
-				/* Assert the clock */
-				(*fn->clk) (TRUE, TRUE, cookie);
-				CONFIG_FPGA_DELAY ();
-				val <<= 1;
-				i --;
-			} while (i > 0);
+		if(*fn->bwr)
+			(*fn->bwr) (data, bsize, TRUE, cookie);
+		else {
+			while (bytecount < bsize) {
+
+				/* Xilinx detects an error if INIT goes low (active)
+				   while DONE is low (inactive) */
+				if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
+					puts ("** CRC error during FPGA load.\n");
+					return (FPGA_FAIL);
+				}
+				val = data [bytecount ++];
+				i = 8;
+				do {
+					/* Deassert the clock */
+					(*fn->clk) (FALSE, TRUE, cookie);
+					CONFIG_FPGA_DELAY ();
+					/* Write data */
+					(*fn->wr) ((val & 0x80), TRUE, cookie);
+					CONFIG_FPGA_DELAY ();
+					/* Assert the clock */
+					(*fn->clk) (TRUE, TRUE, cookie);
+					CONFIG_FPGA_DELAY ();
+					val <<= 1;
+					i --;
+				} while (i > 0);
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-			if (bytecount % (bsize / 40) == 0)
-				putc ('.');		/* let them know we are alive */
+				if (bytecount % (bsize / 40) == 0)
+					putc ('.');		/* let them know we are alive */
 #endif
+			}
 		}
 
 		CONFIG_FPGA_DELAY ();
diff --git a/drivers/input/ps2ser.c b/drivers/input/ps2ser.c
index 1b20a76c4c..8d0b6d6042 100644
--- a/drivers/input/ps2ser.c
+++ b/drivers/input/ps2ser.c
@@ -36,8 +36,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define PSC_BASE MPC5XXX_PSC2
 #elif CONFIG_PS2SERIAL == 3
 #define PSC_BASE MPC5XXX_PSC3
-#elif defined(CONFIG_MGT5100)
-#error CONFIG_PS2SERIAL must be in 1, 2 or 3
 #elif CONFIG_PS2SERIAL == 4
 #define PSC_BASE MPC5XXX_PSC4
 #elif CONFIG_PS2SERIAL == 5
@@ -87,23 +85,14 @@ int ps2ser_init(void)
 	psc->command = PSC_SEL_MODE_REG_1;
 
 	/* select clock sources */
-#if defined(CONFIG_MGT5100)
-	psc->psc_clock_select = 0xdd00;
-	baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32;
-#elif defined(CONFIG_MPC5200)
 	psc->psc_clock_select = 0;
 	baseclk = (gd->ipb_clk + 16) / 32;
-#endif
 
 	/* switch to UART mode */
 	psc->sicr = 0;
 
 	/* configure parity, bit length and so on */
-#if defined(CONFIG_MGT5100)
-	psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE;
-#elif defined(CONFIG_MPC5200)
 	psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
-#endif
 	psc->mode = PSC_MODE_ONE_STOP;
 
 	/* set up UART divisor */
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index cd1a86ebad..d0240f55d4 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -605,6 +605,63 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
 	return retcode;
 }
 
+static int use_flash_status_poll(flash_info_t *info)
+{
+#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL
+	if (info->vendor == CFI_CMDSET_AMD_EXTENDED ||
+	    info->vendor == CFI_CMDSET_AMD_STANDARD)
+		return 1;
+#endif
+	return 0;
+}
+
+static int flash_status_poll(flash_info_t *info, void *src, void *dst,
+			     ulong tout, char *prompt)
+{
+#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL
+	ulong start;
+	int ready;
+
+#if CONFIG_SYS_HZ != 1000
+	if ((ulong)CONFIG_SYS_HZ > 100000)
+		tout *= (ulong)CONFIG_SYS_HZ / 1000;  /* for a big HZ, avoid overflow */
+	else
+		tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
+#endif
+
+	/* Wait for command completion */
+	start = get_timer(0);
+	while (1) {
+		switch (info->portwidth) {
+		case FLASH_CFI_8BIT:
+			ready = flash_read8(dst) == flash_read8(src);
+			break;
+		case FLASH_CFI_16BIT:
+			ready = flash_read16(dst) == flash_read16(src);
+			break;
+		case FLASH_CFI_32BIT:
+			ready = flash_read32(dst) == flash_read32(src);
+			break;
+		case FLASH_CFI_64BIT:
+			ready = flash_read64(dst) == flash_read64(src);
+			break;
+		default:
+			ready = 0;
+			break;
+		}
+		if (ready)
+			break;
+		if (get_timer(start) > tout) {
+			printf("Flash %s timeout at address %lx data %lx\n",
+			       prompt, (ulong)dst, (ulong)flash_read8(dst));
+			return ERR_TIMOUT;
+		}
+		udelay(1);		/* also triggers watchdog */
+	}
+#endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */
+	return ERR_OK;
+}
+
 /*-----------------------------------------------------------------------
  */
 static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
@@ -752,7 +809,12 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest,
 	if (!sect_found)
 		sect = find_sector (info, dest);
 
-	return flash_full_status_check (info, sect, info->write_tout, "write");
+	if (use_flash_status_poll(info))
+		return flash_status_poll(info, &cword, dstaddr,
+					 info->write_tout, "write");
+	else
+		return flash_full_status_check(info, sect,
+					       info->write_tout, "write");
 }
 
 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
@@ -914,9 +976,15 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
 		}
 
 		flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
-		retcode = flash_full_status_check (info, sector,
-						   info->buffer_write_tout,
-						   "buffer write");
+		if (use_flash_status_poll(info))
+			retcode = flash_status_poll(info, src - (1 << shift),
+						    dst - (1 << shift),
+						    info->buffer_write_tout,
+						    "buffer write");
+		else
+			retcode = flash_full_status_check(info, sector,
+							  info->buffer_write_tout,
+							  "buffer write");
 		break;
 
 	default:
@@ -938,6 +1006,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	int rcode = 0;
 	int prot;
 	flash_sect_t sect;
+	int st;
 
 	if (info->flash_id != FLASH_MAN_CFI) {
 		puts ("Can't erase unknown flash type - aborted\n");
@@ -1001,10 +1070,20 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 				break;
 			}
 
-			if (flash_full_status_check
-			    (info, sect, info->erase_blk_tout, "erase")) {
+			if (use_flash_status_poll(info)) {
+				cfiword_t cword = (cfiword_t)0xffffffffffffffffULL;
+				void *dest;
+				dest = flash_map(info, sect, 0);
+				st = flash_status_poll(info, &cword, dest,
+						       info->erase_blk_tout, "erase");
+				flash_unmap(info, sect, 0, dest);
+			} else
+				st = flash_full_status_check(info, sect,
+							     info->erase_blk_tout,
+							     "erase");
+			if (st)
 				rcode = 1;
-			} else if (flash_verbose)
+			else if (flash_verbose)
 				putc ('.');
 		}
 	}
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 40002be417..d5eb54ad84 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -31,6 +31,209 @@
 
 #include <nand.h>
 
+#ifdef CONFIG_ATMEL_NAND_HWECC
+
+/* Register access macros */
+#define ecc_readl(add, reg)				\
+	readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
+#define ecc_writel(add, reg, value)			\
+	writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
+
+#include "atmel_nand_ecc.h"	/* Hardware ECC registers */
+
+/* oob layout for large page size
+ * bad block info is on bytes 0 and 1
+ * the bytes have to be consecutives to avoid
+ * several NAND_CMD_RNDOUT during read
+ */
+static struct nand_ecclayout atmel_oobinfo_large = {
+	.eccbytes = 4,
+	.eccpos = {60, 61, 62, 63},
+	.oobfree = {
+		{2, 58}
+	},
+};
+
+/* oob layout for small page size
+ * bad block info is on bytes 4 and 5
+ * the bytes have to be consecutives to avoid
+ * several NAND_CMD_RNDOUT during read
+ */
+static struct nand_ecclayout atmel_oobinfo_small = {
+	.eccbytes = 4,
+	.eccpos = {0, 1, 2, 3},
+	.oobfree = {
+		{6, 10}
+	},
+};
+
+/*
+ * Calculate HW ECC
+ *
+ * function called after a write
+ *
+ * mtd:        MTD block structure
+ * dat:        raw data (unused)
+ * ecc_code:   buffer for ECC
+ */
+static int atmel_nand_calculate(struct mtd_info *mtd,
+		const u_char *dat, unsigned char *ecc_code)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+	unsigned int ecc_value;
+
+	/* get the first 2 ECC bytes */
+	ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
+
+	ecc_code[0] = ecc_value & 0xFF;
+	ecc_code[1] = (ecc_value >> 8) & 0xFF;
+
+	/* get the last 2 ECC bytes */
+	ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
+
+	ecc_code[2] = ecc_value & 0xFF;
+	ecc_code[3] = (ecc_value >> 8) & 0xFF;
+
+	return 0;
+}
+
+/*
+ * HW ECC read page function
+ *
+ * mtd:        mtd info structure
+ * chip:       nand chip info structure
+ * buf:        buffer to store read data
+ */
+static int atmel_nand_read_page(struct mtd_info *mtd,
+		struct nand_chip *chip, uint8_t *buf, int page)
+{
+	int eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	uint32_t *eccpos = chip->ecc.layout->eccpos;
+	uint8_t *p = buf;
+	uint8_t *oob = chip->oob_poi;
+	uint8_t *ecc_pos;
+	int stat;
+
+	/* read the page */
+	chip->read_buf(mtd, p, eccsize);
+
+	/* move to ECC position if needed */
+	if (eccpos[0] != 0) {
+		/* This only works on large pages
+		 * because the ECC controller waits for
+		 * NAND_CMD_RNDOUTSTART after the
+		 * NAND_CMD_RNDOUT.
+		 * anyway, for small pages, the eccpos[0] == 0
+		 */
+		chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
+				mtd->writesize + eccpos[0], -1);
+	}
+
+	/* the ECC controller needs to read the ECC just after the data */
+	ecc_pos = oob + eccpos[0];
+	chip->read_buf(mtd, ecc_pos, eccbytes);
+
+	/* check if there's an error */
+	stat = chip->ecc.correct(mtd, p, oob, NULL);
+
+	if (stat < 0)
+		mtd->ecc_stats.failed++;
+	else
+		mtd->ecc_stats.corrected += stat;
+
+	/* get back to oob start (end of page) */
+	chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
+
+	/* read the oob */
+	chip->read_buf(mtd, oob, mtd->oobsize);
+
+	return 0;
+}
+
+/*
+ * HW ECC Correction
+ *
+ * function called after a read
+ *
+ * mtd:        MTD block structure
+ * dat:        raw data read from the chip
+ * read_ecc:   ECC from the chip (unused)
+ * isnull:     unused
+ *
+ * Detect and correct a 1 bit error for a page
+ */
+static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
+		u_char *read_ecc, u_char *isnull)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+	unsigned int ecc_status, ecc_parity, ecc_mode;
+	unsigned int ecc_word, ecc_bit;
+
+	/* get the status from the Status Register */
+	ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
+
+	/* if there's no error */
+	if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
+		return 0;
+
+	/* get error bit offset (4 bits) */
+	ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
+	/* get word address (12 bits) */
+	ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
+	ecc_word >>= 4;
+
+	/* if there are multiple errors */
+	if (ecc_status & ATMEL_ECC_MULERR) {
+		/* check if it is a freshly erased block
+		 * (filled with 0xff) */
+		if ((ecc_bit == ATMEL_ECC_BITADDR)
+				&& (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
+			/* the block has just been erased, return OK */
+			return 0;
+		}
+		/* it doesn't seems to be a freshly
+		 * erased block.
+		 * We can't correct so many errors */
+		printk(KERN_WARNING "atmel_nand : multiple errors detected."
+				" Unable to correct.\n");
+		return -EIO;
+	}
+
+	/* if there's a single bit error : we can correct it */
+	if (ecc_status & ATMEL_ECC_ECCERR) {
+		/* there's nothing much to do here.
+		 * the bit error is on the ECC itself.
+		 */
+		printk(KERN_WARNING "atmel_nand : one bit error on ECC code."
+				" Nothing to correct\n");
+		return 0;
+	}
+
+	printk(KERN_WARNING "atmel_nand : one bit error on data."
+			" (word offset in the page :"
+			" 0x%x bit offset : 0x%x)\n",
+			ecc_word, ecc_bit);
+	/* correct the error */
+	if (nand_chip->options & NAND_BUSWIDTH_16) {
+		/* 16 bits words */
+		((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
+	} else {
+		/* 8 bits words */
+		dat[ecc_word] ^= (1 << ecc_bit);
+	}
+	printk(KERN_WARNING "atmel_nand : error corrected\n");
+	return 1;
+}
+
+/*
+ * Enable HW ECC : unused on most chips
+ */
+static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
+{
+}
+#endif
+
 static void at91_nand_hwcontrol(struct mtd_info *mtd,
 					 int cmd, unsigned int ctrl)
 {
@@ -64,6 +267,11 @@ static int at91_nand_ready(struct mtd_info *mtd)
 
 int board_nand_init(struct nand_chip *nand)
 {
+#ifdef CONFIG_ATMEL_NAND_HWECC
+	static int chip_nr = 0;
+	struct mtd_info *mtd;
+#endif
+
 	nand->ecc.mode = NAND_ECC_SOFT;
 #ifdef CONFIG_SYS_NAND_DBW_16
 	nand->options = NAND_BUSWIDTH_16;
@@ -74,5 +282,62 @@ int board_nand_init(struct nand_chip *nand)
 #endif
 	nand->chip_delay = 20;
 
+#ifdef CONFIG_ATMEL_NAND_HWECC
+	nand->ecc.mode = NAND_ECC_HW;
+	nand->ecc.calculate = atmel_nand_calculate;
+	nand->ecc.correct = atmel_nand_correct;
+	nand->ecc.hwctl = atmel_nand_hwctl;
+	nand->ecc.read_page = atmel_nand_read_page;
+	nand->ecc.bytes = 4;
+#endif
+
+#ifdef CONFIG_ATMEL_NAND_HWECC
+	mtd = &nand_info[chip_nr++];
+	mtd->priv = nand;
+
+	/* Detect NAND chips */
+	if (nand_scan_ident(mtd, 1)) {
+		printk(KERN_WARNING "NAND Flash not found !\n");
+		return -ENXIO;
+	}
+
+	if (nand->ecc.mode == NAND_ECC_HW) {
+		/* ECC is calculated for the whole page (1 step) */
+		nand->ecc.size = mtd->writesize;
+
+		/* set ECC page size and oob layout */
+		switch (mtd->writesize) {
+		case 512:
+			nand->ecc.layout = &atmel_oobinfo_small;
+			ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_528);
+			break;
+		case 1024:
+			nand->ecc.layout = &atmel_oobinfo_large;
+			ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_1056);
+			break;
+		case 2048:
+			nand->ecc.layout = &atmel_oobinfo_large;
+			ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_2112);
+			break;
+		case 4096:
+			nand->ecc.layout = &atmel_oobinfo_large;
+			ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_4224);
+			break;
+		default:
+			/* page size not handled by HW ECC */
+			/* switching back to soft ECC */
+			nand->ecc.mode = NAND_ECC_SOFT;
+			nand->ecc.calculate = NULL;
+			nand->ecc.correct = NULL;
+			nand->ecc.hwctl = NULL;
+			nand->ecc.read_page = NULL;
+			nand->ecc.postpad = 0;
+			nand->ecc.prepad = 0;
+			nand->ecc.bytes = 0;
+			break;
+		}
+	}
+#endif
+
 	return 0;
 }
diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h
new file mode 100644
index 0000000000..1ee7f993db
--- /dev/null
+++ b/drivers/mtd/nand/atmel_nand_ecc.h
@@ -0,0 +1,36 @@
+/*
+ * Error Corrected Code Controller (ECC) - System peripherals regsters.
+ * Based on AT91SAM9260 datasheet revision B.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef ATMEL_NAND_ECC_H
+#define ATMEL_NAND_ECC_H
+
+#define ATMEL_ECC_CR		0x00			/* Control register */
+#define		ATMEL_ECC_RST		(1 << 0)		/* Reset parity */
+
+#define ATMEL_ECC_MR		0x04			/* Mode register */
+#define		ATMEL_ECC_PAGESIZE	(3 << 0)		/* Page Size */
+#define			ATMEL_ECC_PAGESIZE_528		(0)
+#define			ATMEL_ECC_PAGESIZE_1056		(1)
+#define			ATMEL_ECC_PAGESIZE_2112		(2)
+#define			ATMEL_ECC_PAGESIZE_4224		(3)
+
+#define ATMEL_ECC_SR		0x08			/* Status register */
+#define		ATMEL_ECC_RECERR		(1 << 0)		/* Recoverable Error */
+#define		ATMEL_ECC_ECCERR		(1 << 1)		/* ECC Single Bit Error */
+#define		ATMEL_ECC_MULERR		(1 << 2)		/* Multiple Errors */
+
+#define ATMEL_ECC_PR		0x0c			/* Parity register */
+#define		ATMEL_ECC_BITADDR	(0xf << 0)		/* Bit Error Address */
+#define		ATMEL_ECC_WORDADDR	(0xfff << 4)		/* Word Error Address */
+
+#define ATMEL_ECC_NPR		0x10			/* NParity register */
+#define		ATMEL_ECC_NPARITY	(0xffff << 0)		/* NParity */
+
+#endif
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index bfc2acf59e..4ca738e451 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -57,8 +57,6 @@
 #define ECC_STATE_ERR_CORR_COMP_P	0x2
 #define ECC_STATE_ERR_CORR_COMP_N	0x3
 
-static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE;
-
 /*
  * Exploit the little endianness of the ARM to do multi-byte transfers
  * per device read. This can perform over twice as quickly as individual
@@ -93,7 +91,7 @@ static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 
 	/* copy aligned data */
 	while (len >= 4) {
-		*(u32 *)buf = readl(nand);
+		*(u32 *)buf = __raw_readl(nand);
 		buf += 4;
 		len -= 4;
 	}
@@ -138,7 +136,7 @@ static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 
 	/* copy aligned data */
 	while (len >= 4) {
-		writel(*(u32 *)buf, nand);
+		__raw_writel(*(u32 *)buf, nand);
 		buf += 4;
 		len -= 4;
 	}
@@ -156,7 +154,8 @@ static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 	}
 }
 
-static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
+		unsigned int ctrl)
 {
 	struct		nand_chip *this = mtd->priv;
 	u_int32_t	IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
@@ -164,9 +163,9 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int c
 	if (ctrl & NAND_CTRL_CHANGE) {
 		IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
 
-		if ( ctrl & NAND_CLE )
+		if (ctrl & NAND_CLE)
 			IO_ADDR_W |= MASK_CLE;
-		if ( ctrl & NAND_ALE )
+		if (ctrl & NAND_ALE)
 			IO_ADDR_W |= MASK_ALE;
 		this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
 	}
@@ -181,24 +180,26 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
 {
 	u_int32_t	val;
 
-	(void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2]));
+	(void)__raw_readl(&(davinci_emif_regs->nandfecc[
+				CONFIG_SYS_NAND_CS - 2]));
 
-	val = readl(&emif_regs->NANDFCR);
+	val = __raw_readl(&davinci_emif_regs->nandfcr);
 	val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
 	val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
-	writel(val, &emif_regs->NANDFCR);
+	__raw_writel(val, &davinci_emif_regs->nandfcr);
 }
 
 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
 {
 	u_int32_t	ecc = 0;
 
-	ecc = readl(&(emif_regs->NANDFECC[region - 1]));
+	ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1]));
 
-	return(ecc);
+	return ecc;
 }
 
-static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
+static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+		u_char *ecc_code)
 {
 	u_int32_t		tmp;
 	const int region = 1;
@@ -232,7 +233,8 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u
 	return 0;
 }
 
-static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
+static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
+		u_char *read_ecc, u_char *calc_ecc)
 {
 	struct nand_chip *this = mtd->priv;
 	u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
@@ -268,7 +270,7 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *
 			return -1;
 		}
 	}
-	return(0);
+	return 0;
 }
 #endif /* CONFIG_SYS_NAND_HW_ECC */
 
@@ -315,15 +317,15 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
 		 * Start a new ECC calculation for reading or writing 512 bytes
 		 * of data.
 		 */
-		val = readl(&emif_regs->NANDFCR);
+		val = __raw_readl(&davinci_emif_regs->nandfcr);
 		val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
 		val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
 		val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
 		val |= DAVINCI_NANDFCR_4BIT_ECC_START;
-		writel(val, &emif_regs->NANDFCR);
+		__raw_writel(val, &davinci_emif_regs->nandfcr);
 		break;
 	case NAND_ECC_READSYN:
-		val = emif_regs->NAND4BITECC1;
+		val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
 		break;
 	default:
 		break;
@@ -332,10 +334,12 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
 
 static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
 {
-	ecc[0] = emif_regs->NAND4BITECC1 & NAND_4BITECC_MASK;
-	ecc[1] = emif_regs->NAND4BITECC2 & NAND_4BITECC_MASK;
-	ecc[2] = emif_regs->NAND4BITECC3 & NAND_4BITECC_MASK;
-	ecc[3] = emif_regs->NAND4BITECC4 & NAND_4BITECC_MASK;
+	int i;
+
+	for (i = 0; i < 4; i++) {
+		ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
+			NAND_4BITECC_MASK;
+	}
 
 	return 0;
 }
@@ -418,32 +422,36 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
 	 */
 
 	/*Take 2 bits from 8th byte and 8 bits from 9th byte */
-	writel(((ecc16[4]) >> 6) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
+	__raw_writel(((ecc16[4]) >> 6) & 0x3FF,
+			&davinci_emif_regs->nand4biteccload);
 
 	/* Take 4 bits from 7th byte and 6 bits from 8th byte */
-	writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
-	       &emif_regs->NAND4BITECCLOAD);
+	__raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
+			&davinci_emif_regs->nand4biteccload);
 
 	/* Take 6 bits from 6th byte and 4 bits from 7th byte */
-	writel((ecc16[3] >> 2) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
+	__raw_writel((ecc16[3] >> 2) & 0x3FF,
+			&davinci_emif_regs->nand4biteccload);
 
 	/* Take 8 bits from 5th byte and 2 bits from 6th byte */
-	writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
-	       &emif_regs->NAND4BITECCLOAD);
+	__raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
+			&davinci_emif_regs->nand4biteccload);
 
 	/*Take 2 bits from 3rd byte and 8 bits from 4th byte */
-	writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
-	       &emif_regs->NAND4BITECCLOAD);
+	__raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
+			&davinci_emif_regs->nand4biteccload);
 
 	/* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
-	writel(((ecc16[1]) >> 4) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
+	__raw_writel(((ecc16[1]) >> 4) & 0x3FF,
+			&davinci_emif_regs->nand4biteccload);
 
 	/* Take 6 bits from 1st byte and 4 bits from 2nd byte */
-	writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
-	       &emif_regs->NAND4BITECCLOAD);
+	__raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
+			&davinci_emif_regs->nand4biteccload);
 
 	/* Take 10 bits from 0th and 1st bytes */
-	writel((ecc16[0]) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
+	__raw_writel((ecc16[0]) & 0x3FF,
+			&davinci_emif_regs->nand4biteccload);
 
 	/*
 	 * Perform a dummy read to the EMIF Revision Code and Status register.
@@ -451,7 +459,7 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
 	 * writing the ECC values in previous step.
 	 */
 
-	val = emif_regs->NANDFSR;
+	val = __raw_readl(&davinci_emif_regs->nandfsr);
 
 	/*
 	 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
@@ -467,13 +475,13 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
 	 * Clear any previous address calculation by doing a dummy read of an
 	 * error address register.
 	 */
-	val = emif_regs->NANDERRADD1;
+	val = __raw_readl(&davinci_emif_regs->nanderradd1);
 
 	/*
 	 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
 	 * register to 1.
 	 */
-	emif_regs->NANDFCR |= 1 << 13;
+	__raw_writel(1 << 13, &davinci_emif_regs->nandfcr);
 
 	/*
 	 * Wait for the corr_state field (bits 8 to 11)in the
@@ -481,12 +489,12 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
 	 */
 	i = NAND_TIMEOUT;
 	do {
-		val = emif_regs->NANDFSR;
+		val = __raw_readl(&davinci_emif_regs->nandfsr);
 		val &= 0xc00;
 		i--;
 	} while ((i > 0) && val);
 
-	iserror = emif_regs->NANDFSR;
+	iserror = __raw_readl(&davinci_emif_regs->nandfsr);
 	iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
 	iserror = iserror >> 8;
 
@@ -501,32 +509,33 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
 	 */
 
 	if (iserror == ECC_STATE_NO_ERR) {
-		val = emif_regs->NANDERRVAL1;
+		val = __raw_readl(&davinci_emif_regs->nanderrval1);
 		return 0;
 	} else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
-		val = emif_regs->NANDERRVAL1;
+		val = __raw_readl(&davinci_emif_regs->nanderrval1);
 		return -1;
 	}
 
-	numerrors = ((emif_regs->NANDFSR >> 16) & 0x3) + 1;
+	numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
+			& 0x3) + 1;
 
 	/* Read the error address, error value and correct */
 	for (i = 0; i < numerrors; i++) {
 		if (i > 1) {
 			erroraddress =
-			    ((emif_regs->NANDERRADD2 >>
+			    ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
 			      (16 * (i & 1))) & 0x3FF);
 			erroraddress = ((512 + 7) - erroraddress);
 			errorvalue =
-			    ((emif_regs->NANDERRVAL2 >>
+			    ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
 			      (16 * (i & 1))) & 0xFF);
 		} else {
 			erroraddress =
-			    ((emif_regs->NANDERRADD1 >>
+			    ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
 			      (16 * (i & 1))) & 0x3FF);
 			erroraddress = ((512 + 7) - erroraddress);
 			errorvalue =
-			    ((emif_regs->NANDERRVAL1 >>
+			    ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
 			      (16 * (i & 1))) & 0xFF);
 		}
 		/* xor the corrupt data with error value */
@@ -540,7 +549,7 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
 
 static int nand_davinci_dev_ready(struct mtd_info *mtd)
 {
-	return emif_regs->NANDFSR & 0x1;
+	return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
 }
 
 static void nand_flash_init(void)
@@ -561,21 +570,22 @@ static void nand_flash_init(void)
 	 *                                                                  *
 	 *------------------------------------------------------------------*/
 	 acfg1 = 0
-		| (0 << 31 )	/* selectStrobe */
-		| (0 << 30 )	/* extWait */
-		| (1 << 26 )	/* writeSetup	10 ns */
-		| (3 << 20 )	/* writeStrobe	40 ns */
-		| (1 << 17 )	/* writeHold	10 ns */
-		| (1 << 13 )	/* readSetup	10 ns */
-		| (5 << 7 )	/* readStrobe	60 ns */
-		| (1 << 4 )	/* readHold	10 ns */
-		| (3 << 2 )	/* turnAround	?? ns */
-		| (0 << 0 )	/* asyncSize	8-bit bus */
+		| (0 << 31)	/* selectStrobe */
+		| (0 << 30)	/* extWait */
+		| (1 << 26)	/* writeSetup	10 ns */
+		| (3 << 20)	/* writeStrobe	40 ns */
+		| (1 << 17)	/* writeHold	10 ns */
+		| (1 << 13)	/* readSetup	10 ns */
+		| (5 << 7)	/* readStrobe	60 ns */
+		| (1 << 4)	/* readHold	10 ns */
+		| (3 << 2)	/* turnAround	?? ns */
+		| (0 << 0)	/* asyncSize	8-bit bus */
 		;
 
-	emif_regs->AB1CR = acfg1; /* CS2 */
+	__raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
 
-	emif_regs->NANDFCR = 0x00000101; /* NAND flash on CS2 */
+	/* NAND flash on CS2 */
+	__raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
 #endif
 }
 
diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c
index 1876b7684b..c2b1bbdc7b 100644
--- a/drivers/net/mpc5xxx_fec.c
+++ b/drivers/net/mpc5xxx_fec.c
@@ -336,13 +336,11 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 	 */
 	fec->eth->xmit_fsm = 0x03000000;
 
-#if defined(CONFIG_MPC5200)
 	/*
-	 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
+	 * Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't
 	 * work w/ the current receive task.
 	 */
 	 sdma->PtdCntrl |= 0x00000001;
-#endif
 
 	/*
 	 * Set priority of different initiators
@@ -579,9 +577,7 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
 /********************************************************************/
 static void mpc5xxx_fec_halt(struct eth_device *dev)
 {
-#if defined(CONFIG_MPC5200)
 	struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
-#endif
 	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
 	int counter = 0xffff;
 
@@ -611,13 +607,11 @@ static void mpc5xxx_fec_halt(struct eth_device *dev)
 	SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
 	SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
 
-#if defined(CONFIG_MPC5200)
 	/*
-	 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
+	 * Turn on COMM bus prefetch in the MPC5200 BestComm after we're
 	 * done. It doesn't work w/ the current receive task.
 	 */
 	 sdma->PtdCntrl &= ~0x00000001;
-#endif
 
 	/*
 	 * Disable the Ethernet Controller
diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c
index 0b531402e4..d93b24b897 100644
--- a/drivers/serial/mcfuart.c
+++ b/drivers/serial/mcfuart.c
@@ -34,7 +34,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern void uart_port_conf(void);
+extern void uart_port_conf(int port);
 
 int serial_init(void)
 {
@@ -43,7 +43,7 @@ int serial_init(void)
 
 	uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
 
-	uart_port_conf();
+	uart_port_conf(CONFIG_SYS_UART_PORT);
 
 	/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
 	uart->ucr = UART_UCR_RESET_RX;
diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h
index aa57703c68..b48ec17e97 100644
--- a/include/asm-arm/arch-davinci/emif_defs.h
+++ b/include/asm-arm/arch-davinci/emif_defs.h
@@ -24,47 +24,42 @@
 
 #include <asm/arch/hardware.h>
 
-typedef struct davinci_emif_regs {
-	dv_reg		ERCSR;
-	dv_reg		AWCCR;
-	dv_reg		SDBCR;
-	dv_reg		SDRCR;
-	dv_reg		AB1CR;
-	dv_reg		AB2CR;
-	dv_reg		AB3CR;
-	dv_reg		AB4CR;
-	dv_reg		SDTIMR;
-	dv_reg		DDRSR;
-	dv_reg		DDRPHYCR;
-	dv_reg		DDRPHYSR;
-	dv_reg		TOTAR;
-	dv_reg		TOTACTR;
-	dv_reg		DDRPHYID_REV;
-	dv_reg		SDSRETR;
-	dv_reg		EIRR;
-	dv_reg		EIMR;
-	dv_reg		EIMSR;
-	dv_reg		EIMCR;
-	dv_reg		IOCTRLR;
-	dv_reg		IOSTATR;
-	u_int8_t	RSVD0[8];
-	dv_reg		NANDFCR;
-	dv_reg		NANDFSR;
-	u_int8_t	RSVD1[8];
-	dv_reg		NANDFECC[4];
-	u_int8_t	RSVD2[60];
-	dv_reg		NAND4BITECCLOAD;
-	dv_reg		NAND4BITECC1;
-	dv_reg		NAND4BITECC2;
-	dv_reg		NAND4BITECC3;
-	dv_reg		NAND4BITECC4;
-	dv_reg		NANDERRADD1;
-	dv_reg		NANDERRADD2;
-	dv_reg		NANDERRVAL1;
-	dv_reg		NANDERRVAL2;
-} emif_registers;
-
-typedef emif_registers	*emifregs;
+struct davinci_emif_regs {
+	u_int32_t	ercsr;
+	u_int32_t	awccr;
+	u_int32_t	sdbcr;
+	u_int32_t	sdrcr;
+	u_int32_t	ab1cr;
+	u_int32_t	ab2cr;
+	u_int32_t	ab3cr;
+	u_int32_t	ab4cr;
+	u_int32_t	sdtimr;
+	u_int32_t	ddrsr;
+	u_int32_t	ddrphycr;
+	u_int32_t	ddrphysr;
+	u_int32_t	totar;
+	u_int32_t	totactr;
+	u_int32_t	ddrphyid_rev;
+	u_int32_t	sdsretr;
+	u_int32_t	eirr;
+	u_int32_t	eimr;
+	u_int32_t	eimsr;
+	u_int32_t	eimcr;
+	u_int32_t	ioctrlr;
+	u_int32_t	iostatr;
+	u_int8_t	rsvd0[8];
+	u_int32_t	nandfcr;
+	u_int32_t	nandfsr;
+	u_int8_t	rsvd1[8];
+	u_int32_t	nandfecc[4];
+	u_int8_t	rsvd2[60];
+	u_int32_t	nand4biteccload;
+	u_int32_t	nand4bitecc[4];
+	u_int32_t	nanderradd1;
+	u_int32_t	nanderradd2;
+	u_int32_t	nanderrval1;
+	u_int32_t	nanderrval2;
+};
 
 #define davinci_emif_regs \
 	((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
diff --git a/include/asm-m68k/cache.h b/include/asm-m68k/cache.h
new file mode 100644
index 0000000000..7c84e48471
--- /dev/null
+++ b/include/asm-m68k/cache.h
@@ -0,0 +1,210 @@
+/*
+ * ColdFire cache
+ *
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \
+    defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x)
+#define CONFIG_CF_V2
+#endif
+
+#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x)
+#define CONFIG_CF_V3
+#endif
+
+#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x)
+#define CONFIG_CF_V4
+#if defined(CONFIG_MCF5441x)
+#define CONFIG_CF_V4E		/* Four Extra ACRn */
+#endif
+#endif
+
+/* ***** CACR ***** */
+/* V2 Core */
+#ifdef CONFIG_CF_V2
+
+#define CF_CACR_CENB		(1 << 31)
+#define CF_CACR_CPD		(1 << 28)
+#define CF_CACR_CFRZ		(1 << 27)
+#define CF_CACR_CEIB		(1 << 10)
+#define CF_CACR_DCM		(1 << 9)
+#define CF_CACR_DBWE		(1 << 8)
+
+#if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253)
+#define CF_CACR_DWP		(1 << 6)
+#else
+#define CF_CACR_CINV		(1 << 24)
+#define CF_CACR_DISI		(1 << 23)
+#define CF_CACR_DISD		(1 << 22)
+#define CF_CACR_INVI		(1 << 21)
+#define CF_CACR_INVD		(1 << 20)
+#define CF_CACR_DWP		(1 << 5)
+#define CF_CACR_EUSP		(1 << 4)
+#endif				/* CONFIG_MCF5249 || CONFIG_MCF5253 */
+
+#endif				/* CONFIG_CF_V2 */
+
+/* V3 Core */
+#ifdef CONFIG_CF_V3
+
+#define CF_CACR_EC		(1 << 31)
+#define CF_CACR_ESB		(1 << 29)
+#define CF_CACR_DPI		(1 << 28)
+#define CF_CACR_HLCK		(1 << 27)
+#define CF_CACR_CINVA		(1 << 24)
+#define CF_CACR_DNFB		(1 << 10)
+#define CF_CACR_DCM_UNMASK	0xFFFFFCFF
+#define CF_CACR_DCM_WT		(0 << 8)
+#define CF_CACR_DCM_CB		(1 << 8)
+#define CF_CACR_DCM_P		(2 << 8)
+#define CF_CACR_DCM_IP		(3 << 8)
+#define CF_CACR_DW		(1 << 5)
+#define CF_CACR_EUSP		(1 << 4)
+
+#endif				/* CONFIG_CF_V3 */
+
+/* V4 Core */
+#ifdef CONFIG_CF_V4
+
+#define CF_CACR_DEC		(1 << 31)
+#define CF_CACR_DW		(1 << 30)
+#define CF_CACR_DESB		(1 << 29)
+#define CF_CACR_DDPI		(1 << 28)
+#define CF_CACR_DHLCK		(1 << 27)
+#define CF_CACR_DDCM_UNMASK	(0xF9FFFFFF)
+#define CF_CACR_DDCM_WT		(0 << 25)
+#define CF_CACR_DDCM_CB		(1 << 25)
+#define CF_CACR_DDCM_P		(2 << 25)
+#define CF_CACR_DDCM_IP		(3 << 25)
+#define CF_CACR_DCINVA		(1 << 24)
+
+#define CF_CACR_DDSP		(1 << 23)
+#define CF_CACR_BEC		(1 << 19)
+#define CF_CACR_BCINVA		(1 << 18)
+#define CF_CACR_IEC		(1 << 15)
+#define CF_CACR_DNFB		(1 << 13)
+#define CF_CACR_IDPI		(1 << 12)
+#define CF_CACR_IHLCK		(1 << 11)
+#define CF_CACR_IDCM		(1 << 10)
+#define CF_CACR_ICINVA		(1 << 8)
+#define CF_CACR_IDSP		(1 << 7)
+#define CF_CACR_EUSP		(1 << 5)
+
+#ifdef CONFIG_MCF5445x
+#define CF_CACR_IVO		(1 << 20)
+#define CF_CACR_SPA		(1 << 14)
+#else
+#define CF_CACR_DF		(1 << 4)
+#endif
+
+#endif				/* CONFIG_CF_V4 */
+
+/* ***** ACR ***** */
+#define CF_ACR_ADR_UNMASK	(0x00FFFFFF)
+#define CF_ACR_ADR(x)		((x & 0xFF) << 24)
+#define CF_ACR_ADRMSK_UNMASK	(0xFF00FFFF)
+#define CF_ACR_ADRMSK(x)	((x & 0xFF) << 16)
+#define CF_ACR_EN		(1 << 15)
+#define CF_ACR_SM_UNMASK	(0xFFFF9FFF)
+#define CF_ACR_SM_UM		(0 << 13)
+#define CF_ACR_SM_SM		(1 << 13)
+#define CF_ACR_SM_ALL		(3 << 13)
+#define CF_ACR_WP		(1 << 2)
+
+/* V2 Core */
+#ifdef CONFIG_CF_V2
+#define CF_ACR_CM		(1 << 6)
+#define CF_ACR_BWE		(1 << 5)
+#else
+/* V3 & V4 */
+#define CF_ACR_CM_UNMASK	(0xFFFFFF9F)
+#define CF_ACR_CM_WT		(0 << 5)
+#define CF_ACR_CM_CB		(1 << 5)
+#define CF_ACR_CM_P		(2 << 5)
+#define CF_ACR_CM_IP		(3 << 5)
+#endif				/* CONFIG_CF_V2 */
+
+/* V4 Core */
+#ifdef CONFIG_CF_V4
+#define CF_ACR_AMM		(1 << 10)
+#define CF_ACR_SP		(1 << 3)
+#endif				/* CONFIG_CF_V4 */
+
+
+#ifndef CONFIG_SYS_CACHE_ICACR
+#define CONFIG_SYS_CACHE_ICACR	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_DCACR
+#ifdef CONFIG_SYS_CACHE_ICACR
+#define CONFIG_SYS_CACHE_DCACR	CONFIG_SYS_CACHE_ICACR
+#else
+#define CONFIG_SYS_CACHE_DCACR	0
+#endif
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR0
+#define CONFIG_SYS_CACHE_ACR0	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR1
+#define CONFIG_SYS_CACHE_ACR1	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR2
+#define CONFIG_SYS_CACHE_ACR2	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR3
+#define CONFIG_SYS_CACHE_ACR3	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR4
+#define CONFIG_SYS_CACHE_ACR4	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR5
+#define CONFIG_SYS_CACHE_ACR5	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR6
+#define CONFIG_SYS_CACHE_ACR6	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR7
+#define CONFIG_SYS_CACHE_ACR7	0
+#endif
+
+#define CF_ADDRMASK(x)		(((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16)
+
+#ifndef __ASSEMBLY__		/* put C only stuff in this section */
+
+void icache_invalid(void);
+void dcache_invalid(void);
+
+#endif
+
+#endif				/* __CACHE_H */
diff --git a/include/asm-m68k/immap_5253.h b/include/asm-m68k/immap_5253.h
index b5a4cb54a7..28cd107a82 100644
--- a/include/asm-m68k/immap_5253.h
+++ b/include/asm-m68k/immap_5253.h
@@ -37,6 +37,7 @@
 #define MMAP_CAN0		(CONFIG_SYS_MBAR + 0x00010000)
 #define MMAP_CAN1		(CONFIG_SYS_MBAR + 0x00011000)
 
+#define MMAP_PAR		(CONFIG_SYS_MBAR2 + 0x0000019C)
 #define MMAP_I2C1		(CONFIG_SYS_MBAR2 + 0x00000440)
 #define MMAP_UART2		(CONFIG_SYS_MBAR2 + 0x00000C00)
 
diff --git a/include/asm-m68k/m520x.h b/include/asm-m68k/m520x.h
index 267bfd994a..71f147e751 100644
--- a/include/asm-m68k/m520x.h
+++ b/include/asm-m68k/m520x.h
@@ -70,7 +70,6 @@
 #define PACR_TP	1
 
 #define SCM_BMT_BME			(0x00000008)
-#define SCM_BMT_BMT_MASK		(0x07)
 #define SCM_BMT_BMT(x)			((x) & 0x07)
 #define SCM_BMT_BMT1024			(0x0000)
 #define SCM_BMT_BMT512			(0x0001)
@@ -179,7 +178,7 @@
 #define CCM_CCR_PLL_MODE		(0x0002)
 #define CCM_CCR_RESERVED		(0x0001)
 
-#define CCM_CIR_PIN(x)			(((x) & 0x03FF) << 6)
+#define CCM_CIR_PIN(x)			(((x) & 0xFFC0) >> 6)
 #define CCM_CIR_PRN(x)			((x) & 0x003F)
 
 /* *** General Purpose I/O (GPIO) *** */
@@ -196,7 +195,7 @@
 #define GPIO_PAR_FBCTL_OE		(0x10)
 #define GPIO_PAR_FBCTL_TA		(0x08)
 #define GPIO_PAR_FBCTL_RWB		(0x04)
-#define GPIO_PAR_FBCTL_TS_MASK		(0xFC)
+#define GPIO_PAR_FBCTL_TS_UNMASK	(0xFC)
 #define GPIO_PAR_FBCTL_TS_TS		(0x03)
 #define GPIO_PAR_FBCTL_TS_DMA		(0x02)
 
@@ -207,39 +206,39 @@
 
 #define GPIO_PAR_CS3			(0x08)
 #define GPIO_PAR_CS2			(0x04)
-#define GPIO_PAR_CS1_MASK		(0xFC)
+#define GPIO_PAR_CS1_UNMASK		(0xFC)
 #define GPIO_PAR_CS1_CS1		(0x03)
 #define GPIO_PAR_CS1_SDCS1		(0x02)
 
-#define GPIO_PAR_FECI2C_RMII_MASK	(0x0F)
-#define GPIO_PAR_FECI2C_MDC_MASK	(0x3F)
+#define GPIO_PAR_FECI2C_RMII_UNMASK	(0x0F)
+#define GPIO_PAR_FECI2C_MDC_UNMASK	(0x3F)
 #define GPIO_PAR_FECI2C_MDC_MDC		(0xC0)
 #define GPIO_PAR_FECI2C_MDC_SCL		(0x80)
 #define GPIO_PAR_FECI2C_MDC_U2TXD	(0x40)
-#define GPIO_PAR_FECI2C_MDIO_MASK	(0xCF)
+#define GPIO_PAR_FECI2C_MDIO_UNMASK	(0xCF)
 #define GPIO_PAR_FECI2C_MDIO_MDIO	(0x30)
 #define GPIO_PAR_FECI2C_MDIO_SDA	(0x20)
 #define GPIO_PAR_FECI2C_MDIO_U2RXD	(0x10)
-#define GPIO_PAR_FECI2C_I2C_MASK	(0xF0)
-#define GPIO_PAR_FECI2C_SCL_MASK	(0xF3)
+#define GPIO_PAR_FECI2C_I2C_UNMASK	(0xF0)
+#define GPIO_PAR_FECI2C_SCL_UNMASK	(0xF3)
 #define GPIO_PAR_FECI2C_SCL_SCL		(0x0C)
 #define GPIO_PAR_FECI2C_SCL_U2RXD	(0x04)
-#define GPIO_PAR_FECI2C_SDA_MASK	(0xFC)
+#define GPIO_PAR_FECI2C_SDA_UNMASK	(0xFC)
 #define GPIO_PAR_FECI2C_SDA_SDA		(0x03)
 #define GPIO_PAR_FECI2C_SDA_U2TXD	(0x01)
 
-#define GPIO_PAR_QSPI_PCS2_MASK		(0x3F)
+#define GPIO_PAR_QSPI_PCS2_UNMASK	(0x3F)
 #define GPIO_PAR_QSPI_PCS2_PCS2		(0xC0)
 #define GPIO_PAR_QSPI_PCS2_DACK0	(0x80)
 #define GPIO_PAR_QSPI_PCS2_U2RTS	(0x40)
-#define GPIO_PAR_QSPI_DIN_MASK		(0xCF)
+#define GPIO_PAR_QSPI_DIN_UNMASK	(0xCF)
 #define GPIO_PAR_QSPI_DIN_DIN		(0x30)
 #define GPIO_PAR_QSPI_DIN_DREQ0		(0x20)
 #define GPIO_PAR_QSPI_DIN_U2CTS		(0x10)
-#define GPIO_PAR_QSPI_DOUT_MASK		(0xF3)
+#define GPIO_PAR_QSPI_DOUT_UNMASK	(0xF3)
 #define GPIO_PAR_QSPI_DOUT_DOUT		(0x0C)
 #define GPIO_PAR_QSPI_DOUT_SDA		(0x08)
-#define GPIO_PAR_QSPI_SCK_MASK		(0xFC)
+#define GPIO_PAR_QSPI_SCK_UNMASK	(0xFC)
 #define GPIO_PAR_QSPI_SCK_SCK		(0x03)
 #define GPIO_PAR_QSPI_SCK_SCL		(0x02)
 
@@ -247,50 +246,50 @@
 #define GPIO_PAR_TMR_TIN2(x)		(((x) & 0x03) << 4)
 #define GPIO_PAR_TMR_TIN1(x)		(((x) & 0x03) << 2)
 #define GPIO_PAR_TMR_TIN0(x)		((x) & 0x03)
-#define GPIO_PAR_TMR_TIN3_MASK		(0x3F)
+#define GPIO_PAR_TMR_TIN3_UNMASK	(0x3F)
 #define GPIO_PAR_TMR_TIN3_TIN3		(0xC0)
 #define GPIO_PAR_TMR_TIN3_TOUT3		(0x80)
 #define GPIO_PAR_TMR_TIN3_U2CTS		(0x40)
-#define GPIO_PAR_TMR_TIN2_MASK		(0xCF)
+#define GPIO_PAR_TMR_TIN2_UNMASK	(0xCF)
 #define GPIO_PAR_TMR_TIN2_TIN2		(0x30)
 #define GPIO_PAR_TMR_TIN2_TOUT2		(0x20)
 #define GPIO_PAR_TMR_TIN2_U2RTS		(0x10)
-#define GPIO_PAR_TMR_TIN1_MASK		(0xF3)
+#define GPIO_PAR_TMR_TIN1_UNMASK	(0xF3)
 #define GPIO_PAR_TMR_TIN1_TIN1		(0x0C)
 #define GPIO_PAR_TMR_TIN1_TOUT1		(0x08)
 #define GPIO_PAR_TMR_TIN1_U2RXD		(0x04)
-#define GPIO_PAR_TMR_TIN0_MASK		(0xFC)
+#define GPIO_PAR_TMR_TIN0_UNMASK	(0xFC)
 #define GPIO_PAR_TMR_TIN0_TIN0		(0x03)
 #define GPIO_PAR_TMR_TIN0_TOUT0		(0x02)
 #define GPIO_PAR_TMR_TIN0_U2TXD		(0x01)
 
-#define GPIO_PAR_UART1_MASK		(0xF03F)
-#define GPIO_PAR_UART0_MASK		(0xFFC0)
-#define GPIO_PAR_UART_U1CTS_MASK	(0xF3FF)
+#define GPIO_PAR_UART1_UNMASK		(0xF03F)
+#define GPIO_PAR_UART0_UNMASK		(0xFFC0)
+#define GPIO_PAR_UART_U1CTS_UNMASK	(0xF3FF)
 #define GPIO_PAR_UART_U1CTS_U1CTS	(0x0C00)
 #define GPIO_PAR_UART_U1CTS_TIN1	(0x0800)
 #define GPIO_PAR_UART_U1CTS_PCS1	(0x0400)
-#define GPIO_PAR_UART_U1RTS_MASK	(0xFCFF)
+#define GPIO_PAR_UART_U1RTS_UNMASK	(0xFCFF)
 #define GPIO_PAR_UART_U1RTS_U1RTS	(0x0300)
 #define GPIO_PAR_UART_U1RTS_TOUT1	(0x0200)
 #define GPIO_PAR_UART_U1RTS_PCS1	(0x0100)
 #define GPIO_PAR_UART_U1TXD		(0x0080)
 #define GPIO_PAR_UART_U1RXD		(0x0040)
-#define GPIO_PAR_UART_U0CTS_MASK	(0xFFCF)
+#define GPIO_PAR_UART_U0CTS_UNMASK	(0xFFCF)
 #define GPIO_PAR_UART_U0CTS_U0CTS	(0x0030)
 #define GPIO_PAR_UART_U0CTS_TIN0	(0x0020)
 #define GPIO_PAR_UART_U0CTS_PCS0	(0x0010)
-#define GPIO_PAR_UART_U0RTS_MASK	(0xFFF3)
+#define GPIO_PAR_UART_U0RTS_UNMASK	(0xFFF3)
 #define GPIO_PAR_UART_U0RTS_U0RTS	(0x000C)
 #define GPIO_PAR_UART_U0RTS_TOUT0	(0x0008)
 #define GPIO_PAR_UART_U0RTS_PCS0	(0x0004)
 #define GPIO_PAR_UART_U0TXD		(0x0002)
 #define GPIO_PAR_UART_U0RXD		(0x0001)
 
-#define GPIO_PAR_FEC_7W_MASK		(0xF3)
+#define GPIO_PAR_FEC_7W_UNMASK		(0xF3)
 #define GPIO_PAR_FEC_7W_FEC		(0x0C)
 #define GPIO_PAR_FEC_7W_U1RTS		(0x04)
-#define GPIO_PAR_FEC_MII_MASK		(0xFC)
+#define GPIO_PAR_FEC_MII_UNMASK		(0xFC)
 #define GPIO_PAR_FEC_MII_FEC		(0x03)
 #define GPIO_PAR_FEC_MII_UnCTS		(0x01)
 
@@ -300,17 +299,17 @@
 #define GPIO_MSCR_FB_DUP(x)		(((x) & 0x03) << 4)
 #define GPIO_MSCR_FB_DLO(x)		(((x) & 0x03) << 2)
 #define GPIO_MSCR_FB_ADRCTL(x)		((x) & 0x03)
-#define GPIO_MSCR_FB_FBCLK_MASK		(0x3F)
-#define GPIO_MSCR_FB_DUP_MASK		(0xCF)
-#define GPIO_MSCR_FB_DLO_MASK		(0xF3)
-#define GPIO_MSCR_FB_ADRCTL_MASK	(0xFC)
+#define GPIO_MSCR_FB_FBCLK_UNMASK	(0x3F)
+#define GPIO_MSCR_FB_DUP_UNMASK		(0xCF)
+#define GPIO_MSCR_FB_DLO_UNMASK		(0xF3)
+#define GPIO_MSCR_FB_ADRCTL_UNMASK	(0xFC)
 
 #define GPIO_MSCR_SDR_SDCLKB(x)		(((x) & 0x03) << 4)
 #define GPIO_MSCR_SDR_SDCLK(x)		(((x) & 0x03) << 2)
 #define GPIO_MSCR_SDR_SDRAM(x)		((x) & 0x03)
-#define GPIO_MSCR_SDR_SDCLKB_MASK	(0xCF)
-#define GPIO_MSCR_SDR_SDCLK_MASK	(0xF3)
-#define GPIO_MSCR_SDR_SDRAM_MASK	(0xFC)
+#define GPIO_MSCR_SDR_SDCLKB_UNMASK	(0xCF)
+#define GPIO_MSCR_SDR_SDCLK_UNMASK	(0xF3)
+#define GPIO_MSCR_SDR_SDRAM_UNMASK	(0xFC)
 
 #define MSCR_25VDDR			(0x03)
 #define MSCR_18VDDR_FULL		(0x02)
@@ -318,27 +317,27 @@
 #define MSCR_18VDDR_HALF		(0x00)
 
 #define GPIO_DSCR_I2C(x)		((x) & 0x03)
-#define GPIO_DSCR_I2C_MASK		(0xFC)
+#define GPIO_DSCR_I2C_UNMASK		(0xFC)
 
 #define GPIO_DSCR_MISC_DBG(x)		(((x) & 0x03) << 4)
-#define GPIO_DSCR_MISC_DBG_MASK		(0xCF)
+#define GPIO_DSCR_MISC_DBG_UNMASK	(0xCF)
 #define GPIO_DSCR_MISC_RSTOUT(x)	(((x) & 0x03) << 2)
-#define GPIO_DSCR_MISC_RSTOUT_MASK	(0xF3)
+#define GPIO_DSCR_MISC_RSTOUT_UNMASK	(0xF3)
 #define GPIO_DSCR_MISC_TIMER(x)		((x) & 0x03)
-#define GPIO_DSCR_MISC_TIMER_MASK	(0xFC)
+#define GPIO_DSCR_MISC_TIMER_UNMASK	(0xFC)
 
 #define GPIO_DSCR_FEC(x)		((x) & 0x03)
-#define GPIO_DSCR_FEC_MASK		(0xFC)
+#define GPIO_DSCR_FEC_UNMASK		(0xFC)
 
 #define GPIO_DSCR_UART_UART1(x)		(((x) & 0x03) << 4)
-#define GPIO_DSCR_UART_UART1_MASK	(0xCF)
+#define GPIO_DSCR_UART_UART1_UNMASK	(0xCF)
 #define GPIO_DSCR_UART_UART0(x)		(((x) & 0x03) << 2)
-#define GPIO_DSCR_UART_UART0_MASK	(0xF3)
+#define GPIO_DSCR_UART_UART0_UNMASK	(0xF3)
 #define GPIO_DSCR_UART_IRQ(x)		((x) & 0x03)
-#define GPIO_DSCR_UART_IRQ_MASK		(0xFC)
+#define GPIO_DSCR_UART_IRQ_UNMASK	(0xFC)
 
 #define GPIO_DSCR_QSPI(x)		((x) & 0x03)
-#define GPIO_DSCR_QSPI_MASK		(0xFC)
+#define GPIO_DSCR_QSPI_UNMASK		(0xFC)
 
 #define DSCR_50PF			(0x03)
 #define DSCR_30PF			(0x02)
@@ -347,12 +346,12 @@
 
 /* *** Phase Locked Loop (PLL) *** */
 #define PLL_PODR_CPUDIV(x)		(((x) & 0x0F) << 4)
-#define PLL_PODR_CPUDIV_MASK		(0x0F)
+#define PLL_PODR_CPUDIV_UNMASK		(0x0F)
 #define PLL_PODR_BUSDIV(x)		((x) & 0x0F)
-#define PLL_PODR_BUSDIV_MASK		(0xF0)
+#define PLL_PODR_BUSDIV_UNMASK		(0xF0)
 
 #define PLL_PCR_DITHEN			(0x80)
 #define PLL_PCR_DITHDEV(x)		((x) & 0x07)
-#define PLL_PCR_DITHDEV_MASK		(0xF8)
+#define PLL_PCR_DITHDEV_UNMASK		(0xF8)
 
 #endif				/* __M520X__ */
diff --git a/include/asm-m68k/m5227x.h b/include/asm-m68k/m5227x.h
index 824d333114..c77d5dd657 100644
--- a/include/asm-m68k/m5227x.h
+++ b/include/asm-m68k/m5227x.h
@@ -117,36 +117,34 @@
 
 /* Bit definitions and macros for CCR */
 #define CCM_CCR_DRAMSEL			(0x0100)
-#define CCM_CCR_CSC_MASK		(0xFF3F)
+#define CCM_CCR_CSC_UNMASK		(0xFF3F)
 #define CCM_CCR_CSC_FBCS5_CS4		(0x00C0)
 #define CCM_CCR_CSC_FBCS5_A22		(0x0080)
 #define CCM_CCR_CSC_FB_A23_A22		(0x0040)
 #define CCM_CCR_LIMP			(0x0020)
 #define CCM_CCR_LOAD			(0x0010)
-#define CCM_CCR_BOOTPS_MASK		(0xFFF3)
+#define CCM_CCR_BOOTPS_UNMASK		(0xFFF3)
 #define CCM_CCR_BOOTPS_PS16		(0x0008)
 #define CCM_CCR_BOOTPS_PS8		(0x0004)
 #define CCM_CCR_BOOTPS_PS32		(0x0000)
 #define CCM_CCR_OSCMODE_OSCBYPASS	(0x0002)
 
 /* Bit definitions and macros for RCON */
-#define CCM_RCON_CSC_MASK		(0xFF3F)
+#define CCM_RCON_CSC_UNMASK		(0xFF3F)
 #define CCM_RCON_CSC_FBCS5_CS4		(0x00C0)
 #define CCM_RCON_CSC_FBCS5_A22		(0x0080)
 #define CCM_RCON_CSC_FB_A23_A22		(0x0040)
 #define CCM_RCON_LIMP			(0x0020)
 #define CCM_RCON_LOAD			(0x0010)
-#define CCM_RCON_BOOTPS_MASK		(0xFFF3)
+#define CCM_RCON_BOOTPS_UNMASK		(0xFFF3)
 #define CCM_RCON_BOOTPS_PS16		(0x0008)
 #define CCM_RCON_BOOTPS_PS8		(0x0004)
 #define CCM_RCON_BOOTPS_PS32		(0x0000)
 #define CCM_RCON_OSCMODE_OSCBYPASS	(0x0002)
 
 /* Bit definitions and macros for CIR */
-#define CCM_CIR_PRN(x)			(((x)&0x003F))	/* Part revision number */
-#define CCM_CIR_PIN(x)			(((x)&0x03FF)<<6)	/* Part identification number */
-#define CCM_CIR_PIN_MASK		(0xFFC0)
-#define CCM_CIR_PRN_MASK		(0x003F)
+#define CCM_CIR_PIN(x)			(((x) & 0xFFC0) >> 6)
+#define CCM_CIR_PRN(x)			((x) & 0x003F)
 #define CCM_CIR_PIN_MCF52277		(0x0000)
 
 /* Bit definitions and macros for MISCCR */
@@ -195,7 +193,7 @@
 * General Purpose I/O Module (GPIO)
 *********************************************************************/
 /* Bit definitions and macros for PAR_BE */
-#define GPIO_PAR_BE_MASK		(0x0F)
+#define GPIO_PAR_BE_UNMASK		(0x0F)
 #define GPIO_PAR_BE_BE3_BE3		(0x08)
 #define GPIO_PAR_BE_BE3_GPIO		(0x00)
 #define GPIO_PAR_BE_BE2_BE2		(0x04)
@@ -217,111 +215,111 @@
 #define GPIO_PAR_FBCTL_OE		(0x80)
 #define GPIO_PAR_FBCTL_TA		(0x40)
 #define GPIO_PAR_FBCTL_RW		(0x20)
-#define GPIO_PAR_FBCTL_TS_MASK		(0xE7)
+#define GPIO_PAR_FBCTL_TS_UNMASK	(0xE7)
 #define GPIO_PAR_FBCTL_TS_FBTS		(0x18)
 #define GPIO_PAR_FBCTL_TS_DMAACK	(0x10)
 #define GPIO_PAR_FBCTL_TS_GPIO		(0x00)
 
 /* Bit definitions and macros for PAR_FECI2C */
-#define GPIO_PAR_I2C_SCL_MASK		(0xF3)
+#define GPIO_PAR_I2C_SCL_UNMASK		(0xF3)
 #define GPIO_PAR_I2C_SCL_SCL		(0x0C)
 #define GPIO_PAR_I2C_SCL_CANTXD		(0x08)
 #define GPIO_PAR_I2C_SCL_U2TXD		(0x04)
 #define GPIO_PAR_I2C_SCL_GPIO		(0x00)
 
-#define GPIO_PAR_I2C_SDA_MASK		(0xFC)
+#define GPIO_PAR_I2C_SDA_UNMASK		(0xFC)
 #define GPIO_PAR_I2C_SDA_SDA		(0x03)
 #define GPIO_PAR_I2C_SDA_CANRXD		(0x02)
 #define GPIO_PAR_I2C_SDA_U2RXD		(0x01)
 #define GPIO_PAR_I2C_SDA_GPIO		(0x00)
 
 /* Bit definitions and macros for PAR_UART */
-#define GPIO_PAR_UART_U1CTS_MASK	(0x3FFF)
+#define GPIO_PAR_UART_U1CTS_UNMASK	(0x3FFF)
 #define GPIO_PAR_UART_U1CTS_U1CTS	(0xC000)
 #define GPIO_PAR_UART_U1CTS_SSIBCLK	(0x8000)
 #define GPIO_PAR_UART_U1CTS_LCDCLS	(0x4000)
 #define GPIO_PAR_UART_U1CTS_GPIO	(0x0000)
 
-#define GPIO_PAR_UART_U1RTS_MASK	(0xCFFF)
+#define GPIO_PAR_UART_U1RTS_UNMASK	(0xCFFF)
 #define GPIO_PAR_UART_U1RTS_U1RTS	(0x3000)
 #define GPIO_PAR_UART_U1RTS_SSIFS	(0x2000)
 #define GPIO_PAR_UART_U1RTS_LCDPS	(0x1000)
 #define GPIO_PAR_UART_U1RTS_GPIO	(0x0000)
 
-#define GPIO_PAR_UART_U1RXD_MASK	(0xF3FF)
+#define GPIO_PAR_UART_U1RXD_UNMASK	(0xF3FF)
 #define GPIO_PAR_UART_U1RXD_U1RXD	(0x0C00)
 #define GPIO_PAR_UART_U1RXD_SSIRXD	(0x0800)
 #define GPIO_PAR_UART_U1RXD_GPIO	(0x0000)
 
-#define GPIO_PAR_UART_U1TXD_MASK	(0xFCFF)
+#define GPIO_PAR_UART_U1TXD_UNMASK	(0xFCFF)
 #define GPIO_PAR_UART_U1TXD_U1TXD	(0x0300)
 #define GPIO_PAR_UART_U1TXD_SSITXD	(0x0200)
 #define GPIO_PAR_UART_U1TXD_GPIO	(0x0000)
 
-#define GPIO_PAR_UART_U0CTS_MASK	(0xFF3F)
+#define GPIO_PAR_UART_U0CTS_UNMASK	(0xFF3F)
 #define GPIO_PAR_UART_U0CTS_U0CTS	(0x00C0)
 #define GPIO_PAR_UART_U0CTS_T1OUT	(0x0080)
 #define GPIO_PAR_UART_U0CTS_USBVBUSEN	(0x0040)
 #define GPIO_PAR_UART_U0CTS_GPIO	(0x0000)
 
-#define GPIO_PAR_UART_U0RTS_MASK	(0xFFCF)
+#define GPIO_PAR_UART_U0RTS_UNMASK	(0xFFCF)
 #define GPIO_PAR_UART_U0RTS_U0RTS	(0x0030)
 #define GPIO_PAR_UART_U0RTS_T1IN	(0x0020)
 #define GPIO_PAR_UART_U0RTS_USBVBUSOC	(0x0010)
 #define GPIO_PAR_UART_U0RTS_GPIO	(0x0000)
 
-#define GPIO_PAR_UART_U0RXD_MASK	(0xFFF3)
+#define GPIO_PAR_UART_U0RXD_UNMASK	(0xFFF3)
 #define GPIO_PAR_UART_U0RXD_U0RXD	(0x000C)
 #define GPIO_PAR_UART_U0RXD_CANRX	(0x0008)
 #define GPIO_PAR_UART_U0RXD_GPIO	(0x0000)
 
-#define GPIO_PAR_UART_U0TXD_MASK	(0xFFFC)
+#define GPIO_PAR_UART_U0TXD_UNMASK	(0xFFFC)
 #define GPIO_PAR_UART_U0TXD_U0TXD	(0x0003)
 #define GPIO_PAR_UART_U0TXD_CANTX	(0x0002)
 #define GPIO_PAR_UART_U0TXD_GPIO	(0x0000)
 
 /* Bit definitions and macros for PAR_DSPI */
-#define GPIO_PAR_DSPI_PCS0_MASK		(0x3F)
+#define GPIO_PAR_DSPI_PCS0_UNMASK	(0x3F)
 #define GPIO_PAR_DSPI_PCS0_PCS0		(0xC0)
 #define GPIO_PAR_DSPI_PCS0_U2RTS	(0x80)
 #define GPIO_PAR_DSPI_PCS0_GPIO		(0x00)
-#define GPIO_PAR_DSPI_SIN_MASK		(0xCF)
+#define GPIO_PAR_DSPI_SIN_UNMASK	(0xCF)
 #define GPIO_PAR_DSPI_SIN_SIN		(0x30)
 #define GPIO_PAR_DSPI_SIN_U2RXD		(0x20)
 #define GPIO_PAR_DSPI_SIN_GPIO		(0x00)
-#define GPIO_PAR_DSPI_SOUT_MASK		(0xF3)
+#define GPIO_PAR_DSPI_SOUT_UNMASK	(0xF3)
 #define GPIO_PAR_DSPI_SOUT_SOUT		(0x0C)
 #define GPIO_PAR_DSPI_SOUT_U2TXD	(0x08)
 #define GPIO_PAR_DSPI_SOUT_GPIO		(0x00)
-#define GPIO_PAR_DSPI_SCK_MASK		(0xFC)
+#define GPIO_PAR_DSPI_SCK_UNMASK	(0xFC)
 #define GPIO_PAR_DSPI_SCK_SCK		(0x03)
 #define GPIO_PAR_DSPI_SCK_U2CTS		(0x02)
 #define GPIO_PAR_DSPI_SCK_GPIO		(0x00)
 
 /* Bit definitions and macros for PAR_TIMER */
-#define GPIO_PAR_TIMER_T3IN_MASK	(0x3F)
+#define GPIO_PAR_TIMER_T3IN_UNMASK	(0x3F)
 #define GPIO_PAR_TIMER_T3IN_T3IN	(0xC0)
 #define GPIO_PAR_TIMER_T3IN_T3OUT	(0x80)
 #define GPIO_PAR_TIMER_T3IN_SSIMCLK	(0x40)
 #define GPIO_PAR_TIMER_T3IN_GPIO	(0x00)
-#define GPIO_PAR_TIMER_T2IN_MASK	(0xCF)
+#define GPIO_PAR_TIMER_T2IN_UNMASK	(0xCF)
 #define GPIO_PAR_TIMER_T2IN_T2IN	(0x30)
 #define GPIO_PAR_TIMER_T2IN_T2OUT	(0x20)
 #define GPIO_PAR_TIMER_T2IN_DSPIPCS2	(0x10)
 #define GPIO_PAR_TIMER_T2IN_GPIO	(0x00)
-#define GPIO_PAR_TIMER_T1IN_MASK	(0xF3)
+#define GPIO_PAR_TIMER_T1IN_UNMASK	(0xF3)
 #define GPIO_PAR_TIMER_T1IN_T1IN	(0x0C)
 #define GPIO_PAR_TIMER_T1IN_T1OUT	(0x08)
 #define GPIO_PAR_TIMER_T1IN_LCDCONTRAST	(0x04)
 #define GPIO_PAR_TIMER_T1IN_GPIO	(0x00)
-#define GPIO_PAR_TIMER_T0IN_MASK	(0xFC)
+#define GPIO_PAR_TIMER_T0IN_UNMASK	(0xFC)
 #define GPIO_PAR_TIMER_T0IN_T0IN	(0x03)
 #define GPIO_PAR_TIMER_T0IN_T0OUT	(0x02)
 #define GPIO_PAR_TIMER_T0IN_LCDREV	(0x01)
 #define GPIO_PAR_TIMER_T0IN_GPIO	(0x00)
 
 /* Bit definitions and macros for GPIO_PAR_LCDCTL */
-#define GPIO_PAR_LCDCTL_ACDOE_MASK	(0xE7)
+#define GPIO_PAR_LCDCTL_ACDOE_UNMASK	(0xE7)
 #define GPIO_PAR_LCDCTL_ACDOE_ACDOE	(0x18)
 #define GPIO_PAR_LCDCTL_ACDOE_SPLSPR	(0x10)
 #define GPIO_PAR_LCDCTL_ACDOE_GPIO	(0x00)
@@ -330,141 +328,141 @@
 #define GPIO_PAR_LCDCTL_LSCLK		(0x01)
 
 /* Bit definitions and macros for PAR_IRQ */
-#define GPIO_PAR_IRQ_IRQ4_MASK		(0xF3)
+#define GPIO_PAR_IRQ_IRQ4_UNMASK	(0xF3)
 #define GPIO_PAR_IRQ_IRQ4_SSIINPCLK	(0x0C)
 #define GPIO_PAR_IRQ_IRQ4_DMAREQ0	(0x08)
 #define GPIO_PAR_IRQ_IRQ4_GPIO		(0x00)
-#define GPIO_PAR_IRQ_IRQ1_MASK		(0xFC)
+#define GPIO_PAR_IRQ_IRQ1_UNMASK	(0xFC)
 #define GPIO_PAR_IRQ_IRQ1_PCIINT	(0x03)
 #define GPIO_PAR_IRQ_IRQ1_USBCLKIN	(0x02)
 #define GPIO_PAR_IRQ_IRQ1_SSICLKIN	(0x01)
 #define GPIO_PAR_IRQ_IRQ1_GPIO		(0x00)
 
 /* Bit definitions and macros for GPIO_PAR_LCDH */
-#define GPIO_PAR_LCDH_LD17_MASK		(0xFFFFF3FF)
+#define GPIO_PAR_LCDH_LD17_UNMASK	(0xFFFFF3FF)
 #define GPIO_PAR_LCDH_LD17_LD17		(0x00000C00)
 #define GPIO_PAR_LCDH_LD17_LD11		(0x00000800)
 #define GPIO_PAR_LCDH_LD17_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDH_LD16_MASK		(0xFFFFFCFF)
+#define GPIO_PAR_LCDH_LD16_UNMASK	(0xFFFFFCFF)
 #define GPIO_PAR_LCDH_LD16_LD16		(0x00000300)
 #define GPIO_PAR_LCDH_LD16_LD10		(0x00000200)
 #define GPIO_PAR_LCDH_LD16_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDH_LD15_MASK		(0xFFFFFF3F)
+#define GPIO_PAR_LCDH_LD15_UNMASK	(0xFFFFFF3F)
 #define GPIO_PAR_LCDH_LD15_LD15		(0x000000C0)
 #define GPIO_PAR_LCDH_LD15_LD9		(0x00000080)
 #define GPIO_PAR_LCDH_LD15_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDH_LD14_MASK		(0xFFFFFFCF)
+#define GPIO_PAR_LCDH_LD14_UNMASK	(0xFFFFFFCF)
 #define GPIO_PAR_LCDH_LD14_LD14		(0x00000030)
 #define GPIO_PAR_LCDH_LD14_LD8		(0x00000020)
 #define GPIO_PAR_LCDH_LD14_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDH_LD13_MASK		(0xFFFFFFF3)
+#define GPIO_PAR_LCDH_LD13_UNMASK	(0xFFFFFFF3)
 #define GPIO_PAR_LCDH_LD13_LD13		(0x0000000C)
 #define GPIO_PAR_LCDH_LD13_CANTX	(0x00000008)
 #define GPIO_PAR_LCDH_LD13_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDH_LD12_MASK		(0xFFFFFFFC)
+#define GPIO_PAR_LCDH_LD12_UNMASK	(0xFFFFFFFC)
 #define GPIO_PAR_LCDH_LD12_LD12		(0x00000003)
 #define GPIO_PAR_LCDH_LD12_CANRX	(0x00000002)
 #define GPIO_PAR_LCDH_LD12_GPIO		(0x00000000)
 
 /* Bit definitions and macros for GPIO_PAR_LCDL */
-#define GPIO_PAR_LCDL_LD11_MASK		(0x3FFFFFFF)
+#define GPIO_PAR_LCDL_LD11_UNMASK	(0x3FFFFFFF)
 #define GPIO_PAR_LCDL_LD11_LD11		(0xC0000000)
 #define GPIO_PAR_LCDL_LD11_LD7		(0x80000000)
 #define GPIO_PAR_LCDL_LD11_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD10_MASK		(0xCFFFFFFF)
+#define GPIO_PAR_LCDL_LD10_UNMASK	(0xCFFFFFFF)
 #define GPIO_PAR_LCDL_LD10_LD10		(0x30000000)
 #define GPIO_PAR_LCDL_LD10_LD6		(0x20000000)
 #define GPIO_PAR_LCDL_LD10_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD9_MASK		(0xF3FFFFFF)
+#define GPIO_PAR_LCDL_LD9_UNMASK	(0xF3FFFFFF)
 #define GPIO_PAR_LCDL_LD9_LD9		(0x0C000000)
 #define GPIO_PAR_LCDL_LD9_LD5		(0x08000000)
 #define GPIO_PAR_LCDL_LD9_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD8_MASK		(0xFCFFFFFF)
+#define GPIO_PAR_LCDL_LD8_UNMASK	(0xFCFFFFFF)
 #define GPIO_PAR_LCDL_LD8_LD8		(0x03000000)
 #define GPIO_PAR_LCDL_LD8_LD4		(0x02000000)
 #define GPIO_PAR_LCDL_LD8_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD7_MASK		(0xFF3FFFFF)
+#define GPIO_PAR_LCDL_LD7_UNMASK	(0xFF3FFFFF)
 #define GPIO_PAR_LCDL_LD7_LD7		(0x00C00000)
 #define GPIO_PAR_LCDL_LD7_PWM7		(0x00800000)
 #define GPIO_PAR_LCDL_LD7_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD6_MASK		(0xFFCFFFFF)
+#define GPIO_PAR_LCDL_LD6_UNMASK	(0xFFCFFFFF)
 #define GPIO_PAR_LCDL_LD6_LD6		(0x00300000)
 #define GPIO_PAR_LCDL_LD6_PWM5		(0x00200000)
 #define GPIO_PAR_LCDL_LD6_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD5_MASK		(0xFFF3FFFF)
+#define GPIO_PAR_LCDL_LD5_UNMASK	(0xFFF3FFFF)
 #define GPIO_PAR_LCDL_LD5_LD5		(0x000C0000)
 #define GPIO_PAR_LCDL_LD5_LD3		(0x00080000)
 #define GPIO_PAR_LCDL_LD5_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD4_MASK		(0xFFFCFFFF)
+#define GPIO_PAR_LCDL_LD4_UNMASK	(0xFFFCFFFF)
 #define GPIO_PAR_LCDL_LD4_LD4		(0x00030000)
 #define GPIO_PAR_LCDL_LD4_LD2		(0x00020000)
 #define GPIO_PAR_LCDL_LD4_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD3_MASK		(0xFFFF3FFF)
+#define GPIO_PAR_LCDL_LD3_UNMASK	(0xFFFF3FFF)
 #define GPIO_PAR_LCDL_LD3_LD3		(0x0000C000)
 #define GPIO_PAR_LCDL_LD3_LD1		(0x00008000)
 #define GPIO_PAR_LCDL_LD3_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD2_MASK		(0xFFFFCFFF)
+#define GPIO_PAR_LCDL_LD2_UNMASK	(0xFFFFCFFF)
 #define GPIO_PAR_LCDL_LD2_LD2		(0x00003000)
 #define GPIO_PAR_LCDL_LD2_LD0		(0x00002000)
 #define GPIO_PAR_LCDL_LD2_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD1_MASK		(0xFFFFF3FF)
+#define GPIO_PAR_LCDL_LD1_UNMASK	(0xFFFFF3FF)
 #define GPIO_PAR_LCDL_LD1_LD1		(0x00000C00)
 #define GPIO_PAR_LCDL_LD1_PWM3		(0x00000800)
 #define GPIO_PAR_LCDL_LD1_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD0_MASK		(0xFFFFFCFF)
+#define GPIO_PAR_LCDL_LD0_UNMASK	(0xFFFFFCFF)
 #define GPIO_PAR_LCDL_LD0_LD0		(0x00000300)
 #define GPIO_PAR_LCDL_LD0_PWM1		(0x00000200)
 #define GPIO_PAR_LCDL_LD0_GPIO		(0x00000000)
 
 /* Bit definitions and macros for MSCR_FB */
-#define GPIO_MSCR_FB_DUPPER_MASK	(0xCF)
+#define GPIO_MSCR_FB_DUPPER_UNMASK	(0xCF)
 #define GPIO_MSCR_FB_DUPPER_25V_33V	(0x30)
 #define GPIO_MSCR_FB_DUPPER_FULL_18V	(0x20)
 #define GPIO_MSCR_FB_DUPPER_OD		(0x10)
 #define GPIO_MSCR_FB_DUPPER_HALF_18V	(0x00)
 
-#define GPIO_MSCR_FB_DLOWER_MASK	(0xF3)
+#define GPIO_MSCR_FB_DLOWER_UNMASK	(0xF3)
 #define GPIO_MSCR_FB_DLOWER_25V_33V	(0x0C)
 #define GPIO_MSCR_FB_DLOWER_FULL_18V	(0x08)
 #define GPIO_MSCR_FB_DLOWER_OD		(0x04)
 #define GPIO_MSCR_FB_DLOWER_HALF_18V	(0x00)
 
-#define GPIO_MSCR_FB_ADDRCTL_MASK	(0xFC)
+#define GPIO_MSCR_FB_ADDRCTL_UNMASK	(0xFC)
 #define GPIO_MSCR_FB_ADDRCTL_25V_33V	(0x03)
 #define GPIO_MSCR_FB_ADDRCTL_FULL_18V	(0x02)
 #define GPIO_MSCR_FB_ADDRCTL_OD		(0x01)
 #define GPIO_MSCR_FB_ADDRCTL_HALF_18V	(0x00)
 
 /* Bit definitions and macros for MSCR_SDRAM */
-#define GPIO_MSCR_SDRAM_SDCLKB_MASK	(0xCF)
+#define GPIO_MSCR_SDRAM_SDCLKB_UNMASK	(0xCF)
 #define GPIO_MSCR_SDRAM_SDCLKB_25V_33V	(0x30)
 #define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V	(0x20)
 #define GPIO_MSCR_SDRAM_SDCLKB_OD	(0x10)
 #define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V	(0x00)
 
-#define GPIO_MSCR_SDRAM_SDCLK_MASK	(0xF3)
+#define GPIO_MSCR_SDRAM_SDCLK_UNMASK	(0xF3)
 #define GPIO_MSCR_SDRAM_SDCLK_25V_33V	(0x0C)
 #define GPIO_MSCR_SDRAM_SDCLK_FULL_18V	(0x08)
 #define GPIO_MSCR_SDRAM_SDCLK_OPD	(0x04)
 #define GPIO_MSCR_SDRAM_SDCLK_HALF_18V	(0x00)
 
-#define GPIO_MSCR_SDRAM_SDCTL_MASK	(0xFC)
+#define GPIO_MSCR_SDRAM_SDCTL_UNMASK	(0xFC)
 #define GPIO_MSCR_SDRAM_SDCTL_25V_33V	(0x03)
 #define GPIO_MSCR_SDRAM_SDCTL_FULL_18V	(0x02)
 #define GPIO_MSCR_SDRAM_SDCTL_OPD	(0x01)
diff --git a/include/asm-m68k/m5235.h b/include/asm-m68k/m5235.h
index 22987ac778..71a40d33d2 100644
--- a/include/asm-m68k/m5235.h
+++ b/include/asm-m68k/m5235.h
@@ -557,8 +557,8 @@
 #define CCM_RCON_MODE			(0x0001)
 
 /* Bit definitions and macros for CCM_CIR */
-#define CCM_CIR_PIN(x)			(((x)&0x03FF)<<6)
-#define CCM_CIR_PRN(x)			((x)&0x003F)
+#define CCM_CIR_PIN(x)			(((x) & 0xFFC0) >> 6)
+#define CCM_CIR_PRN(x)			((x) & 0x003F)
 
 /*********************************************************************
 * PLL Clock Module
diff --git a/include/asm-m68k/m5301x.h b/include/asm-m68k/m5301x.h
index 80cefc40aa..0920a0dc2a 100644
--- a/include/asm-m68k/m5301x.h
+++ b/include/asm-m68k/m5301x.h
@@ -254,7 +254,7 @@
 #define CCM_MISCCR_PLL_LOCK		(0x2000)
 #define CCM_MISCCR_LIMP			(0x1000)
 #define CCM_MISCCR_BME			(0x8000)
-#define CCM_MISCCR_BMT_MASK		(0xF8FF)
+#define CCM_MISCCR_BMT_UNMASK		(0xF8FF)
 #define CCM_MISCCR_BMT(x)		(((x) & 0x0007) << 8)
 #define CCM_MISCCR_BMT_512		(0x0700)
 #define CCM_MISCCR_BMT_1024		(0x0600)
@@ -330,32 +330,32 @@
 
 #define GPIO_PAR_CS5			(0x40)
 #define GPIO_PAR_CS4			(0x10)
-#define GPIO_PAR_CS1_MASK		(0xF3)
+#define GPIO_PAR_CS1_UNMASK		(0xF3)
 #define GPIO_PAR_CS1_CS1		(0x0C)
 #define GPIO_PAR_CS1_SDCS1		(0x08)
-#define GPIO_PAR_CS0_MASK		(0xFC)
+#define GPIO_PAR_CS0_UNMASK		(0xFC)
 #define GPIO_PAR_CS0_CS0		(0x03)
 #define GPIO_PAR_CS0_CS4		(0x02)
 
-#define GPIO_PAR_DSPIH_SIN_MASK		(0x3F)
+#define GPIO_PAR_DSPIH_SIN_UNMASK	(0x3F)
 #define GPIO_PAR_DSPIH_SIN		(0xC0)
 #define GPIO_PAR_DSPIH_SIN_U2RXD	(0x80)
-#define GPIO_PAR_DSPIH_SOUT_MASK	(0xCF)
+#define GPIO_PAR_DSPIH_SOUT_UNMASK	(0xCF)
 #define GPIO_PAR_DSPIH_SOUT		(0x30)
 #define GPIO_PAR_DSPIH_SOUT_U2TXD	(0x20)
-#define GPIO_PAR_DSPIH_SCK_MASK		(0xF3)
+#define GPIO_PAR_DSPIH_SCK_UNMASK	(0xF3)
 #define GPIO_PAR_DSPIH_SCK		(0x0C)
 #define GPIO_PAR_DSPIH_SCK_U2CTS	(0x08)
-#define GPIO_PAR_DSPIH_PCS0_MASK	(0xFC)
+#define GPIO_PAR_DSPIH_PCS0_UNMASK	(0xFC)
 #define GPIO_PAR_DSPIH_PCS0		(0x03)
 #define GPIO_PAR_DSPIH_PCS0_U2RTS	(0x02)
 
-#define GPIO_PAR_DSPIL_PCS1_MASK	(0x3F)
+#define GPIO_PAR_DSPIL_PCS1_UNMASK	(0x3F)
 #define GPIO_PAR_DSPIL_PCS1		(0xC0)
-#define GPIO_PAR_DSPIL_PCS2_MASK	(0xCF)
+#define GPIO_PAR_DSPIL_PCS2_UNMASK	(0xCF)
 #define GPIO_PAR_DSPIL_PCS2		(0x30)
 #define GPIO_PAR_DSPIL_PCS2_USBH_OC	(0x20)
-#define GPIO_PAR_DSPIL_PCS3_MASK	(0xF3)
+#define GPIO_PAR_DSPIL_PCS3_UNMASK	(0xF3)
 #define GPIO_PAR_DSPIL_PCS3		(0x0C)
 #define GPIO_PAR_DSPIL_PCS3_USBH_EN	(0x08)
 
@@ -365,30 +365,30 @@
 #define GPIO_PAR_FEC0_RMII_FEC		(0x01)
 
 /* GPIO_PAR_FECI2C */
-#define GPIO_PAR_FECI2C_RMII0_MASK	(0x3F)
+#define GPIO_PAR_FECI2C_RMII0_UNMASK	(0x3F)
 #define GPIO_PAR_FECI2C_MDC0		(0x80)
 #define GPIO_PAR_FECI2C_MDIO0		(0x40)
-#define GPIO_PAR_FECI2C_RMII1_MASK	(0xCF)
+#define GPIO_PAR_FECI2C_RMII1_UNMASK	(0xCF)
 #define GPIO_PAR_FECI2C_MDC1		(0x20)
 #define GPIO_PAR_FECI2C_MDIO1		(0x10)
-#define GPIO_PAR_FECI2C_SDA_MASK	(0xF3)
+#define GPIO_PAR_FECI2C_SDA_UNMASK	(0xF3)
 #define GPIO_PAR_FECI2C_SDA(x)		(((x) & 0x03) << 2)
 #define GPIO_PAR_FECI2C_SDA_SDA		(0x0C)
 #define GPIO_PAR_FECI2C_SDA_U2TXD	(0x08)
 #define GPIO_PAR_FECI2C_SDA_MDIO1	(0x04)
-#define GPIO_PAR_FECI2C_SCL_MASK	(0xFC)
+#define GPIO_PAR_FECI2C_SCL_UNMASK	(0xFC)
 #define GPIO_PAR_FECI2C_SCL(x)		((x) & 0x03)
 #define GPIO_PAR_FECI2C_SCL_SCL		(0x03)
 #define GPIO_PAR_FECI2C_SCL_U2RXD	(0x02)
 #define GPIO_PAR_FECI2C_SCL_MDC1	(0x01)
 
-#define GPIO_PAR_IRQ0H_IRQ07_MASK	(0x3F)
-#define GPIO_PAR_IRQ0H_IRQ06_MASK	(0xCF)
+#define GPIO_PAR_IRQ0H_IRQ07_UNMASK	(0x3F)
+#define GPIO_PAR_IRQ0H_IRQ06_UNMASK	(0xCF)
 #define GPIO_PAR_IRQ0H_IRQ06_USBCLKIN	(0x10)
-#define GPIO_PAR_IRQ0H_IRQ04_MASK	(0xFC)
+#define GPIO_PAR_IRQ0H_IRQ04_UNMASK	(0xFC)
 #define GPIO_PAR_IRQ0H_IRQ04_DREQ0	(0x02)
 
-#define GPIO_PAR_IRQ0L_IRQ01_MASK	(0xF3)
+#define GPIO_PAR_IRQ0L_IRQ01_UNMASK	(0xF3)
 #define GPIO_PAR_IRQ0L_IRQ01_DREQ1	(0x08)
 
 #define GPIO_PAR_IRQ1H_IRQ17_DDATA3	(0x40)
@@ -401,24 +401,24 @@
 #define GPIO_PAR_IRQ1L_IRQ11_PST1	(0x04)
 #define GPIO_PAR_IRQ1L_IRQ10_PST0	(0x01)
 
-#define GPIO_PAR_SIMP1H_DATA1_MASK	(0x3F)
+#define GPIO_PAR_SIMP1H_DATA1_UNMASK	(0x3F)
 #define GPIO_PAR_SIMP1H_DATA1_SIMDATA1	(0xC0)
 #define GPIO_PAR_SIMP1H_DATA1_SSITXD	(0x80)
 #define GPIO_PAR_SIMP1H_DATA1_U1TXD	(0x40)
-#define GPIO_PAR_SIMP1H_VEN1_MASK	(0xCF)
+#define GPIO_PAR_SIMP1H_VEN1_UNMASK	(0xCF)
 #define GPIO_PAR_SIMP1H_VEN1_SIMVEN1	(0x30)
 #define GPIO_PAR_SIMP1H_VEN1_SSIRXD	(0x20)
 #define GPIO_PAR_SIMP1H_VEN1_U1RXD	(0x10)
-#define GPIO_PAR_SIMP1H_RST1_MASK	(0xF3)
+#define GPIO_PAR_SIMP1H_RST1_UNMASK	(0xF3)
 #define GPIO_PAR_SIMP1H_RST1_SIMRST1	(0x0C)
 #define GPIO_PAR_SIMP1H_RST1_SSIFS	(0x08)
 #define GPIO_PAR_SIMP1H_RST1_U1RTS	(0x04)
-#define GPIO_PAR_SIMP1H_PD1_MASK	(0xFC)
+#define GPIO_PAR_SIMP1H_PD1_UNMASK	(0xFC)
 #define GPIO_PAR_SIMP1H_PD1_SIMPD1	(0x03)
 #define GPIO_PAR_SIMP1H_PD1_SSIBCLK	(0x02)
 #define GPIO_PAR_SIMP1H_PD1_U1CTS	(0x01)
 
-#define GPIO_PAR_SIMP1L_CLK_MASK	(0x3F)
+#define GPIO_PAR_SIMP1L_CLK_UNMASK	(0x3F)
 #define GPIO_PAR_SIMP1L_CLK_CLK1	(0xC0)
 #define GPIO_PAR_SIMP1L_CLK_SSIMCLK	(0x80)
 
@@ -432,19 +432,19 @@
 #define GPIO_PAR_TIN2(x)		(((x) & 0x03) << 4)
 #define GPIO_PAR_TIN1(x)		(((x) & 0x03) << 2)
 #define GPIO_PAR_TIN0(x)		((x) & 0x03)
-#define GPIO_PAR_TIN3_MASK		(0x3F)
+#define GPIO_PAR_TIN3_UNMASK		(0x3F)
 #define GPIO_PAR_TIN3_TIN3		(0xC0)
 #define GPIO_PAR_TIN3_TOUT3		(0x80)
 #define GPIO_PAR_TIN3_IRQ03		(0x40)
-#define GPIO_PAR_TIN2_MASK		(0xCF)
+#define GPIO_PAR_TIN2_UNMASK		(0xCF)
 #define GPIO_PAR_TIN2_TIN2		(0x30)
 #define GPIO_PAR_TIN2_TOUT2		(0x20)
 #define GPIO_PAR_TIN2_IRQ02		(0x10)
-#define GPIO_PAR_TIN1_MASK		(0xF3)
+#define GPIO_PAR_TIN1_UNMASK		(0xF3)
 #define GPIO_PAR_TIN1_TIN1		(0x0C)
 #define GPIO_PAR_TIN1_TOUT1		(0x08)
 #define GPIO_PAR_TIN1_DACK1		(0x04)
-#define GPIO_PAR_TIN0_MASK		(0xFC)
+#define GPIO_PAR_TIN0_UNMASK		(0xFC)
 #define GPIO_PAR_TIN0_TIN0		(0x03)
 #define GPIO_PAR_TIN0_TOUT0		(0x02)
 #define GPIO_PAR_TIN0_CODEC_ALTCLK	(0x01)
@@ -455,10 +455,10 @@
 #define GPIO_PAR_UART_U0RXD		(0x10)
 #define GPIO_PAR_UART_RTS0(x)		(((x) & 0x03) << 2)
 #define GPIO_PAR_UART_CTS0(x)		((x) & 0x03)
-#define GPIO_PAR_UART_RTS0_MASK		(0xF3)
+#define GPIO_PAR_UART_RTS0_UNMASK	(0xF3)
 #define GPIO_PAR_UART_RTS0_U0RTS	(0x0C)
 #define GPIO_PAR_UART_RTS0_USBO_VBOC	(0x08)
-#define GPIO_PAR_UART_CTS0_MASK		(0xFC)
+#define GPIO_PAR_UART_CTS0_UNMASK	(0xFC)
 #define GPIO_PAR_UART_CTS0_U0CTS	(0x03)
 #define GPIO_PAR_UART_CTS0_USB0_VBEN	(0x02)
 #define GPIO_PAR_UART_CTS0_USB_PULLUP	(0x01)
@@ -476,20 +476,20 @@
 #define GPIO_PAR_SSIH_TXD(x)		(((x) & 0x03) << 4)
 #define GPIO_PAR_SSIH_FS(x)		(((x) & 0x03) << 2)
 #define GPIO_PAR_SSIH_MCLK(x)		((x) & 0x03)
-#define GPIO_PAR_SSIH_RXD_MASK		(0x3F)
+#define GPIO_PAR_SSIH_RXD_UNMASK	(0x3F)
 #define GPIO_PAR_SSIH_RXD_SSIRXD	(0xC0)
 #define GPIO_PAR_SSIH_RXD_U1RXD		(0x40)
-#define GPIO_PAR_SSIH_TXD_MASK		(0xCF)
+#define GPIO_PAR_SSIH_TXD_UNMASK	(0xCF)
 #define GPIO_PAR_SSIH_TXD_SSIRXD	(0x30)
 #define GPIO_PAR_SSIH_TXD_U1TXD		(0x10)
-#define GPIO_PAR_SSIH_FS_MASK		(0xF3)
+#define GPIO_PAR_SSIH_FS_UNMASK		(0xF3)
 #define GPIO_PAR_SSIH_FS_SSIFS		(0x0C)
 #define GPIO_PAR_SSIH_FS_U1RTS		(0x04)
-#define GPIO_PAR_SSIH_MCLK_MASK		(0xFC)
+#define GPIO_PAR_SSIH_MCLK_UNMASK	(0xFC)
 #define GPIO_PAR_SSIH_MCLK_SSIMCLK	(0x03)
 #define GPIO_PAR_SSIH_MCLK_SSICLKIN	(0x01)
 
-#define GPIO_PAR_SSIL_MASK		(0x3F)
+#define GPIO_PAR_SSIL_UNMASK		(0x3F)
 #define GPIO_PAR_SSIL_BCLK		(0xC0)
 #define GPIO_PAR_SSIL_U1CTS		(0x40)
 
@@ -497,40 +497,40 @@
 #define GPIO_MSCR_MSCR2(x)		(((x) & 0x07) << 5)
 #define GPIO_MSCR_MSCR3(x)		(((x) & 0x07) << 5)
 #define GPIO_MSCR_MSCR4(x)		(((x) & 0x07) << 5)
-#define GPIO_MSCR_MSCRn_MASK		(0x1F)
+#define GPIO_MSCR_MSCRn_UNMASK		(0x1F)
 #define GPIO_MSCR_MSCRn_SDR		(0xE0)
 #define GPIO_MSCR_MSCRn_25VDDR		(0x60)
 #define GPIO_MSCR_MSCRn_18VDDR_FULL	(0x20)
 #define GPIO_MSCR_MSCRn_18VDDR_HALF	(0x00)
 
 #define GPIO_MSCR_MSCR5(x)		(((x) & 0x07) << 2)
-#define GPIO_MSCR_MSCR5_MASK		(0xE3)
+#define GPIO_MSCR_MSCR5_UNMASK		(0xE3)
 #define GPIO_MSCR_MSCR5_SDR		(0x1C)
 #define GPIO_MSCR_MSCR5_25VDDR		(0x0C)
 #define GPIO_MSCR_MSCR5_18VDDR_FULL	(0x04)
 #define GPIO_MSCR_MSCR5_18VDDR_HALF	(0x00)
 
-#define GPIO_SRCR_DSPI_MASK		(0xFC)
+#define GPIO_SRCR_DSPI_UNMASK		(0xFC)
 #define GPIO_SRCR_DSPI(x)		((x) & 0x03)
-#define GPIO_SRCR_I2C_MASK		(0xFC)
+#define GPIO_SRCR_I2C_UNMASK		(0xFC)
 #define GPIO_SRCR_I2C(x)		((x) & 0x03)
-#define GPIO_SRCR_IRQ_IRQ0_MASK		(0xF3)
+#define GPIO_SRCR_IRQ_IRQ0_UNMASK	(0xF3)
 #define GPIO_SRCR_IRQ_IRQ0(x)		(((x) & 0x03) << 2)
-#define GPIO_SRCR_IRQ_IRQ1DBG_MASK	(0xFC)
+#define GPIO_SRCR_IRQ_IRQ1DBG_UNMASK	(0xFC)
 #define GPIO_SRCR_IRQ_IRQ1DBG(x)	((x) & 0x03)
-#define GPIO_SRCR_SIM_SIMP0_MASK	(0xF3)
+#define GPIO_SRCR_SIM_SIMP0_UNMASK	(0xF3)
 #define GPIO_SRCR_SIM_SIMP0(x)		(((x) & 0x03) << 2)
-#define GPIO_SRCR_SIM_SIMP1_MASK	(0xFC)
+#define GPIO_SRCR_SIM_SIMP1_UNMASK	(0xFC)
 #define GPIO_SRCR_SIM_SIMP1(x)		((x) & 0x03)
-#define GPIO_SRCR_TIMER_MASK		(0xFC)
+#define GPIO_SRCR_TIMER_UNMASK		(0xFC)
 #define GPIO_SRCR_TIMER(x)		((x) & 0x03)
-#define GPIO_SRCR_UART2_MASK		(0xF3)
+#define GPIO_SRCR_UART2_UNMASK		(0xF3)
 #define GPIO_SRCR_UART2(x)		(((x) & 0x03) << 2)
-#define GPIO_SRCR_UART0_MASK		(0xFC)
+#define GPIO_SRCR_UART0_UNMASK		(0xFC)
 #define GPIO_SRCR_UART0(x)		((x) & 0x03)
-#define GPIO_SRCR_SDHC_MASK		(0xFC)
+#define GPIO_SRCR_SDHC_UNMASK		(0xFC)
 #define GPIO_SRCR_SDHC(x)		((x) & 0x03)
-#define GPIO_SRCR_SSI_MASK		(0xFC)
+#define GPIO_SRCR_SSI_UNMASK		(0xFC)
 #define GPIO_SRCR_SSI(x)		((x) & 0x03)
 
 #define SRCR_HIGHEST			(0x03)
@@ -538,11 +538,11 @@
 #define SRCR_LOW			(0x01)
 #define SRCR_LOWEST			(0x00)
 
-#define GPIO_DSCR_FEC_RMIICLK_MASK	(0xCF)
+#define GPIO_DSCR_FEC_RMIICLK_UNMASK	(0xCF)
 #define GPIO_DSCR_FEC_RMIICLK(x)	(((x) & 0x03) << 4)
-#define GPIO_DSCR_FEC_RMII0_MASK	(0xF3)
+#define GPIO_DSCR_FEC_RMII0_UNMASK	(0xF3)
 #define GPIO_DSCR_FEC_RMII0(x)		(((x) & 0x03) << 2)
-#define GPIO_DSCR_FEC_RMII1_MASK	(0xFC)
+#define GPIO_DSCR_FEC_RMII1_UNMASK	(0xFC)
 #define GPIO_DSCR_FEC_RMII1(x)		((x) & 0x03)
 
 #define DSCR_50PF			(0x03)
@@ -572,18 +572,18 @@
 #define PLL_PCR_LOL_IRQ			(0x00004000)
 #define PLL_PCR_LOL_RE			(0x00002000)
 #define PLL_PCR_LOL_EN			(0x00001000)
-#define PLL_PCR_REFDIV_MASK		(0xFFFFF8FF)
+#define PLL_PCR_REFDIV_UNMASK		(0xFFFFF8FF)
 #define PLL_PCR_REFDIV(x)		(((x) & 0x07) << 8)
-#define PLL_PCR_FBDIV_MASK		(0xFFFFFFC0)
+#define PLL_PCR_FBDIV_UNMASK		(0xFFFFFFC0)
 #define PLL_PCR_FBDIV(x)		((x) & 0x3F)
 
-#define PLL_PDR_OUTDIV4_MASK		(0x0FFF)
+#define PLL_PDR_OUTDIV4_UNMASK		(0x0FFF)
 #define PLL_PDR_OUTDIV4(x)		(((x) & 0x0000000F) << 12)
-#define PLL_PDR_OUTDIV3_MASK		(0xF0FF)
+#define PLL_PDR_OUTDIV3_UNMASK		(0xF0FF)
 #define PLL_PDR_OUTDIV3(x)		(((x) & 0x0000000F) << 8)
-#define PLL_PDR_OUTDIV2_MASK		(0xFF0F)
+#define PLL_PDR_OUTDIV2_UNMASK		(0xFF0F)
 #define PLL_PDR_OUTDIV2(x)		(((x) & 0x0000000F) << 4)
-#define PLL_PDR_OUTDIV1_MASK		(0xFFF0)
+#define PLL_PDR_OUTDIV1_UNMASK		(0xFFF0)
 #define PLL_PDR_OUTDIV1(x)		((x) & 0x0000000F)
 #define PLL_PDR_USB(x)			PLL_PDR_OUTDIV4(x)
 #define PLL_PDR_SDRAM(x)		PLL_PDR_OUTDIV3(x)
diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h
index 596662191c..dfddde62ad 100644
--- a/include/asm-m68k/m5445x.h
+++ b/include/asm-m68k/m5445x.h
@@ -286,13 +286,13 @@
 /* Bit definitions and macros for PAR_FEC */
 #define GPIO_PAR_FEC_FEC0(x)		(((x)&0x07))
 #define GPIO_PAR_FEC_FEC1(x)		(((x)&0x07)<<4)
-#define GPIO_PAR_FEC_FEC1_MASK		(0x8F)
+#define GPIO_PAR_FEC_FEC1_UNMASK	(0x8F)
 #define GPIO_PAR_FEC_FEC1_MII		(0x70)
 #define GPIO_PAR_FEC_FEC1_RMII_GPIO	(0x30)
 #define GPIO_PAR_FEC_FEC1_RMII_ATA	(0x20)
 #define GPIO_PAR_FEC_FEC1_ATA		(0x10)
 #define GPIO_PAR_FEC_FEC1_GPIO		(0x00)
-#define GPIO_PAR_FEC_FEC0_MASK		(0xF8)
+#define GPIO_PAR_FEC_FEC0_UNMASK	(0xF8)
 #define GPIO_PAR_FEC_FEC0_MII		(0x07)
 #define GPIO_PAR_FEC_FEC0_RMII_GPIO	(0x03)
 #define GPIO_PAR_FEC_FEC0_RMII_ULPI	(0x02)
@@ -304,15 +304,15 @@
 #define GPIO_PAR_DMA_DACK0(x)		(((x)&0x03)<<2)
 #define GPIO_PAR_DMA_DREQ1(x)		(((x)&0x03)<<4)
 #define GPIO_PAR_DMA_DACK1(x)		(((x)&0x03)<<6)
-#define GPIO_PAR_DMA_DACK1_MASK		(0x3F)
+#define GPIO_PAR_DMA_DACK1_UNMASK	(0x3F)
 #define GPIO_PAR_DMA_DACK1_DACK1	(0xC0)
 #define GPIO_PAR_DMA_DACK1_ULPI_DIR	(0x40)
 #define GPIO_PAR_DMA_DACK1_GPIO		(0x00)
-#define GPIO_PAR_DMA_DREQ1_MASK		(0xCF)
+#define GPIO_PAR_DMA_DREQ1_UNMASK	(0xCF)
 #define GPIO_PAR_DMA_DREQ1_DREQ1	(0x30)
 #define GPIO_PAR_DMA_DREQ1_USB_CLKIN	(0x10)
 #define GPIO_PAR_DMA_DREQ1_GPIO		(0x00)
-#define GPIO_PAR_DMA_DACK0_MASK		(0xF3)
+#define GPIO_PAR_DMA_DACK0_UNMASK	(0xF3)
 #define GPIO_PAR_DMA_DACK0_DACK1	(0x0C)
 #define GPIO_PAR_DMA_DACK0_ULPI_DIR	(0x04)
 #define GPIO_PAR_DMA_DACK0_GPIO		(0x00)
@@ -330,7 +330,7 @@
 #define GPIO_PAR_FBCTL_TA_GPIO		(0x00)
 #define GPIO_PAR_FBCTL_RW_RW		(0x20)
 #define GPIO_PAR_FBCTL_RW_GPIO		(0x00)
-#define GPIO_PAR_FBCTL_TS_MASK		(0xE7)
+#define GPIO_PAR_FBCTL_TS_UNMASK	(0xE7)
 #define GPIO_PAR_FBCTL_TS_TS		(0x18)
 #define GPIO_PAR_FBCTL_TS_ALE		(0x10)
 #define GPIO_PAR_FBCTL_TS_TBST		(0x08)
@@ -364,11 +364,11 @@
 #define GPIO_PAR_BE_BS1			(0x04)
 #define GPIO_PAR_BE_BS2(x)		(((x)&0x03)<<4)
 #define GPIO_PAR_BE_BS3(x)		(((x)&0x03)<<6)
-#define GPIO_PAR_BE_BE3_MASK		(0x3F)
+#define GPIO_PAR_BE_BE3_UNMASK		(0x3F)
 #define GPIO_PAR_BE_BE3_BE3		(0xC0)
 #define GPIO_PAR_BE_BE3_TSIZ1		(0x80)
 #define GPIO_PAR_BE_BE3_GPIO		(0x00)
-#define GPIO_PAR_BE_BE2_MASK		(0xCF)
+#define GPIO_PAR_BE_BE2_UNMASK		(0xCF)
 #define GPIO_PAR_BE_BE2_BE2		(0x30)
 #define GPIO_PAR_BE_BE2_TSIZ0		(0x20)
 #define GPIO_PAR_BE_BE2_GPIO		(0x00)
@@ -393,22 +393,22 @@
 #define GPIO_PAR_TIMER_T1IN(x)		(((x)&0x03)<<2)
 #define GPIO_PAR_TIMER_T2IN(x)		(((x)&0x03)<<4)
 #define GPIO_PAR_TIMER_T3IN(x)		(((x)&0x03)<<6)
-#define GPIO_PAR_TIMER_T3IN_MASK	(0x3F)
+#define GPIO_PAR_TIMER_T3IN_UNMASK	(0x3F)
 #define GPIO_PAR_TIMER_T3IN_T3IN	(0xC0)
 #define GPIO_PAR_TIMER_T3IN_T3OUT	(0x80)
 #define GPIO_PAR_TIMER_T3IN_U2RXD	(0x40)
 #define GPIO_PAR_TIMER_T3IN_GPIO	(0x00)
-#define GPIO_PAR_TIMER_T2IN_MASK	(0xCF)
+#define GPIO_PAR_TIMER_T2IN_UNMASK	(0xCF)
 #define GPIO_PAR_TIMER_T2IN_T2IN	(0x30)
 #define GPIO_PAR_TIMER_T2IN_T2OUT	(0x20)
 #define GPIO_PAR_TIMER_T2IN_U2TXD	(0x10)
 #define GPIO_PAR_TIMER_T2IN_GPIO	(0x00)
-#define GPIO_PAR_TIMER_T1IN_MASK	(0xF3)
+#define GPIO_PAR_TIMER_T1IN_UNMASK	(0xF3)
 #define GPIO_PAR_TIMER_T1IN_T1IN	(0x0C)
 #define GPIO_PAR_TIMER_T1IN_T1OUT	(0x08)
 #define GPIO_PAR_TIMER_T1IN_U2CTS	(0x04)
 #define GPIO_PAR_TIMER_T1IN_GPIO	(0x00)
-#define GPIO_PAR_TIMER_T0IN_MASK	(0xFC)
+#define GPIO_PAR_TIMER_T0IN_UNMASK	(0xFC)
 #define GPIO_PAR_TIMER_T0IN_T0IN	(0x03)
 #define GPIO_PAR_TIMER_T0IN_T0OUT	(0x02)
 #define GPIO_PAR_TIMER_T0IN_U2RTS	(0x01)
@@ -417,12 +417,12 @@
 /* Bit definitions and macros for PAR_USB */
 #define GPIO_PAR_USB_VBUSOC(x)		(((x)&0x03))
 #define GPIO_PAR_USB_VBUSEN(x)		(((x)&0x03)<<2)
-#define GPIO_PAR_USB_VBUSEN_MASK	(0xF3)
+#define GPIO_PAR_USB_VBUSEN_UNMASK	(0xF3)
 #define GPIO_PAR_USB_VBUSEN_VBUSEN	(0x0C)
 #define GPIO_PAR_USB_VBUSEN_USBPULLUP	(0x08)
 #define GPIO_PAR_USB_VBUSEN_ULPI_NXT	(0x04)
 #define GPIO_PAR_USB_VBUSEN_GPIO	(0x00)
-#define GPIO_PAR_USB_VBUSOC_MASK	(0xFC)
+#define GPIO_PAR_USB_VBUSOC_UNMASK	(0xFC)
 #define GPIO_PAR_USB_VBUSOC_VBUSOC	(0x03)
 #define GPIO_PAR_USB_VBUSOC_ULPI_STP	(0x01)
 #define GPIO_PAR_USB_VBUSOC_GPIO	(0x00)
@@ -460,11 +460,11 @@
 #define GPIO_PAR_FECI2C_MDC0		(0x0040)
 #define GPIO_PAR_FECI2C_MDIO1(x)	(((x)&0x0003)<<8)
 #define GPIO_PAR_FECI2C_MDC1(x)		(((x)&0x0003)<<10)
-#define GPIO_PAR_FECI2C_MDC1_MASK	(0xF3FF)
+#define GPIO_PAR_FECI2C_MDC1_UNMASK	(0xF3FF)
 #define GPIO_PAR_FECI2C_MDC1_MDC1	(0x0C00)
 #define GPIO_PAR_FECI2C_MDC1_ATA_DIOR	(0x0800)
 #define GPIO_PAR_FECI2C_MDC1_GPIO	(0x0000)
-#define GPIO_PAR_FECI2C_MDIO1_MASK	(0xFCFF)
+#define GPIO_PAR_FECI2C_MDIO1_UNMASK	(0xFCFF)
 #define GPIO_PAR_FECI2C_MDIO1_MDIO1	(0x0300)
 #define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW	(0x0200)
 #define GPIO_PAR_FECI2C_MDIO1_GPIO	(0x0000)
@@ -472,11 +472,11 @@
 #define GPIO_PAR_FECI2C_MDC0_GPIO	(0x0000)
 #define GPIO_PAR_FECI2C_MDIO0_MDIO0	(0x0010)
 #define GPIO_PAR_FECI2C_MDIO0_GPIO	(0x0000)
-#define GPIO_PAR_FECI2C_SCL_MASK	(0xFFF3)
+#define GPIO_PAR_FECI2C_SCL_UNMASK	(0xFFF3)
 #define GPIO_PAR_FECI2C_SCL_SCL		(0x000C)
 #define GPIO_PAR_FECI2C_SCL_U2TXD	(0x0004)
 #define GPIO_PAR_FECI2C_SCL_GPIO	(0x0000)
-#define GPIO_PAR_FECI2C_SDA_MASK	(0xFFFC)
+#define GPIO_PAR_FECI2C_SDA_UNMASK	(0xFFFC)
 #define GPIO_PAR_FECI2C_SDA_SDA		(0x0003)
 #define GPIO_PAR_FECI2C_SDA_U2RXD	(0x0001)
 #define GPIO_PAR_FECI2C_SDA_GPIO	(0x0000)
@@ -487,19 +487,19 @@
 #define GPIO_PAR_SSI_SRXD(x)		(((x)&0x0003)<<4)
 #define GPIO_PAR_SSI_FS(x)		(((x)&0x0003)<<6)
 #define GPIO_PAR_SSI_BCLK(x)		(((x)&0x0003)<<8)
-#define GPIO_PAR_SSI_BCLK_MASK		(0xFCFF)
+#define GPIO_PAR_SSI_BCLK_UNMASK	(0xFCFF)
 #define GPIO_PAR_SSI_BCLK_BCLK		(0x0300)
 #define GPIO_PAR_SSI_BCLK_U1CTS		(0x0200)
 #define GPIO_PAR_SSI_BCLK_GPIO		(0x0000)
-#define GPIO_PAR_SSI_FS_MASK		(0xFF3F)
+#define GPIO_PAR_SSI_FS_UNMASK		(0xFF3F)
 #define GPIO_PAR_SSI_FS_FS		(0x00C0)
 #define GPIO_PAR_SSI_FS_U1RTS		(0x0080)
 #define GPIO_PAR_SSI_FS_GPIO		(0x0000)
-#define GPIO_PAR_SSI_SRXD_MASK		(0xFFCF)
+#define GPIO_PAR_SSI_SRXD_UNMASK	(0xFFCF)
 #define GPIO_PAR_SSI_SRXD_SRXD		(0x0030)
 #define GPIO_PAR_SSI_SRXD_U1RXD		(0x0020)
 #define GPIO_PAR_SSI_SRXD_GPIO		(0x0000)
-#define GPIO_PAR_SSI_STXD_MASK		(0xFFF3)
+#define GPIO_PAR_SSI_STXD_UNMASK	(0xFFF3)
 #define GPIO_PAR_SSI_STXD_STXD		(0x000C)
 #define GPIO_PAR_SSI_STXD_U1TXD		(0x0008)
 #define GPIO_PAR_SSI_STXD_GPIO		(0x0000)
@@ -552,7 +552,7 @@
 #define GPIO_PAR_PCI_GNT1		(0x0400)
 #define GPIO_PAR_PCI_GNT2		(0x1000)
 #define GPIO_PAR_PCI_GNT3(x)		(((x)&0x0003)<<14)
-#define GPIO_PAR_PCI_GNT3_MASK		(0x3FFF)
+#define GPIO_PAR_PCI_GNT3_UNMASK	(0x3FFF)
 #define GPIO_PAR_PCI_GNT3_GNT3		(0xC000)
 #define GPIO_PAR_PCI_GNT3_ATA_DMACK	(0x8000)
 #define GPIO_PAR_PCI_GNT3_GPIO		(0x0000)
@@ -562,7 +562,7 @@
 #define GPIO_PAR_PCI_GNT1_GPIO		(0x0000)
 #define GPIO_PAR_PCI_GNT0_GNT0		(0x0100)
 #define GPIO_PAR_PCI_GNT0_GPIO		(0x0000)
-#define GPIO_PAR_PCI_REQ3_MASK		(0xFF3F)
+#define GPIO_PAR_PCI_REQ3_UNMASK	(0xFF3F)
 #define GPIO_PAR_PCI_REQ3_REQ3		(0x00C0)
 #define GPIO_PAR_PCI_REQ3_ATA_INTRQ	(0x0080)
 #define GPIO_PAR_PCI_REQ3_GPIO		(0x0000)
@@ -578,22 +578,22 @@
 #define GPIO_MSCR_SDRAM_SDCLK(x)	(((x)&0x03)<<2)
 #define GPIO_MSCR_SDRAM_SDDQS(x)	(((x)&0x03)<<4)
 #define GPIO_MSCR_SDRAM_SDDATA(x)	(((x)&0x03)<<6)
-#define GPIO_MSCR_SDRAM_SDDATA_MASK	(0x3F)
+#define GPIO_MSCR_SDRAM_SDDATA_UNMASK	(0x3F)
 #define GPIO_MSCR_SDRAM_SDDATA_DDR1	(0xC0)
 #define GPIO_MSCR_SDRAM_SDDATA_DDR2	(0x80)
 #define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR	(0x40)
 #define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR	(0x00)
-#define GPIO_MSCR_SDRAM_SDDQS_MASK	(0xCF)
+#define GPIO_MSCR_SDRAM_SDDQS_UNMASK	(0xCF)
 #define GPIO_MSCR_SDRAM_SDDQS_DDR1	(0x30)
 #define GPIO_MSCR_SDRAM_SDDQS_DDR2	(0x20)
 #define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR	(0x10)
 #define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR	(0x00)
-#define GPIO_MSCR_SDRAM_SDCLK_MASK	(0xF3)
+#define GPIO_MSCR_SDRAM_SDCLK_UNMASK	(0xF3)
 #define GPIO_MSCR_SDRAM_SDCLK_DDR1	(0x0C)
 #define GPIO_MSCR_SDRAM_SDCLK_DDR2	(0x08)
 #define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR	(0x04)
 #define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR	(0x00)
-#define GPIO_MSCR_SDRAM_SDCTL_MASK	(0xFC)
+#define GPIO_MSCR_SDRAM_SDCTL_UNMASK	(0xFC)
 #define GPIO_MSCR_SDRAM_SDCTL_DDR1	(0x03)
 #define GPIO_MSCR_SDRAM_SDCTL_DDR2	(0x02)
 #define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR	(0x01)
diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h
index 8c5a742290..44befe9edf 100644
--- a/include/configs/BC3450.h
+++ b/include/configs/BC3450.h
@@ -471,13 +471,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
-# define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-# define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-# define CONFIG_SYS_HID0_INIT		0
-# define CONFIG_SYS_HID0_FINAL		0
-#endif
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
index a0b27a89c4..880cb4ee6b 100644
--- a/include/configs/EB+MCF-EV123.h
+++ b/include/configs/EB+MCF-EV123.h
@@ -208,6 +208,18 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+					 CF_CACR_CEIB | CF_CACR_DBWE | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 5ef0b7798e..5d3a744fff 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -30,6 +30,7 @@
  */
 
 #define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* (more precisely a MPC5200 CPU) */
 #define CONFIG_ICECUBE		1	/* ... on IceCube board */
 
 #define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
@@ -47,7 +48,6 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 
-#ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
 /*
  * PCI Mapping:
  * 0x40000000 - 0x4fffffff - PCI Memory
@@ -77,10 +77,6 @@
 #define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 #define CONFIG_NS8382X		1
 
-#else
-#define CONFIG_MII		1
-#endif
-
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -169,7 +165,6 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#if defined(CONFIG_MPC5200)
 /*
  * IPB Bus clocking configuration.
  */
@@ -178,7 +173,6 @@
 #else
 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 #endif
-#endif /* CONFIG_MPC5200 */
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
@@ -338,13 +332,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #if defined(CONFIG_LITE5200B)
 #define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index 32123d2f54..e6632acbe7 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -158,7 +158,7 @@
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
 #define CONFIG_SYS_SDRAM_CFG1		0x43711630
 #define CONFIG_SYS_SDRAM_CFG2		0x56670000
 #define CONFIG_SYS_SDRAM_CTRL		0xE1002000
@@ -207,6 +207,19 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /* Chipselect bank definitions */
 /*
  * CS0 - NOR Flash
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index 1801d9d7d5..6c6b5d6d57 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -302,6 +302,19 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 2b816ceae2..5c0dc842aa 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -237,6 +237,18 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index e3830e5369..33ac2859df 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -60,6 +60,7 @@
  * Command line configuration.
  */
 #include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
 #undef CONFIG_CMD_NET
 
 #define CONFIG_SYS_PROMPT		"=> "
@@ -165,6 +166,20 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(2) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 5e86e4cb90..b5af493b80 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -57,6 +57,7 @@
  */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_LOADB
 #define CONFIG_CMD_LOADS
 #define CONFIG_CMD_EXT2
@@ -95,11 +96,6 @@
 #	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
 #	undef CONFIG_DM9000_DEBUG
 
-#	define CONFIG_ETHADDR		00:e0:0c:bc:e5:60
-#	define CONFIG_IPADDR		10.82.121.249
-#	define CONFIG_NETMASK		255.255.252.0
-#	define CONFIG_SERVERIP		10.82.120.80
-#	define CONFIG_GATEWAYIP		10.82.123.254
 #	define CONFIG_OVERWRITE_ETHADDR_ONCE
 
 #	define CONFIG_EXTRA_ENV_SETTINGS		\
@@ -109,9 +105,9 @@
 		"u-boot=u-boot.bin\0"			\
 		"load=tftp ${loadaddr) ${u-boot}\0"	\
 		"upd=run load; run prog\0"		\
-		"prog=prot off 0 2ffff;"	\
-		"era 0 2ffff;"			\
-		"cp.b ${loadaddr} 0 ${filesize};"	\
+		"prog=prot off 0xff800000 0xff82ffff;"	\
+		"era 0xff800000 0xff82ffff;"		\
+		"cp.b ${loadaddr} 0xff800000 ${filesize};"	\
 		"save\0"				\
 		""
 #endif
@@ -231,6 +227,20 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(8) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
 /* Port configuration */
 #define CONFIG_SYS_FECI2C		0xF0
 
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
index df6970cdfa..206d1152ee 100644
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -64,6 +64,7 @@
  * Command line configuration.
  */
 #include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
 #undef CONFIG_CMD_NET
 #define CONFIG_CMD_LOADB
 #define CONFIG_CMD_LOADS
@@ -179,6 +180,20 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(2) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
 /* Port configuration */
 #define CONFIG_SYS_FECI2C		0xF0
 
diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
index 50b3ab2808..798949cc56 100644
--- a/include/configs/M5271EVB.h
+++ b/include/configs/M5271EVB.h
@@ -72,6 +72,7 @@
  */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_MII
@@ -229,6 +230,19 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /* Chip Select 0  : Boot Flash */
 #define CONFIG_SYS_CS0_BASE	0xFFE00000
 #define CONFIG_SYS_CS0_MASK	0x001F0001
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index f824158a69..f704bb3ff7 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -74,6 +74,7 @@
  */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
@@ -211,6 +212,19 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index b380159812..981670ac06 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -72,6 +72,7 @@
 /* Available command configuration */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
@@ -121,11 +122,6 @@
 #define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFF0)
 #define CONFIG_SYS_I2C_PINMUX_SET	(0x000F)
 
-#ifdef CONFIG_MCFFEC
-#define CONFIG_ETHADDR		00:06:3b:01:41:55
-#define CONFIG_ETH1ADDR		00:0e:0c:bc:e5:60
-#endif
-
 #define CONFIG_SYS_PROMPT		"-> "
 #define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
 
@@ -145,6 +141,23 @@
 #define CONFIG_SYS_MEMTEST_START	0x400
 #define CONFIG_SYS_MEMTEST_END		0x380000
 
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_NET_RETRY_COUNT	5
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif				/* FEC_ENET */
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=10000\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr} ${uboot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off ffe00000 ffe3ffff;"	\
+	"era ffe00000 ffe3ffff;"		\
+	"cp.b ${loadaddr} ffe00000 ${filesize};"\
+	"save\0"				\
+	""
+
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CLK			150000000
 
@@ -208,6 +221,19 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index 15590cfcd5..6e0aa14d3a 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -64,6 +64,7 @@
  * Command line configuration.
  */
 #include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
@@ -209,6 +210,18 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+					 CF_CACR_CEIB | CF_CACR_DBWE | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 30855bdaa2..d983a8fedb 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -69,6 +69,8 @@
 #	define CONFIG_MII_INIT		1
 #	define CONFIG_SYS_DISCOVER_PHY
 #	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_TX_ETH_BUFFER	8
+#	define CONFIG_SYS_FEC_BUF_USE_SRAM
 #	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #	define CONFIG_HAS_ETH1
 
@@ -166,7 +168,7 @@
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
 #define CONFIG_SYS_INIT_RAM_END		0x20000	/* End of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL	0x21
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
@@ -180,7 +182,7 @@
 #define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
 #define CONFIG_SYS_SDRAM_CFG1		0x43711630
 #define CONFIG_SYS_SDRAM_CFG2		0x56670000
-#define CONFIG_SYS_SDRAM_CTRL		0xE1002000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
 #define CONFIG_SYS_SDRAM_EMOD		0x80010000
 #define CONFIG_SYS_SDRAM_MODE		0x00CD0000
 
@@ -231,6 +233,17 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 8180c05e67..159b178f40 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -237,6 +237,17 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index 8652a80aa1..af1988ce0a 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -237,6 +237,17 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index a5acfd2846..a80d33047f 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -309,6 +309,21 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE		16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
+					 CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 7737284aab..5b4bba8c26 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -279,7 +279,7 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_END		0x8000	/* End of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL	0x221
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
@@ -408,6 +408,21 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE		16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
+					 CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index 4534002e47..d0077667f3 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -286,6 +286,22 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA + \
+					 CF_CACR_IDCM)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_BCINVA | \
+					 CF_CACR_IEC | CF_CACR_ICINVA)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index 971cb67bad..f23b8b0efa 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -272,6 +272,22 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA + \
+					 CF_CACR_IDCM)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_BCINVA | \
+					 CF_CACR_IEC | CF_CACR_ICINVA)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index f9687d2743..22de2075f9 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -50,7 +50,6 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 
-#ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
 /*
  * PCI Mapping:
  * 0x40000000 - 0x4fffffff - PCI Memory
@@ -75,7 +74,6 @@
 #define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 #undef  CONFIG_NS8382X
 
-#endif
 
 /* Partitions */
 #define CONFIG_DOS_PARTITION
@@ -111,9 +109,7 @@
 #define CONFIG_CMD_SNTP
 #define CONFIG_CMD_USB
 
-#if defined(CONFIG_MPC5200)
 #define CONFIG_CMD_PCI
-#endif
 
 
 /*
@@ -147,12 +143,10 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#if defined(CONFIG_MPC5200)
 /*
  * IPB Bus clocking configuration.
  */
 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-#endif
 /*
  * I2C configuration
  */
@@ -301,13 +295,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #if defined(CONFIG_BOOT_ROM)
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_BOOTROM_BASE
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
index 25f3a26f35..b69f015c7c 100644
--- a/include/configs/TASREG.h
+++ b/include/configs/TASREG.h
@@ -252,6 +252,17 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
index 3438abaeaa..6da18ebca1 100644
--- a/include/configs/TB5200.h
+++ b/include/configs/TB5200.h
@@ -430,13 +430,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 2154c7870e..107bff19ff 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -633,13 +633,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h
index 1daa5746ee..7510ab10e4 100644
--- a/include/configs/Total5200.h
+++ b/include/configs/Total5200.h
@@ -41,6 +41,7 @@
  */
 
 #define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* (more precisely a MPC5200 CPU) */
 #define CONFIG_TOTAL5200	1	/* ... on Total5200 board */
 
 #define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
@@ -73,7 +74,6 @@
 #define CONFIG_SPLASH_SCREEN
 
 
-#ifdef CONFIG_MPC5200	/* MGT5100 PCI is not supported yet. */
 /*
  * PCI Mapping:
  * 0x40000000 - 0x4fffffff - PCI Memory
@@ -98,12 +98,6 @@
 #define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 #define CONFIG_NS8382X		1
 
-#else	/* MGT5100 */
-
-#define CONFIG_MII		1
-
-#endif
-
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -127,9 +121,7 @@
  */
 #include <config_cmd_default.h>
 
-#if defined(CONFIG_MPC5200)
-    #define CONFIG_CMD_PCI
-#endif
+#define CONFIG_CMD_PCI
 
 #define CONFIG_CMD_BMP
 #define CONFIG_CMD_EEPROM
@@ -176,12 +168,10 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#if defined(CONFIG_MPC5200)
 /*
  * IPB Bus clocking configuration.
  */
 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-#endif
 
 /*
  * I2C configuration
@@ -326,17 +316,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
-
-#if defined (CONFIG_MGT5100)
-#   define CONFIG_BOARD_EARLY_INIT_R	/* switch from CS_BOOT to CS0 */
-#endif
 
 #if CONFIG_TOTAL5200_REV==1
 #   define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
diff --git a/include/configs/aev.h b/include/configs/aev.h
index 2b4826d90e..98958a6237 100644
--- a/include/configs/aev.h
+++ b/include/configs/aev.h
@@ -362,13 +362,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
new file mode 100644
index 0000000000..7c8281cae7
--- /dev/null
+++ b/include/configs/astro_mcf5373l.h
@@ -0,0 +1,400 @@
+/*
+ * Configuration settings for the Sentec Cobra Board.
+ *
+ * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * configuration for ASTRO "Urmel" board.
+ * Originating from Cobra5272 configuration, messed up by
+ * Wolfgang Wegner <w.wegner@astro-kom.de>
+ * Please do not bother the original author with bug reports
+ * concerning this file.
+ */
+
+#ifndef _CONFIG_ASTRO_MCF5373L_H
+#define _CONFIG_ASTRO_MCF5373L_H
+
+/*
+ * set the card type to actually compile for; either of
+ * the possibilities listed below has to be used!
+ */
+#define CONFIG_ASTRO_V532	1
+
+#if CONFIG_ASTRO_V532
+#define ASTRO_ID	0xF8
+#elif CONFIG_ASTRO_V512
+#define ASTRO_ID	0xFA
+#elif CONFIG_ASTRO_TWIN7S2
+#define ASTRO_ID	0xF9
+#elif CONFIG_ASTRO_V912
+#define ASTRO_ID	0xFC
+#elif CONFIG_ASTRO_COFDMDUOS2
+#define ASTRO_ID	0xFB
+#else
+#error No card type defined!
+#endif
+
+/*
+ * Define processor
+ * possible values for Urmel board: only Coldfire M5373 processor supported
+ * (please do not change)
+ */
+
+/* it seems not clear yet which processor defines we should use */
+#define CONFIG_MCF537x			/* define processor family */
+#define CONFIG_MCF532x			/* define processor family */
+#define CONFIG_M5373			/* define processor type */
+#define CONFIG_ASTRO5373L		/* define board type */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+/*
+ * CONFIG_MK_RAM defines if u-boot is loaded via BDM (or started from
+ * a different bootloader that has already performed RAM setup) or
+ * started directly from flash, which is the regular case for production
+ * boards.
+ */
+#ifdef CONFIG_MK_RAM
+#define CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_TEXT_BASE		0x40020000
+#define ENABLE_JFFS	0
+#else
+#define CONFIG_TEXT_BASE		0x00000000
+#define ENABLE_JFFS	1
+#endif
+
+/* Define which commmands should be available at u-boot command prompt */
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_XIMG
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#if ENABLE_JFFS
+#define CONFIG_CMD_JFFS2
+#endif
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C			/* I2C with hw support */
+#undef CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SPEED		80000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x58000
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+/*
+ * Defines processor clock - important for correct timings concerning serial
+ * interface etc.
+ * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms
+ */
+
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CLK			80000000
+#define CONFIG_SYS_CPU_CLK		(CONFIG_SYS_CLK * 3)
+#define CONFIG_SYS_SDRAM_SIZE		32		/* SDRAM size in MB */
+
+#define CONFIG_SYS_CORE_SRAM_SIZE	0x8000
+#define CONFIG_SYS_CORE_SRAM		0x80000000
+
+#define CONFIG_SYS_UNIFY_CACHE
+
+/*
+ * Define baudrate for UART1 (console output, tftp, ...)
+ * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
+ * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected
+ * in u-boot command interface
+ */
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(2)
+#define CONFIG_SYS_UART2_ALT3_GPIO
+
+/*
+ * Watchdog configuration; Watchdog is disabled for running from RAM
+ * and set to highest possible value else. Beware there is no check
+ * in the watchdog code to validate the timeout value set here!
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 3355	/* timeout in milliseconds */
+#endif
+
+/*
+ * Configuration for environment
+ * Environment is located in the last sector of the flash
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_ENV_OFFSET		0x1FF8000
+#define CONFIG_ENV_SECT_SIZE		0x8000
+#define CONFIG_ENV_IS_IN_FLASH		1
+#else
+/*
+ * environment in RAM - This is used to use a single PC-based application
+ * to load an image, load U-Boot, load an environment and then start U-Boot
+ * to execute the commands from the environment. Feedback is done via setting
+ * and reading memory locations.
+ */
+#define CONFIG_ENV_ADDR		0x40060000
+#define CONFIG_ENV_SECT_SIZE	0x8000
+#define CONFIG_ENV_IS_IN_FLASH	1
+#endif
+
+/* here we put our FPGA configuration... */
+#define CONFIG_MISC_INIT_R	1
+
+/* Define user parameters that have to be customized most likely */
+
+/* AUTOBOOT settings - booting images automatically by u-boot after power on */
+
+/*
+ * used for autoboot, delay in seconds u-boot will wait before starting
+ * defined (auto-)boot command, setting to -1 disables delay, setting to
+ * 0 will too prevent access to u-boot command interface: u-boot then has
+ * to be reflashed
+ * beware - watchdog is not serviced during autoboot delay time!
+ */
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_BOOTDELAY	1
+#else
+#define CONFIG_BOOTDELAY	1
+#endif
+
+/*
+ * The following settings will be contained in the environment block ; if you
+ * want to use a neutral environment all those settings can be manually set in
+ * u-boot: 'set' command
+ */
+
+#define _QUOTEME(x)	#x
+#define QUOTEME(x)	_QUOTEME(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS			\
+	"loaderversion=11\0"				\
+	"card_id="QUOTEME(ASTRO_ID)"\0"			\
+	"alterafile=0\0"				\
+	"xilinxfile=0\0"				\
+	"xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\
+		"fpga load 0 0x41000000 $filesize\0" \
+	"alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\
+		"fpga load 1 0x41000000 $filesize\0" \
+	"env_default=1\0"				\
+	"env_check=if test $env_default -eq 1;"\
+		" then setenv env_default 0;saveenv;fi\0"
+
+/*
+ * "update" is a non-standard command that has to be supplied
+ * by external update.c; This is not included in mainline because
+ * it needs non-blocking CFI routines.
+ */
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_BOOTCOMMAND	""	/* no autoboot in this case */
+#else
+#if CONFIG_ASTRO_V532
+#define CONFIG_BOOTCOMMAND	"protect off 0x80000 0x1ffffff;run env_check;"\
+				"run xilinxload&&run alteraload&&bootm 0x80000;"\
+				"update;reset"
+#else
+#define CONFIG_BOOTCOMMAND	"protect off 0x80000 0x1ffffff;run env_check;"\
+				"run xilinxload&&bootm 0x80000;update;reset"
+#endif
+#endif
+
+/* default bootargs that are considered during boot */
+#define CONFIG_BOOTARGS		" console=ttyS2,115200 rootfstype=romfs"\
+				" loaderversion=$loaderversion"
+
+#define CONFIG_SYS_PROMPT	"URMEL > "
+
+/* default RAM address for user programs */
+#define CONFIG_SYS_LOAD_ADDR	0x20000
+
+#define CONFIG_SYS_LONGHELP
+
+#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024
+#else
+#define CONFIG_SYS_CBSIZE		256
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_FPGA_COUNT	1
+#define CONFIG_FPGA
+#define	CONFIG_FPGA_XILINX
+#define	CONFIG_FPGA_SPARTAN3
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_WAIT		1000
+
+/* End of user parameters to be customized */
+
+/* Defines memory range for test */
+
+#define CONFIG_SYS_MEMTEST_START	0x40020000
+#define CONFIG_SYS_MEMTEST_END		0x41ffffff
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/* Base register address */
+
+#define CONFIG_SYS_MBAR		0xFC000000	/* Register Base Addrs */
+
+/* System Conf. Reg. & System Protection Reg. */
+
+#define CONFIG_SYS_SCR		0x0003;
+#define CONFIG_SYS_SPR		0xffff;
+
+/*
+ * Definitions for initial stack pointer and data area (in internal SRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_END		0x8000
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+
+/*
+ * Chipselect bank definitions
+ *
+ * CS0 - Flash 32MB (first 16MB)
+ * CS1 - Flash 32MB (second half)
+ * CS2 - FPGA
+ * CS3 - FPGA
+ * CS4 - unused
+ * CS5 - unused
+ */
+#define CONFIG_SYS_CS0_BASE		0
+#define CONFIG_SYS_CS0_MASK		0x00ff0001
+#define CONFIG_SYS_CS0_CTRL		0x00001fc0
+
+#define CONFIG_SYS_CS1_BASE		0x01000000
+#define CONFIG_SYS_CS1_MASK		0x00ff0001
+#define CONFIG_SYS_CS1_CTRL		0x00001fc0
+
+#define CONFIG_SYS_CS2_BASE		0x20000000
+#define CONFIG_SYS_CS2_MASK		0x00ff0001
+#define CONFIG_SYS_CS2_CTRL		0x0000fec0
+
+#define CONFIG_SYS_CS3_BASE		0x21000000
+#define CONFIG_SYS_CS3_MASK		0x00ff0001
+#define CONFIG_SYS_CS3_CTRL		0x0000fec0
+
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+
+#ifdef	CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_TEXT_BASE
+#else
+/* This is mainly used during relocation in start.S */
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64 * 1024)
+/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + \
+						(CONFIG_SYS_SDRAM_SIZE << 20))
+
+/* FLASH organization */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	259
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
+
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
+#define CONFIG_SYS_FLASH_SIZE		0x2000000
+#define CONFIG_SYS_FLASH_PROTECTION	1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_FLASH_CFI_NONBLOCK	1
+
+#if ENABLE_JFFS
+/* JFFS Partition offset set */
+#define CONFIG_SYS_JFFS2_FIRST_BANK    0
+#define CONFIG_SYS_JFFS2_NUM_BANKS     1
+/* 512k reserved for u-boot */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR  0x40
+#endif
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
+#endif	/* _CONFIG_ASTRO_MCF5373L_H */
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 1c3ea23c77..330e3ac667 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -331,6 +331,19 @@ from which user programs will be started */
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  *
diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h
index 52df16af14..f7290d6eb4 100644
--- a/include/configs/cpci5200.h
+++ b/include/configs/cpci5200.h
@@ -59,7 +59,6 @@
 #define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#ifdef CONFIG_MPC5200		/* MPC5100 PCI is not supported yet. */
 /*
  * PCI Mapping:
  * 0x40000000 - 0x4fffffff - PCI Memory
@@ -90,8 +89,6 @@
 #define CONFIG_NS8382X		1
 #endif
 
-#endif
-
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -169,8 +166,6 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_vxworks0"
 
-#if defined(CONFIG_MPC5200)
-
 #define CONFIG_RTC_M48T35A	1	/* ST Electronics M48 timekeeper */
 #define CONFIG_SYS_NVRAM_BASE_ADDR	0xfd010000
 #define CONFIG_SYS_NVRAM_SIZE		32*1024
@@ -179,7 +174,6 @@
  * IPB Bus clocking configuration.
  */
 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-#endif
 /*
  * I2C configuration
  */
@@ -303,13 +297,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h
index a81527ebed..f9cdcbc3ce 100644
--- a/include/configs/hmi1001.h
+++ b/include/configs/hmi1001.h
@@ -261,13 +261,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/idmr.h b/include/configs/idmr.h
index 841affb7cc..61e3bad4f3 100644
--- a/include/configs/idmr.h
+++ b/include/configs/idmr.h
@@ -224,6 +224,19 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /* Port configuration */
 #define CONFIG_SYS_FECI2C		0xF0
 
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 14f7826705..c5b1565e34 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -366,13 +366,8 @@ static inline void tws_data_config_output(unsigned output)
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h
index d0cb1e1d60..6903b36146 100644
--- a/include/configs/ipek01.h
+++ b/include/configs/ipek01.h
@@ -324,13 +324,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h
index b29ef9b655..d25e093ac6 100644
--- a/include/configs/manroland/mpc5200-common.h
+++ b/include/configs/manroland/mpc5200-common.h
@@ -170,13 +170,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h
index 4a93b58885..73405eabb9 100644
--- a/include/configs/mecp5200.h
+++ b/include/configs/mecp5200.h
@@ -63,9 +63,6 @@
 #endif
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-
-#ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
-
 #define CONFIG_MII
 #if 0 /* test-only !!! */
 #define CONFIG_NET_MULTI	1
@@ -74,10 +71,6 @@
 #define CONFIG_NS8382X		1
 #endif
 
-#else	/* MPC5100 */
-
-#endif
-
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -152,12 +145,10 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_vxworks0"
 
-#if defined(CONFIG_MPC5200)
 /*
  * IPB Bus clocking configuration.
  */
 #undef CONFIG_SYS_IPBSPEED_133			/* define for 133MHz speed */
-#endif
 /*
  * I2C configuration
  */
@@ -288,13 +279,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index 18e7cc2a9c..bdc0f7944a 100644
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -138,7 +138,6 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#if defined(CONFIG_MPC5200)
 /*
  * IPB Bus clocking configuration.
  */
@@ -154,7 +153,6 @@
  */
 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
-#endif
 
 /*
  * I2C configuration
@@ -276,13 +274,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h
index 8ca55d78ec..80a0bc609a 100644
--- a/include/configs/pf5200.h
+++ b/include/configs/pf5200.h
@@ -61,7 +61,6 @@
 #endif
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#ifdef CONFIG_MPC5200		/* MPC5100 PCI is not supported yet. */
 /*
  * PCI Mapping:
  * 0x40000000 - 0x4fffffff - PCI Memory
@@ -87,7 +86,6 @@
 #define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
 #define CONFIG_NS8382X		1
 #endif
-#endif
 
 /* Partitions */
 #define CONFIG_MAC_PARTITION
@@ -121,9 +119,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IDE
 
-#ifdef CONFIG_MPC5200
 #define CONFIG_CMD_PCI
-#endif
 
 
 #if (TEXT_BASE == 0xFF000000)	/* Boot low with 16 MB Flash */
@@ -166,12 +162,10 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_vxworks0"
 
-#if defined(CONFIG_MPC5200)
 /*
  * IPB Bus clocking configuration.
  */
 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-#endif
 /*
  * I2C configuration
  */
@@ -289,13 +283,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h
index 5a2ef3aa8c..060026bb64 100644
--- a/include/configs/smmaco4.h
+++ b/include/configs/smmaco4.h
@@ -358,13 +358,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
index 27dda253fb..d377e199d8 100644
--- a/include/configs/spieval.h
+++ b/include/configs/spieval.h
@@ -438,13 +438,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index 92bcdb33fb..d462ed0f1e 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -170,12 +170,10 @@
 
 #define CONFIG_BOOTCOMMAND	"run net_nfs"
 
-#if defined(CONFIG_MPC5200)
 /*
  * IPB Bus clocking configuration.
  */
 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK			/* define for 133MHz speed */
-#endif
 
 /*
  * I2C configuration
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 0a9dd0dd84..a3d5f8cbfe 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -81,5 +81,7 @@ int fdt_resize(void *blob);
 
 int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size);
 
+void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
+
 #endif /* ifdef CONFIG_OF_LIBFDT */
 #endif /* ifndef __FDT_SUPPORT_H */
diff --git a/include/i2c.h b/include/i2c.h
index 31088b675a..d828964256 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -127,8 +127,6 @@ typedef struct _mux_device {
 	struct _mux_device	*next;
 } I2C_MUX_DEVICE;
 
-int	i2c_mux_add_device(I2C_MUX_DEVICE *dev);
-
 I2C_MUX_DEVICE	*i2c_mux_search_device(int id);
 I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf);
 int i2x_mux_select_mux(int bus);
diff --git a/include/jffs2/load_kernel.h b/include/jffs2/load_kernel.h
index 8b2720e951..906eb3d3cd 100644
--- a/include/jffs2/load_kernel.h
+++ b/include/jffs2/load_kernel.h
@@ -78,5 +78,6 @@ struct mtdids {
 extern int mtdparts_init(void);
 extern int find_dev_and_part(const char *id, struct mtd_device **dev,
 				u8 *part_num, struct part_info **part);
+extern struct mtd_device *device_find(u8 type, u8 num);
 
 #endif /* load_kernel_h */
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
index 4dcf90c037..2d343c7b08 100644
--- a/include/mpc5xxx.h
+++ b/include/mpc5xxx.h
@@ -1,7 +1,7 @@
 /*
  * include/asm-ppc/mpc5xxx.h
  *
- * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx
+ * Prototypes, etc. for the Motorola MPC5xxx
  * embedded cpu chips
  *
  * 2003 (c) MontaVista, Software, Inc.
@@ -33,24 +33,15 @@
 #include <asm/types.h>
 
 /* Processor name */
-#if defined(CONFIG_MPC5200)
 #define CPU_ID_STR	"MPC5200"
-#elif defined(CONFIG_MGT5100)
-#define CPU_ID_STR	"MGT5100"
-#endif
 
 /* Exception offsets (PowerPC standard) */
 #define EXC_OFF_SYS_RESET	0x0100
 #define _START_OFFSET		EXC_OFF_SYS_RESET
 
 /* useful macros for manipulating CSx_START/STOP */
-#if defined(CONFIG_MGT5100)
-#define START_REG(start)	((start) >> 15)
-#define STOP_REG(start, size)	(((start) + (size) - 1) >> 15)
-#elif defined(CONFIG_MPC5200)
 #define START_REG(start)	((start) >> 16)
 #define STOP_REG(start, size)	(((start) + (size) - 1) >> 16)
-#endif
 
 /* Internal memory map */
 
@@ -70,21 +61,12 @@
 #define MPC5XXX_BOOTCS_STOP	(CONFIG_SYS_MBAR + 0x0050)
 #define MPC5XXX_ADDECR		(CONFIG_SYS_MBAR + 0x0054)
 
-#if defined(CONFIG_MGT5100)
-#define MPC5XXX_SDRAM_START	(CONFIG_SYS_MBAR + 0x0034)
-#define MPC5XXX_SDRAM_STOP	(CONFIG_SYS_MBAR + 0x0038)
-#define MPC5XXX_PCI1_START	(CONFIG_SYS_MBAR + 0x003c)
-#define MPC5XXX_PCI1_STOP	(CONFIG_SYS_MBAR + 0x0040)
-#define MPC5XXX_PCI2_START	(CONFIG_SYS_MBAR + 0x0044)
-#define MPC5XXX_PCI2_STOP	(CONFIG_SYS_MBAR + 0x0048)
-#elif defined(CONFIG_MPC5200)
 #define MPC5XXX_CS6_START	(CONFIG_SYS_MBAR + 0x0058)
 #define MPC5XXX_CS6_STOP	(CONFIG_SYS_MBAR + 0x005c)
 #define MPC5XXX_CS7_START	(CONFIG_SYS_MBAR + 0x0060)
 #define MPC5XXX_CS7_STOP	(CONFIG_SYS_MBAR + 0x0064)
 #define MPC5XXX_SDRAM_CS0CFG	(CONFIG_SYS_MBAR + 0x0034)
 #define MPC5XXX_SDRAM_CS1CFG	(CONFIG_SYS_MBAR + 0x0038)
-#endif
 
 #define MPC5XXX_SDRAM		(CONFIG_SYS_MBAR + 0x0100)
 #define MPC5XXX_CDM		(CONFIG_SYS_MBAR + 0x0200)
@@ -99,18 +81,12 @@
 #define MPC5XXX_SDMA		(CONFIG_SYS_MBAR + 0x1200)
 #define MPC5XXX_XLBARB		(CONFIG_SYS_MBAR + 0x1f00)
 
-#if defined(CONFIG_MGT5100)
-#define	MPC5XXX_PSC1		(CONFIG_SYS_MBAR + 0x2000)
-#define	MPC5XXX_PSC2		(CONFIG_SYS_MBAR + 0x2400)
-#define	MPC5XXX_PSC3		(CONFIG_SYS_MBAR + 0x2800)
-#elif defined(CONFIG_MPC5200)
 #define	MPC5XXX_PSC1		(CONFIG_SYS_MBAR + 0x2000)
 #define	MPC5XXX_PSC2		(CONFIG_SYS_MBAR + 0x2200)
 #define	MPC5XXX_PSC3		(CONFIG_SYS_MBAR + 0x2400)
 #define	MPC5XXX_PSC4		(CONFIG_SYS_MBAR + 0x2600)
 #define	MPC5XXX_PSC5		(CONFIG_SYS_MBAR + 0x2800)
 #define	MPC5XXX_PSC6		(CONFIG_SYS_MBAR + 0x2c00)
-#endif
 
 #define	MPC5XXX_FEC		(CONFIG_SYS_MBAR + 0x3000)
 #define MPC5XXX_ATA             (CONFIG_SYS_MBAR + 0x3A00)
@@ -118,22 +94,14 @@
 #define MPC5XXX_I2C1		(CONFIG_SYS_MBAR + 0x3D00)
 #define MPC5XXX_I2C2		(CONFIG_SYS_MBAR + 0x3D40)
 
-#if defined(CONFIG_MGT5100)
-#define MPC5XXX_SRAM		(CONFIG_SYS_MBAR + 0x4000)
-#define MPC5XXX_SRAM_SIZE	(8*1024)
-#elif defined(CONFIG_MPC5200)
 #define MPC5XXX_SRAM		(CONFIG_SYS_MBAR + 0x8000)
 #define MPC5XXX_SRAM_SIZE	(16*1024)
-#endif
 
 /* SDRAM Controller */
 #define MPC5XXX_SDRAM_MODE	(MPC5XXX_SDRAM + 0x0000)
 #define MPC5XXX_SDRAM_CTRL	(MPC5XXX_SDRAM + 0x0004)
 #define MPC5XXX_SDRAM_CONFIG1	(MPC5XXX_SDRAM + 0x0008)
 #define MPC5XXX_SDRAM_CONFIG2	(MPC5XXX_SDRAM + 0x000c)
-#if defined(CONFIG_MGT5100)
-#define MPC5XXX_SDRAM_XLBSEL	(MPC5XXX_SDRAM + 0x0010)
-#endif
 #define MPC5XXX_SDRAM_SDELAY	(MPC5XXX_SDRAM + 0x0090)
 
 /* Clock Distribution Module */
@@ -155,19 +123,15 @@
 #define MPC5XXX_BOOTCS_CFG	MPC5XXX_CS0_CFG
 #define MPC5XXX_CS_CTRL		(MPC5XXX_LPB + 0x0018)
 #define MPC5XXX_CS_STATUS	(MPC5XXX_LPB + 0x001c)
-#if defined(CONFIG_MPC5200)
 #define MPC5XXX_CS6_CFG		(MPC5XXX_LPB + 0x0020)
 #define MPC5XXX_CS7_CFG		(MPC5XXX_LPB + 0x0024)
 #define MPC5XXX_CS_BURST	(MPC5XXX_LPB + 0x0028)
 #define MPC5XXX_CS_DEADCYCLE	(MPC5XXX_LPB + 0x002c)
-#endif
 
-#if defined(CONFIG_MPC5200)
 /* XLB Arbiter registers */
 #define MPC5XXX_XLBARB_CFG		(MPC5XXX_XLBARB + 0x40)
 #define MPC5XXX_XLBARB_MPRIEN	(MPC5XXX_XLBARB + 0x64)
 #define MPC5XXX_XLBARB_MPRIVAL	(MPC5XXX_XLBARB + 0x68)
-#endif
 
 /* GPIO registers */
 #define MPC5XXX_GPS_PORT_CONFIG	(MPC5XXX_GPIO + 0x0000)
@@ -242,14 +206,6 @@
 #define MPC5XXX_PCI_CFG		(MPC5XXX_PCI + 0x0c)
 #define MPC5XXX_PCI_BAR0	(MPC5XXX_PCI + 0x10)
 #define MPC5XXX_PCI_BAR1	(MPC5XXX_PCI + 0x14)
-#if defined(CONFIG_MGT5100)
-#define MPC5XXX_PCI_CTRL	(MPC5XXX_PCI + 0x68)
-#define MPC5XXX_PCI_VALMSKR	(MPC5XXX_PCI + 0x6c)
-#define MPC5XXX_PCI_VALMSKW	(MPC5XXX_PCI + 0x70)
-#define MPC5XXX_PCI_SUBW1	(MPC5XXX_PCI + 0x74)
-#define MPC5XXX_PCI_SUBW2	(MPC5XXX_PCI + 0x78)
-#define MPC5XXX_PCI_WINCOMMAND	(MPC5XXX_PCI + 0x7c)
-#elif defined(CONFIG_MPC5200)
 #define MPC5XXX_PCI_GSCR	(MPC5XXX_PCI + 0x60)
 #define MPC5XXX_PCI_TBATR0	(MPC5XXX_PCI + 0x64)
 #define MPC5XXX_PCI_TBATR1	(MPC5XXX_PCI + 0x68)
@@ -262,7 +218,6 @@
 #define MPC5XXX_PCI_ISR		(MPC5XXX_PCI + 0x88)
 #define MPC5XXX_PCI_ARB		(MPC5XXX_PCI + 0x8c)
 #define MPC5XXX_PCI_CAR		(MPC5XXX_PCI + 0xf8)
-#endif
 
 /* Interrupt Controller registers */
 #define MPC5XXX_ICTL_PER_MASK	(MPC5XXX_ICTL + 0x0000)
@@ -495,31 +450,16 @@ struct mpc5xxx_mmap_ctl {
 	volatile u32	cs4_stop;
 	volatile u32	cs5_start;	/* 0x002c */
 	volatile u32	cs5_stop;
-#if defined(CONFIG_MGT5100)
-	volatile u32	sdram_start;	/* 0x0034 */
-	volatile u32	sdram_stop;	/* 0x0038 */
-	volatile u32	pci1_start;	/* 0x003c */
-	volatile u32	pci1_stop;	/* 0x0040 */
-	volatile u32	pci2_start;	/* 0x0044 */
-	volatile u32	pci2_stop;	/* 0x0048 */
-#elif defined(CONFIG_MPC5200)
 	volatile u32	sdram0;		/* 0x0034 */
 	volatile u32	sdram1;		/* 0x0038 */
 	volatile u32	dummy1[4];	/* 0x003c */
-#endif
 	volatile u32	boot_start;	/* 0x004c */
 	volatile u32	boot_stop;
-#if defined(CONFIG_MGT5100)
-	volatile u32	addecr;		/* 0x0054 */
-#elif defined(CONFIG_MPC5200)
 	volatile u32	ipbi_ws_ctrl;	/* 0x0054 */
-#endif
-#if defined(CONFIG_MPC5200)
 	volatile u32	cs6_start;	/* 0x0058 */
 	volatile u32	cs6_stop;
 	volatile u32	cs7_start;	/* 0x0060 */
 	volatile u32	cs7_stop;
-#endif
 };
 
 /* Clock distribution module */
@@ -546,12 +486,7 @@ struct mpc5xxx_sdram {
 	volatile u32	ctrl;
 	volatile u32	config1;
 	volatile u32	config2;
-#if defined(CONFIG_MGT5100)
-	volatile u32	xlbsel;
-	volatile u32    dummy[31];
-#else
 	volatile u32	dummy[32];
-#endif
 	volatile u32	sdelay;
 };
 
@@ -564,12 +499,10 @@ struct mpc5xxx_lpb {
 	volatile u32	cs5_cfg;
 	volatile u32	cs_ctrl;
 	volatile u32	cs_status;
-#if defined(CONFIG_MPC5200)
 	volatile u32	cs6_cfg;
 	volatile u32	cs7_cfg;
 	volatile u32	cs_burst;
 	volatile u32	cs_deadcycle;
-#endif
 };
 
 
diff --git a/include/mtd_node.h b/include/mtd_node.h
new file mode 100644
index 0000000000..5aae0859da
--- /dev/null
+++ b/include/mtd_node.h
@@ -0,0 +1,11 @@
+#ifndef _NODE_INFO
+#define _NODE_INFO
+
+/*
+ * Info we use to search for a flash node in DTB.
+ */
+struct node_info {
+	const char *compat;	/* compatible string */
+	int type;		/* mtd flash type */
+};
+#endif
diff --git a/include/post.h b/include/post.h
index 9fcd3cec2f..ff83bce6b4 100644
--- a/include/post.h
+++ b/include/post.h
@@ -53,6 +53,11 @@
 
 #define POST_FAIL_SAVE		0x80
 
+#define POST_BEFORE		1
+#define POST_AFTER		0
+#define POST_PASSED		1
+#define POST_FAILED		0
+
 #ifndef	__ASSEMBLY__
 
 struct post_test {
diff --git a/include/spartan3.h b/include/spartan3.h
index 30b1c2d62d..d5a589d099 100644
--- a/include/spartan3.h
+++ b/include/spartan3.h
@@ -57,6 +57,7 @@ typedef struct {
 	Xilinx_done_fn	done;
 	Xilinx_wr_fn	wr;
 	Xilinx_post_fn	post;
+	Xilinx_bwr_fn	bwr; /* block write function */
 } Xilinx_Spartan3_Slave_Serial_fns;
 
 /* Device Image Sizes
diff --git a/include/xilinx.h b/include/xilinx.h
index d0799bc572..2cb2e5b6aa 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -100,5 +100,6 @@ typedef int (*Xilinx_busy_fn)( int cookie );
 typedef int (*Xilinx_abort_fn)( int cookie );
 typedef int (*Xilinx_pre_fn)( int cookie );
 typedef int (*Xilinx_post_fn)( int cookie );
+typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie );
 
 #endif  /* _XILINX_H_ */
diff --git a/lib_m68k/cache.c b/lib_m68k/cache.c
index 84fb6c2fbc..ed881783f1 100644
--- a/lib_m68k/cache.c
+++ b/lib_m68k/cache.c
@@ -22,8 +22,129 @@
  */
 
 #include <common.h>
+#include <asm/immap.h>
+#include <asm/cache.h>
 
-void flush_cache (ulong start_addr, ulong size)
+volatile int *cf_icache_status = (int *)ICACHE_STATUS;
+volatile int *cf_dcache_status = (int *)DCACHE_STATUS;
+
+void flush_cache(ulong start_addr, ulong size)
 {
 	/* Must be implemented for all M68k processors with copy-back data cache */
 }
+
+int icache_status(void)
+{
+	return *cf_icache_status;
+}
+
+int dcache_status(void)
+{
+	return *cf_dcache_status;
+}
+
+void icache_enable(void)
+{
+	icache_invalid();
+
+	*cf_icache_status = 1;
+
+#ifdef CONFIG_CF_V4
+	__asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2));
+	__asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3));
+#elif defined(CONFIG_CF_V4e)
+	__asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6));
+	__asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7));
+#else
+	__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
+	__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
+#endif
+
+	__asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR));
+}
+
+void icache_disable(void)
+{
+	u32 temp = 0;
+
+	*cf_icache_status = 0;
+	icache_invalid();
+
+#ifdef CONFIG_CF_V4
+	__asm__ __volatile__("movec %0, %%acr2"::"r"(temp));
+	__asm__ __volatile__("movec %0, %%acr3"::"r"(temp));
+#elif defined(CONFIG_CF_V4e)
+	__asm__ __volatile__("movec %0, %%acr6"::"r"(temp));
+	__asm__ __volatile__("movec %0, %%acr7"::"r"(temp));
+#else
+	__asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
+	__asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
+
+#endif
+}
+
+void icache_invalid(void)
+{
+	u32 temp;
+
+	temp = CONFIG_SYS_ICACHE_INV;
+	if (*cf_icache_status)
+		temp |= CONFIG_SYS_CACHE_ICACR;
+
+	__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
+}
+
+/*
+ * data cache only for ColdFire V4 such as MCF547x_8x, MCF5445x
+ * the dcache will be dummy in ColdFire V2 and V3
+ */
+void dcache_enable(void)
+{
+	dcache_invalid();
+	*cf_dcache_status = 1;
+
+#ifdef CONFIG_CF_V4
+	__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
+	__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
+#elif defined(CONFIG_CF_V4e)
+	__asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4));
+	__asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5));
+
+#endif
+
+	__asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR));
+}
+
+void dcache_disable(void)
+{
+	u32 temp = 0;
+
+	*cf_dcache_status = 0;
+	dcache_invalid();
+
+	__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
+
+#ifdef CONFIG_CF_V4
+	__asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
+	__asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
+#elif defined(CONFIG_CF_V4e)
+	__asm__ __volatile__("movec %0, %%acr4"::"r"(temp));
+	__asm__ __volatile__("movec %0, %%acr5"::"r"(temp));
+
+#endif
+}
+
+void dcache_invalid(void)
+{
+#ifdef CONFIG_CF_V4
+	u32 temp;
+
+	temp = CONFIG_SYS_DCACHE_INV;
+	if (*cf_dcache_status)
+		temp |= CONFIG_SYS_CACHE_DCACR;
+	if (*cf_icache_status)
+		temp |= CONFIG_SYS_CACHE_ICACR;
+
+	__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
+#endif
+}
diff --git a/post/post.c b/post/post.c
index b29eb87fc2..00e835325c 100644
--- a/post/post.c
+++ b/post/post.c
@@ -231,6 +231,12 @@ static void post_get_flags (int *test_flags)
 	}
 }
 
+void __show_post_progress (unsigned int test_num, int before, int result)
+{
+}
+void show_post_progress (unsigned int, int, int)
+			__attribute__((weak, alias("__show_post_progress")));
+
 static int post_run_single (struct post_test *test,
 				int test_flags, int flags, unsigned int i)
 {
@@ -248,13 +254,18 @@ static int post_run_single (struct post_test *test,
 			if (test_flags & POST_PREREL)
 				post_log_mark_start ( test->testid );
 			else
-			post_log ("POST %s ", test->cmd);
+				post_log ("POST %s ", test->cmd);
 		}
 
+		show_post_progress(i, POST_BEFORE, POST_FAILED);
+
 		if (test_flags & POST_PREREL) {
-			if ((*test->test) (flags) == 0)
+			if ((*test->test) (flags) == 0) {
 				post_log_mark_succ ( test->testid );
+				show_post_progress(i, POST_AFTER, POST_PASSED);
+			}
 			else {
+				show_post_progress(i, POST_AFTER, POST_FAILED);
 				if (test_flags & POST_CRITICAL)
 					gd->flags |= GD_FLG_POSTFAIL;
 				if (test_flags & POST_STOP)
@@ -264,6 +275,7 @@ static int post_run_single (struct post_test *test,
 		if ((*test->test) (flags) != 0) {
 			post_log ("FAILED\n");
 			show_boot_progress (-32);
+			show_post_progress(i, POST_AFTER, POST_FAILED);
 			if (test_flags & POST_CRITICAL)
 				gd->flags |= GD_FLG_POSTFAIL;
 			if (test_flags & POST_STOP)
@@ -271,6 +283,7 @@ static int post_run_single (struct post_test *test,
 		}
 		else
 			post_log ("PASSED\n");
+			show_post_progress(i, POST_AFTER, POST_PASSED);
 		}
 
 		if ((test_flags & POST_REBOOT) && !(flags & POST_MANUAL)) {