diff options
| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-04-28 18:33:57 +0200 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2017-05-10 13:37:21 -0600 |
| commit | ffc1fac549d72ce85205dcdde9af9dfe0f04fd76 (patch) | |
| tree | d1555c0d193ff6282b833e704db825b49d4c8348 | |
| parent | e92e58035062930fcbcb1861cc92f512bde4067b (diff) | |
rockchip: clk: rk3399: allow requests for HDMI clocks
This allows requests (via the DTS) for PCLK_HDMI_CTRL/PCLK_VIO_GRF,
which are clock gates in the HDMI output path for the RK3399.
As these are enabled by default (i.e. after reset), we don't implement
any logic to actively open/close these clock gates and simply assume
that their reset-default has not been changed.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3399.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 10db46e400..026ed4dde7 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -882,6 +882,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case SCLK_UART0: case SCLK_UART2: return 24000000; + break; + case PCLK_HDMI_CTRL: + break; case DCLK_VOP0: case DCLK_VOP1: break; @@ -922,6 +925,10 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SPI0...SCLK_SPI5: ret = rk3399_spi_set_clk(priv->cru, clk->id, rate); break; + case PCLK_HDMI_CTRL: + case PCLK_VIO_GRF: + /* the PCLK gates for video are enabled by default */ + break; case DCLK_VOP0: case DCLK_VOP1: ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); |