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| author | David Wu <david.wu@rock-chips.com> | 2017-09-20 14:35:44 +0800 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-10-01 00:33:30 +0200 |
| commit | b375d84135e26d5ec5034a515af4df5981785f37 (patch) | |
| tree | db6f8ccbfbd9a202615b86275432e782d3e16fb1 /Kconfig | |
| parent | ef4cf5ae393e4adf532f536d6da97c87f88db230 (diff) | |
rockchip: clk: Add rk3328 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'Kconfig')
0 files changed, 0 insertions, 0 deletions