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authorThierry Reding <treding@nvidia.com>2015-08-20 11:52:14 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2015-10-15 14:46:43 +0200
commitad3d6e88a1a4e6aacc55b39c2bad1528100784c0 (patch)
tree0e6da861d32909eb34dce4f2c20d30d803d0f2ea /Licenses
parent55aa0bed9803b8a5bd3e462fd712741c2e1cff1b (diff)
armv8/mmu: Set bits marked RES1 in TCR
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved but should be written as 1. For EL1, only bit 23 is not reserved, so only write bit 31 as 1. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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