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authorMarek Vasut <marex@denx.de>2020-08-22 22:45:25 +0200
committerPatrick Delaunay <patrick.delaunay@st.com>2020-09-09 15:02:23 +0200
commitb6055945d66d0f4e3b1ecb82af476232067a4ee4 (patch)
tree241e3a77a2e8f85c8d56ab3303360c2bae8bd34e /Licenses
parent43e2d1dd47a7e9b126659dc17a10f351e49bc53b (diff)
ARM: dts: stm32: Adjust PLL4 settings on AV96 again
PLL4Q is supplying both FDCAN and LTDC. In case HDMI is in use, the 50 MHz generated from PLL4Q cannot be divided well enough to produce accurate clock for HDMI pixel clock. Adjust it to generate 74.25 MHz instead. The PLL4P/PLL4R are generating 99 MHz instead of 100 MHz, which is in tolerance for the SDMMC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Gerald Baeza <gerald.baeza@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
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