diff options
| author | Ye Li <ye.li@nxp.com> | 2019-01-07 03:18:06 +0000 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2019-05-03 20:03:41 +0800 |
| commit | 72a89e0da5ac6a4ab929b15a2b656f04f50767f6 (patch) | |
| tree | 311a4c938f6fb4afd4623f8f4179aa75757471f0 /api/api_net.c | |
| parent | b4ee6daad7a2604ca9466b2ba48de86cc27d381f (diff) | |
mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue
When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode,
the output clock rate is half of the internal clock rate.
This patch set the DDR_EN bit first for DDR mode, hardware divide
the usdhc clock automatically, then follow the original sdr clock
setting method.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'api/api_net.c')
0 files changed, 0 insertions, 0 deletions