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| author | Stefano Babic <sbabic@denx.de> | 2014-03-05 12:51:26 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-03-05 12:51:26 +0100 |
| commit | 1ad6364eeb4f578e423081d1748e8a3fdf1ab01d (patch) | |
| tree | f55731737edf1cfd653b21f2ff9d387e6c53ae24 /arch/arc/include/asm/cache.h | |
| parent | 335143c76612a0ae26eef8abeda77641d4f63b50 (diff) | |
| parent | cc07294bc704694ae33db75b25ac557e5917a83f (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'arch/arc/include/asm/cache.h')
| -rw-r--r-- | arch/arc/include/asm/cache.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h new file mode 100644 index 0000000000..16e7568ef0 --- /dev/null +++ b/arch/arc/include/asm/cache.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARC_CACHE_H +#define __ASM_ARC_CACHE_H + +#include <config.h> + +/* + * The current upper bound for ARC L1 data cache line sizes is 128 bytes. + * We use that value for aligning DMA buffers unless the board config has + * specified an alternate cache line size. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 128 +#endif + +#endif /* __ASM_ARC_CACHE_H */ |