diff options
| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2018-01-16 21:52:25 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2018-01-19 17:59:35 +0300 |
| commit | c0e6769a82f79a0fc20baa9257ebd17b1cecf4fa (patch) | |
| tree | 035547cf0052042c0da6c6e375a21910150e7110 /arch/arc | |
| parent | 7897f4e54cefe9525344bec419dae230e4ff9913 (diff) | |
ARC: Invalidate instruction and data caches early on boot
This is useful to make sure no stale data exists in caches after bootloaders.
The worst thing could be some lines of cache were locked in a bootloader
for example during DDR recalibration and never unlocked. This may lead
to really unpredictable issues later down the line.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'arch/arc')
| -rw-r--r-- | arch/arc/lib/start.S | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S index 95d64f9d43..0d72fe71d4 100644 --- a/arch/arc/lib/start.S +++ b/arch/arc/lib/start.S @@ -44,6 +44,14 @@ ENTRY(_start) #endif sr r5, [ARC_AUX_IC_CTRL] + mov r5, 1 + sr r5, [ARC_AUX_IC_IVIC] + ; As per ARC HS databook (see chapter 5.3.3.2) + ; it is required to add 3 NOPs after each write to IC_IVIC. + nop + nop + nop + 1: ; Disable/enable D-cache according to configuration lr r5, [ARC_BCR_DC_BUILD] @@ -57,6 +65,10 @@ ENTRY(_start) #endif sr r5, [ARC_AUX_DC_CTRL] + mov r5, 1 + sr r5, [ARC_AUX_DC_IVDC] + + 1: #ifdef CONFIG_ISA_ARCV2 ; Disable System-Level Cache (SLC) |