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authorTom Rini <trini@konsulko.com>2019-05-19 09:36:48 -0400
committerTom Rini <trini@konsulko.com>2019-05-19 09:36:48 -0400
commitd3d212b6240f75006c18e4c59b3b28d81eedb7d3 (patch)
tree106781344a5074a0e1cc26e8e371016cef0d0570 /arch/arc
parent98b3156b0df4b0df9cb3a0bbfc240d0c4edd2638 (diff)
parent612f6b223d2cb03ae0170d3eadcb78f7b473ecfb (diff)
Merge branch '2019-05-19-master-imports'
- Convert SYS_[DI]CACHE_OFF to Kconfig, introduce SPL variant. - Various bcm96* fixes. - Import include/android_bootloader_message.h from AOSP - Assorted other small fixes.
Diffstat (limited to 'arch/arc')
-rw-r--r--arch/arc/Kconfig22
-rw-r--r--arch/arc/lib/start.S4
2 files changed, 22 insertions, 4 deletions
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 50369d5983..0cb97207db 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -109,12 +109,30 @@ config CPU_BIG_ENDIAN
Build kernel for Big Endian Mode of ARC CPU
config SYS_ICACHE_OFF
- bool "Do not use Instruction Cache"
+ bool "Do not enable icache"
default n
+ help
+ Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default SYS_ICACHE_OFF
+ help
+ Do not enable instruction cache in SPL.
config SYS_DCACHE_OFF
- bool "Do not use Data Cache"
+ bool "Do not enable dcache"
default n
+ help
+ Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default SYS_DCACHE_OFF
+ help
+ Do not enable data cache in SPL.
menuconfig ARC_DBG
bool "ARC debugging"
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index 84959b41bd..8c744f5be7 100644
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -16,7 +16,7 @@ ENTRY(_start)
lr r5, [ARC_BCR_IC_BUILD]
breq r5, 0, 1f ; I$ doesn't exist
lr r5, [ARC_AUX_IC_CTRL]
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
#else
bset r5, r5, 0 ; I$ exists, but is not used
@@ -37,7 +37,7 @@ ENTRY(_start)
breq r5, 0, 1f ; D$ doesn't exist
lr r5, [ARC_AUX_DC_CTRL]
bclr r5, r5, 6 ; Invalidate (discard w/o wback)
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
bclr r5, r5, 0 ; Enable (+Inv)
#else
bset r5, r5, 0 ; Disable (+Inv)