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| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2018-08-21 15:44:50 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2018-09-26 10:15:00 +0200 |
| commit | fbf7fb0f9fe84e7bb24d184d0783944411400f08 (patch) | |
| tree | 44b42704370df141933c169df100245461dec538 /arch/arc | |
| parent | b94a8271cc42086f3f75941c15bba265f409601d (diff) | |
fpga: zynqmp: Modify PL bitstream loading sequence
This patch modifies PL bitstream loading sequence as per
latest Xilfpga which supports all variants of bitstream images
generated from vivado and from bootgen. With this new change in
Xilfpga, uboot doesn't need to validate and swap bitstream as it will
be taken care inside Xilfpga. ZynqMP PL driver now checks for supporting
PMUFW version before skipping the validation and swap sequence as there
can be old PMUFW which doesn't supports this feature. In this case, driver
uses old way of PL bitstream loading sequence.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arc')
0 files changed, 0 insertions, 0 deletions