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authorMarek Vasut <marex@denx.de>2018-05-07 22:22:26 +0200
committerMarek Vasut <marex@denx.de>2018-07-25 00:13:32 +0200
commit64eeb1585428b71e29022e22d1aae86b65b9e052 (patch)
treee81ae5caa33279729457ea7ab0e93ff6c7ef5417 /arch/arm/Kconfig
parent42f4b83b52735d698bf3f3de2665bf6d42db9f1c (diff)
ARM: dts: socfpga: Adjust NAND register layout on Arria10
Adjust the NAND register size on Arria10 to reflect reality. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm/Kconfig')
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